>FIG. 3) connected thereto. In the following description, this conductive layer 110 may be referred to as a conductive layer 110 (SGD). The widths of the plurality of conductive layers 110 (SGD) in the Y-direction are smaller than the widths of the conductive layers 110 (WL) in the Y-direction. The inter-string unit insulating layer SHE is provided between two conductive layers 110 (SGD) adjacent to each other in the Y-direction in one memory block BLK. Each of the plurality of conductive layers 110 (SGD) is electrically independent for each string unit SU.

A conductive layer 100 is provided below the plurality of conductive layers 110. The conductive layer 100 is connected to a lower end of the semiconductor pillar 120. The semiconductor pillar 120 may include, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P), or may include, for example, a metal such as tungsten (W), a conductive layer made of tungsten silicide, or other conductive layers. Further, the insulating layer 101 made of silicon oxide (SiO₂) or the like is provided between the conductive layer 100 and the conductive layer 110.

The conductive layer 100 functions as the source line SL (see FIG. 3). For example, the source line SL is provided in common for all memory blocks BLK in the memory cell array MCA.

The semiconductor pillars 120 are arranged in a predetermined pattern in the X-direction and the Y-direction. The semiconductor pillars 120 function as channel regions of the plurality of memory cells MC and the select transistors STD and STS in one memory string MS (see FIG. 3). The semiconductor pillar 120 contains, for example, polycrystalline silicon (Si). The semiconductor pillar 120 has a substantially bottomed cylindrical shape, and as shown in FIG. 5, for example, an insulating layer 125 made of silicon oxide or the like is provided in the center portion thereof. Further, each of outer peripheral surfaces of the semiconductor pillars 120 is surrounded by the conductive layer 110 and faces the conductive layer 110.

In an upper end portion of the semiconductor pillar 120, an impurity region (not shown) containing N-type impurities such as phosphorus (P) is provided. This impurity region is connected to the bit line BL through a via contact electrode.

In a lower end portion of the semiconductor pillar 120, an impurity region (not shown) containing N-type impurities such as phosphorus (P) is provided. This impurity region is connected to the conductive layer 100.

The gate insulating film 130 has a substantially bottomed cylindrical shape that covers the outer peripheral surface of the semiconductor pillar 120. For example, as shown in FIG. 5, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133, which are stacked between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 contain, for example, silicon oxide (SiO₂). The charge storage film 132 includes a film made of silicon nitride (SiN) or the like capable of accumulating charges. The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape, and extend in the Z-direction along the outer peripheral surface of the semiconductor pillar 120 excluding a contact portion between the semiconductor pillar 120 and the conductive layer 110.

FIG. 5 shows an example in which the gate insulating film 130 includes the charge storage film 132 made of silicon nitride or the like. Alternatively, the gate insulating film 130 may include a floating gate made of, for example, polycrystalline silicon containing N-type or P-type impurities.

Peripheral Circuit PC

FIG. 6 is a schematic block diagram showing a configuration of a part of the peripheral circuit PC. FIG. 7 is a schematic circuit diagram showing a configuration of a part of the sense amplifier module SAM.

FIG. 6 shows a plurality of control terminals and the like. The plurality of control terminals may be expressed as control terminals corresponding to high active signals (positive logic signals). The plurality of control terminals may be expressed as control terminals corresponding to low active signals (negative logic signals). Further, the plurality of control terminals may be expressed as control terminals corresponding to both the high active signal and the low active signal. In FIG. 6, the symbol of the control terminal corresponding to the low active signal includes an overline (upper line). In this specification, the symbol of the control terminal corresponding to the low active signal includes a slash (“/”). The description in FIG. 6 is an example, and a specific manner of implementation may be modified as appropriate. For example, some or all of the high active signals can be used as the low active signals, or some or all of the low active signals can be used as the high active signals.

The peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. The peripheral circuit PC includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. Further, the peripheral circuit PC includes an input/output control circuit I/O and a logic circuit CTR.

The voltage generation circuit VG includes, for example, a step-down circuit and a step-up circuit. The step-down circuit is, for example, a regulator. The step-up circuit is, for example, a charge pump circuit. Each of the step-down circuit and the step-up circuit is connected to a power supply voltage supply line. The voltage generation circuit VG is supplied with a power supply voltage V_CCand a ground voltage V_SS. The voltage generation circuit VG generates a plurality of operating voltages and simultaneously outputs the operating a voltages to plurality of voltage supply lines. The plurality of operating voltages are supplied to the bit line BL, the source line SL, the word line WL, and the select gate lines SGD and SGS, for example, during a read operation, a write operation, and an erase operation for the memory cell array MCA. The operating voltage is adjusted appropriately according to a control signal from the sequencer SQC.

The row decoder RD selects the memory block BLK, the string unit SU, and the word line WL and selects one page portion PGP from the memory cell array MCA, according to an input row address RA. Further, the row decoder RD transfers a part of the operating voltages supplied from the voltage generation circuit VG to the word line WL and the select gate lines SGD and SGS corresponding to the selected page portion PGP. The row decoder RD transfers another part of the operating voltages supplied from the voltage generation circuit VG to the other word lines WL and select gate lines SGD and SGS.

The sense amplifier module SAM includes, for example, a plurality of sense amplifier units SAU (see FIG. 7) provided corresponding to a plurality of the bit lines BL. As shown in FIG. 7, the sense amplifier unit SAU includes a sense amplifier SA, a wiring LBUS, and latch circuits SDL, DL0 to DLn (n is a natural number). A charge transistor 55 (see FIG. 7) for precharging is connected to the wiring LBUS. The wiring LBUS is connected to a wiring DBUS via a switch transistor DSW.

The sense amplifier SA includes a sense transistor 41. The sense transistor 41 discharges the charges of the wiring LBUS according to the current flowing through the bit line BL. A source electrode of the sense transistor 41 is connected to the voltage supply line to which the ground voltage V_SSis supplied. A drain electrode thereof is connected to the wiring LBUS via a switch transistor 42. A gate electrode thereof is electrically connected to the bit line BL via a sense node SEN, a discharge transistor 43, a node COM, a clamp transistor 44, and a breakdown voltage transistor 45. The sense node SEN is connected to an internal control signal line CLKSA via a capacitor 48.

Further, the sense amplifier SA includes a voltage transfer circuit. The voltage transfer circuit selectively makes the node COM and the sense node SEN into conductive with the voltage supply line to which the voltage V_DDis supplied or the voltage supply line to which a voltage V_SRCis supplied, depending on data stored in the latch circuit SDL. The voltage transfer circuit includes a node N1, a charge transistor 46, a charge transistor 49, a charge transistor 47, and a discharge transistor 50. The charge transistor 46 is connected between the node N1 and the sense node SEN. The charge transistor 49 is connected between the node N1 and the node COM. The charge transistor 47 is connected between the node N1 and the voltage supply line to which the voltage V_DDis supplied. The discharge transistor 50 is connected between the node N1 and the voltage supply line to which the voltage V_SRCis supplied. Gate electrodes of the charge transistor 47 and the discharge transistor 50 are commonly connected to a node INV_S of the latch circuit SDL.

The sense transistor 41, the switch transistor 42, the discharge transistor 43, the clamp transistor 44, the charge transistor 46, the charge transistor 49, and the discharge transistor 50 are, for example, enhancement-type NMOS transistors. The breakdown voltage transistor 45 is, for example, a depression-type NMOS transistor. The charge transistor 47 is, for example, a PMOS transistor.

A gate electrode of the switch transistor 42 is connected to a signal line STB. A gate electrode of the discharge transistor 43 is connected to a signal line XXL. A gate electrode of the clamp transistor 44 is connected to a signal line BLC. A gate electrode of the breakdown voltage transistor 45 is connected to a signal line BLS. A gate electrode of the charge transistor 46 is connected to signal line HLL. A gate electrode of the charge transistor 49 is connected to a signal line BLX. The signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to the sequencer SQC (see FIG. 6).

The latch circuit SDL includes nodes LAT_S and INV_S, an inverter 51, an inverter 52, a switch transistor 53, and a switch transistor 54. The inverter 51 includes an output terminal connected to the node LAT_S and an input terminal connected to the node INV_S. The inverter 52 includes an input terminal connected to the node LAT_S and an output terminal connected to the node INV_S. The switch transistor 53 is provided in a current path between the node LAT_S and the wiring LBUS. The switch transistor 54 is provided in a current path between the node INV_S and the wiring LBUS. The switch transistors 53 and 54 are, for example, NMOS transistors. A gate electrode of the switch transistor 53 is connected to the sequencer SQC via a signal line STL. A gate electrode of the switch transistor 54 is connected to the sequencer SQC via a signal line STI.

A plurality of the latch circuits SDL corresponding to the plurality of bit lines BL configure the latch portion SDLP described with reference to FIG. 2. One latch circuit SDL stores one bit of the data stored in the latch portion SDLP.

The latch circuits DL0 to DLn are configured almost similarly to the latch circuit SDL. However, as described above, the node INV_S of the latch circuit SDL is conductive with the gate electrodes of the charge transistor 47 and the discharge transistor 50 in the sense amplifier SA. In this point, the latch circuits DL0 to DLn differ from the latch circuit SDL.

A plurality of the latch circuits DL0 corresponding to the plurality of bit lines BL configure the latch portion DL0P described with reference to FIG. 2. Similarly, a plurality of the latch circuits DLI to DLn corresponding to the plurality of bit lines BL configure the latch portions DL1P to DLnP, respectively, described with reference to FIG. 2. Each of the latch circuits DL0 to DLn stores one bit of the data stored in the corresponding latch portions DL0P to DLnP.

The switch transistor DSW is, for example, an NMOS transistor. The switch transistor DSW is connected between the wiring LBUS and the wiring DBUS. A gate electrode of the switch transistor DSW is connected to the sequencer SQC via a signal line DBS.

Each of the signal lines STB, HLL, XXL, BLX, BLC, and BLS described above is commonly connected to all sense amplifier units SAU in the sense amplifier module SAM. The voltage supply line to which the voltage V_DDis supplied and the voltage supply line to which the voltage V_SRCis supplied are commonly connected to all sense amplifier units SAU in the sense amplifier module SAM, respectively. Further, the signal line STI and the signal line STL of the latch circuit SDL are commonly connected to all sense amplifier units SAU in the sense amplifier module SAM, respectively.

The cache memory CM (see FIG. 6) includes a plurality of latch circuits. The plurality of latch circuits in the cache memory CM are connected to the latch circuits DL0 to DLn in the sense amplifier module SAM via the wiring DBUS. Data DAT (data input from the controller CD, data read from the memory cell array MCA, and the like) in the plurality of latch circuits in the cache memory CM is sequentially transferred to the sense amplifier module SAM or the input/output control circuit I/O.

Further, a decode circuit and a switch circuit (not shown) are connected to the cache memory CM. The decode circuit decodes a column address CA stored in the address register ADR. The switch circuit makes the latch circuit corresponding to the column address CA into conductive with a bus DB in accordance with the output signal of the decode circuit.

The sequencer SQC outputs an internal control signal to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG according to command data D_CMDstored in the command register CMR. The sequencer SQC appropriately outputs status data DST indicating the state of the sequencer SQC to the status register STR.

Further, the sequencer SQC generates a ready/busy signal and outputs the ready/busy signal to a terminal RY//BY. During a period when the terminal RY//BY is in an “L” state (busy period), access to the memory die MD is basically prohibited. During a period when the terminal RY//BY is in an “H” state (ready period), access to the memory die MD is permitted.

The input/output control circuit I/O includes data input/output terminals DQ0 to DQ7, toggle signal input/output terminals DOS and/DQS, a plurality of input circuits, a plurality of output circuits, a shift register, and a buffer circuit. Each of the plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit is connected to a terminal to which a power supply voltage V_CCQand the ground voltage V_SSare supplied.

Data input via the data input/output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR in accordance with an internal control signal from the logic circuit CTR. Further, data output via the data input/output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit in accordance with the internal control signal from the logic circuit CTR.

The plurality of input circuits include, for example, a comparator connected to any one of the data input/output terminals DQ0 to DQ7 or both the toggle signal input/output terminals DQS and/DQS. The plurality of output circuits include, for example, an off chip driver (OCD) circuit connected to any one of the data input/output terminals DQ0 to DQ7 or any one of the toggle signal input/output terminals DQS and/DQS.

The logic circuit CTR receives an external control signal from the controller CD via external control terminals/CEn, CLE, ALE, /WE, /RE, and RE, and outputs an internal control signal to the input/output control circuit I/O in accordance with the external control signal.

The external control terminal/CEn is used when selecting the memory die MD. The input/output control circuit I/O of the memory die MD in which “L” is input to the external control terminal/CEn inputs and outputs data via the data input/output terminals DQ0 to DQ7. The input/output control circuit I/O of the memory die MD in which “H” is input to the external control terminal/CEn does not input and output data via the data input/output terminals DQ0 to DQ7.

The external control terminal CLE is used when using the command register CMR. When “H” is input to the external control terminal CLE, data input via the data input/output terminals DQ0 to DQ7 is stored as command data D_CMDin the buffer memory in the input/output control circuit I/O and transferred to the command register CMR.

The external control terminal ALE is used when using the address register ADR. When “H” is input to the external control terminal ALE, data input via the data input/output terminals DQ0 to DQ7 is stored as address data D_ADDin the buffer memory in the input/output control circuit I/O and transferred to the address register ADR.

When “L” is input to both the external control terminals CLE and ALE, data input via the data input/output terminals DQ0 to DQ7 is stored as the data DAT in the buffer memory in the input/output control circuit I/O. The data DAT is transferred to the cache memory CM via the bus DB. The external control terminal/WE is used when inputting data via the data input/output terminals DQ0 to DQ7. Data input via the data input/output terminals DQ0 to DQ7 is fetched into the shift register in the input/output control circuit I/O at the timing of the rise of the voltage of the external control terminal/WE.

The toggle signal input/output terminals DQS and/DQS are used when inputting data via the data input/output terminals DQ0 to DQ7. Data input via the data input/output terminals DQ0 to DQ7 is fetched into the shift register in the input/output control circuit I/O at the timing of the rise of the voltage of the toggle signal input/output terminal DOS and the fall of the voltage of the toggle signal input/output terminal/DQS. Data input via the data input/output terminals DQ0 to DQ7 is fetched into the shift register in the input/output control circuit I/O at the timing of the fall of the voltage of the toggle signal input/output terminal DQS (switching of the input signal) and the rise of the voltage of the toggle signal input/output terminal/DQS.

When inputting data, the external control terminal/WE may be used or the toggle signal input/output terminals DQS and/DQS may be used.

The external control terminals/RE and RE are used when outputting data via the data input/output terminals DQ0 to DQ7. Data output from the data input/output terminals DQ0 to DQ7 may be switched at the timing of the rise of the voltage of the external control terminal/RE. Data output from the data input/output terminals DQ0 to DQ7 may be switched at the timing of the fall of the voltage of the external control terminal/RE and the rise of the voltage of the external control terminal RE. Data output from the data input/output terminals DQ0 to DQ7 may be switched at the timing of the rise of the voltage of the external control terminal/RE and the fall of the voltage of the external control terminal RE.

Controller CD

FIG. 8 is a schematic block diagram showing a configuration of a part of the controller CD.

The controller CD, together with the storage device MEM and the like, implements various functions illustrated below.

In order to increase the speed, the read operation and the write operation are performed in parallel on the plurality of memory dies MD in the memory system 10. A set of the plurality of memory blocks BLK selected from the plurality of memory dies MD on which operations can be performed in parallel is referred to as a logical block.

A logical-to-physical address conversion table 60 stores a logical address representing an identification number of the logical block and a position in the logical block, and a physical address assigned to each page PG of the memory die MD (see FIG. 2) in correlation with each other. During the read operation, the physical address corresponding to the logical address is acquired by referring to an LUT 61, which will be described below, and the logical-to-physical address conversion table 60. During the write operation, the physical address of an “erased” page PG (see FIG. 2) is acquired and stored in the logical-to-physical address conversion table 60 in correlation with the logical address.

The look up table (LUT) 61 is a table that indicates in which logical address the data, which is stored with an address designated by the host computer 20 using a logical block address (LBA) or the like, is stored. When the stored data is valid, the LUT 61 stores the LBA and the logical address in correlation with each other. When the stored data is invalid, the LUT 61 stores information indicating that the correlation between the LBA and the logical address regarding the data is invalid. In the following description, among the logical blocks, a logical block of which corresponding pages PG are all “invalid” may be referred to as a free block.

A PECycle storage unit 62 stores each logical block and the number of times of erase operations executed on each logical block in correlation with each other. In the following description, the number of times of erase operations executed on each logical block may be referred to as a program erase cycle (PECycle). During the erase operation, the PECycle corresponding to the logical block on which the erase operation is executed is updated by referring to the PECycle storage unit 62. During the write operation, when selecting the logical block to which data is to be newly written, the free block having the smallest number of PECycles is selected by referring to the PECycle storage unit 62. After the erase operation is executed on this free block, the write operation is executed on the page PG in the memory block BLK that configures this logical block.

A memory control parameter storage unit 63 stores control parameters for the memory die MD. Such control parameters include various parameters. For example, during the read operation, the write operation, and the erase operation, the operating voltages supplied to the bit line BL, the source line SL, the word line WL, and the select gate lines SGD and SGS may be adjusted as appropriate. The memory control parameter storage unit 63 may store, for example, these operating voltages and the like.

During the read operation, an ECC processing unit 64 detects errors in data read from the memory die MD, and outputs the number of error bits FBC (failure bit count). The ECC processing unit 64 corrects the data when possible, during the read operation. Further, the ECC processing unit 64 encodes data input from the host computer 20 during the write operation. The ECC processing unit 64 may be implemented as a dedicated circuit, not by the controller CD and the storage device MEM.

An ECC parameter storage unit 65 stores control parameters regarding the ECC processing unit 64. For example, ECC calculation methods include a method using a BCH code, a method using an LDPC code, and the like. The ECC parameter storage unit 65 stores, for example, a value indicating which calculation method the ECC processing unit 64 uses to execute ECC processing and encoding processing. An FBC storage unit 66 stores the number of error bits FBC output from the ECC processing unit 64.

A timer 67 stores information indicating the current time (hereinafter referred to as time information”). The timer 67 receives a clock signal from a crystal oscillator (not shown) and updates the current time information as appropriate. Further, the timer 67 receives current time information from the host computer 20 and modifies the current time information in the timer 67 as appropriate.

A time information storage unit 68 stores time information indicating the time. The time information stored in the time information storage unit 68 will be described below.

Threshold voltage of memory cell MC

As described with reference to FIG. 3, the memory cell MC stores data as the magnitude of the threshold voltage. This point will be described below.

Example where Memory Cell MC Stores 1 Bit of Data

First, with reference to FIG. 9, an example in which the memory cell MC stores 1 bit of data will be described. FIG. 9 is a schematic histogram illustrating the threshold voltage of the memory cell MC in which 1 bit of data is stored. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC.

In the example of FIG. 9, the threshold voltage of the memory cell MC is set to one of two states. For example, the threshold voltage of the memory cell MC set to a lower state is lower than an erase verification voltage V_VFYEr. The threshold voltage of the memory cell MC set to an upper state is higher than a verification voltage V_VFYSand lower than a read pass voltage V_READ.

In the example of FIG. 9, a read voltage V_CGRis set between threshold voltage distribution corresponding to the lower state and threshold voltage distribution corresponding to the upper state.

For example, the lower state corresponds to a lower threshold voltage. The memory cell MC in the lower state is, for example, the memory cell MC in an erased state. For example, data “1” is assigned to the memory cell MC in the lower state.

The upper state corresponds to a high threshold voltage. The memory cell MC in the upper state is, for example, the memory cell MC in a written state. For example, data “0” is assigned to the memory cell MC in the upper state.

Example where Memory Cell MC Stores 2 Bits of Data

Next, with reference to FIGS. 10A and 10B, an example in which the memory cell MC stores 2 bits of data will be described. FIG. 10A is a schematic histogram illustrating the threshold voltage of the memory cell MC in which 2 bits of data is stored. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC. FIG. 10B is a table showing an example of a relationship between the threshold voltage of the memory cell MC in which 2 bits of data is stored and the stored data.

In the example of FIG. 10A, the threshold voltage of the memory cell MC is set to one of four states. The threshold voltage of the memory cell MC set to an Er state is lower than the erase verification voltage V_VEYEr. The threshold voltage of the memory cell MC set to an A state is higher than a verification voltage V_VEYAand lower than a verification voltage V_VFYB. The threshold voltage of the memory cell MC set to a B state is higher than the verification voltage V_VFYBand lower than a verification voltage V_VFYC. Similarly, the threshold voltage of the memory cell MC set to a C state is higher than the verification voltage V_VFYCand lower than the read pass voltage V_READ.

In the example of FIG. 10A, a read voltage V_CGARis set between threshold voltage distribution corresponding to the Er state and threshold voltage distribution corresponding to the A state. A read voltage V_CGBRis set between the threshold voltage distribution corresponding to the A state and threshold voltage distribution corresponding to the B state. A read voltage V_CGCRis set between the threshold voltage distribution corresponding to the B state and threshold voltage distribution corresponding to the C state.

For example, the Er state corresponds to a lowest threshold voltage. The memory cell MC in the Er state is the memory cell MC in the erased state. For example, data “11” is assigned to the memory cell MC in the Er state.

The A state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state. For example, data “10” is assigned to the memory cell MC in the A state.

The B state corresponds to a threshold voltage higher than the threshold voltage corresponding to the A state. For example, data “00” is assigned to the memory cell MC in the B state.

The C state corresponds to a threshold voltage higher than the threshold voltage corresponding to the B state. For example, data “01” is assigned to the memory cell MC in the C state.

In the case of the assignment illustrated in FIG. 10B, lower bits of data can be determined by one read voltage V_CGBR, and middle bits of data can be determined by two read voltages V_CGARand V_CGCR.

Example where Memory Cell MC Stores 4 Bits of Data

Next, with reference to FIGS. 11A and 11B, an example in which the memory cell MC stores 4 bits of data will be described. FIG. 11A is a schematic histogram illustrating the threshold voltage of the memory cell MC in which 4 bits of data is stored. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC. FIG. 11B is a table showing an example of a relationship between the threshold voltage of the memory cell MC in which 4 bits of data is stored and the stored data.

In the example of FIG. 11A, the threshold voltage of the memory cell MC is controlled into 16 states. The threshold voltage of the memory cell MC set to the Er state (S0 state) is lower than the erase verification voltage V_VFYEr. For example, the threshold voltage of the memory cell MC set to an S1 state is higher than a verification voltage V_VFY1and lower than a verification voltage V_VEY2. For example, the threshold voltage of the memory cell MC set to an S2 state is higher than the verification voltage V_VEY2and lower than a verification voltage V_VFY3. Similarly, the threshold voltages of the memory cells MC set to an S3 state to an S14 state are respectively higher than the verification voltage V_VFY3to a verification voltage V_VFY14and lower than a verification voltage V_VFY4to a verification voltage V_VFY15. For example, the threshold voltage of the memory cell MC set to an S15 state is higher than the verification voltage V_VFY15and lower than the read pass voltage V_READ.

In the example of FIG. 11A, a read voltage V_CG1Ris set between the threshold voltage distribution corresponding to the Er state and threshold voltage distribution corresponding to the S1 state. A read voltage V_CG2Ris set between the threshold voltage distribution corresponding to the S1 state and threshold voltage distribution corresponding to the S2 state. Similarly, a read voltage V_CG3Rto a read voltage V_CG15Rare respectively set from between the threshold voltage distribution corresponding to the S2 state and threshold voltage distribution corresponding to the S3 state to between threshold voltage distribution corresponding to the S14 state and threshold voltage distribution corresponding to the S15 state.

For example, the Er state corresponds to the lowest threshold voltage. The memory cell MC in the Er state is, for example, the memory cell MC in the erased state. For example, data “1111” is assigned to the memory cell MC in the Er state.

The S1 state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state. For example, data “1110” may be assigned to the memory cell MC in the S1 state.

The S2 state corresponds to a threshold voltage higher than the threshold voltage corresponding to the S1 state. For example, data “1100” may be assigned to the memory cell MC in the S2 state.

Similarly, the S3 state to the S15 state in the drawing correspond to threshold voltages higher than those corresponding to the S2 state to the S14 state, respectively. For example, data “1101”, data “1001”, data “1011”, data “0011”, data “0010”, data “1010”, data “1000”, data “0000”, data “0001”, data “0101”, data “0111”, data “0110”, and data “0100” may be respectively assigned to the memory cells MC in these states.

In the case of the assignment illustrated in FIG. 11B, the lower bits of data can be determined by three read voltages V_CGGR, V_CGBR, and V_CG10R. The middle bits of data can be determined by two read voltages V_CGARand V_CG12R. Upper bits of data can be determined by five read voltages V_CG2R, V_CG5R, V_CG9R, V_CG13R, and V_CG15R. Further, top bits of data can be determined by five read voltages V_CG1R, V_CG3R, V_CG7R, V_CG11R, and V_CG14R.

Read Operation

Next, the read operation will be described. FIG. 12 is a timing chart illustrating the read operation.

As described with reference to FIG. 6, the memory die MD includes eight data input/output terminals DQ0 to DQ7. In the following description, 8 bits of data input to these eight data input/output terminals DQ0 to DQ7 may be represented using two-digit hexadecimal numbers. For example, when “0, 0, 0, 0, 0, 0, 0, and 0” is input to the eight data input/output terminals DQ0 to DQ7, this data may be represented as data 00h or the like. Further, when “1, 1, 1, 1, 1, 1, 1, and 1” is input, this data may be represented as data FFh or the like.

FIG. 12 illustrates a command set CS_Rthat is input to the memory die MD during the read operation. This command set CS_Rincludes data 00h, CA1, CA2, RA1, RA2, RA3, and data 30h.

At timing t101, the controller CD inputs data 00h to the memory die MD as command data D_CMD. That is, in a state where the voltages of the data input/output terminals DQ0 to DQ7 are set to “H” or “L” according to each bit of data 00h, “H” is input to the external control terminal CLE, and “L” is input to the external control terminal ALE, the external control terminal/WE is raised from “L” to “H”. Data 00h is a command input at the start of the read operation.

At timing t102, the controller CD inputs data CA1 to the memory die MD as address data D_ADD. That is, in a state where the voltages of the data input/output terminals DQ0 to DQ7 are set to “H” or “L” according to each bit of data CA1, “L” is input to the external control terminal CLE, and “H” is input to the external control terminal ALE, the external control terminal/WE is raised from “L” to “H”. Data CA1 is a part of the column address CA (see FIG. 6).

At timing t103, the controller CD inputs data CA2 to the memory die MD as address data D_ADD. Data CA2 is a part of the column address CA (see FIG. 6).

At timing t104, the controller CD inputs data RA1 to the memory die MD as address data D_ADD. Data RA1 is a part of the row address RA (see FIG. 6). Data RA1 includes, for example, a block address and a page address. The block address is data that specifies the memory block BLK (see FIG. 2). The page address is data that specifies the page portion PGP (see FIG. 2).

At timing t105, the controller CD inputs data RA2 to the memory die MD as address data D_ADD. Data RA2 is a part of the row address RA (see FIG. 6). Data RA2 includes, for example, the block address and the page address.

At timing t106, the controller CD inputs data RA3 to the memory die MD as address data D_ADD. Data RA3 is a part of the row address RA (see FIG. 6). Data RA3 includes a chip address. The chip address is data that specifies one memory die MD from the plurality of memory dies MD controlled by the controller CD.

At timing t107, the controller CD inputs data 30h to the memory die MD as command data D_CMD. Data 30h is a command indicating that the input of the command set related to the read operation is completed.

At timing t108, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. The read operation is executed in the memory die MD.

At timing t109, the read operation with respect to the memory die MD ends. The terminal RY//BY changes from the “L” state to the “H” state, and access to the memory die MD is permitted.

The command set CS_Rillustrated in FIG. 12 is merely an example, and a specific mode may be adjusted as appropriate. For example, the command set CS_Rmay include data input before data 00h. In the example of FIG. 12, the row address RA (see FIG. 6) in the command set CS_Rincludes three pieces of data RA1 to RA3. Alternatively, the row address RA in the command set CS_Rmay include four or more pieces of data. The same applies to the command sets illustrated in the subsequent description.

FIG. 13 is a schematic cross-sectional view diagram illustrating the read operation. In the following description, the word line WL that is a target of the operation may be referred to as a selected word line WL_S, and the other word lines WL may be referred to as unselected word lines WL_U.

In the read operation, for example, the voltage V_DDis supplied to the bit line BL. For example, the latch circuit SDL in FIG. 7 is caused to store “H”, and the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to “L, L, H, H, H, and H”. With this, the voltage V_DDis supplied to the bit line BL and the sense node SEN. Further, the voltage V_SRCis supplied to the source line SL. The voltage V_SRCmay be larger than the ground voltage V_SSor may be equal to the ground voltage V_SS. The voltage V_DDis larger than the voltage V_SRC.

Further, in the read operation, the voltage V_SGis supplied to the drain-side select gate line SGD. The voltage V_SGis larger than the voltage V_DD. A voltage difference between the voltage V_SGand the voltage V_DDis larger than the threshold voltage when the drain-side select transistor STD functions as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the drain-side select transistor STD, and the voltage V_DDis transferred.

In the read operation, the voltage V_SGis supplied to the source-side select gate line SGS. The voltage V_SGis larger than the voltage V_SRC. A voltage difference between the voltage V_SGand the voltage V_SRCis larger than the threshold voltage when the source-side select transistor STS functions as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the source-side select transistor STS, and the voltage V_SRCis transferred.

In the read operation, the read pass voltage V_READis supplied to the unselected word line WL_U. The read pass voltage V_READis larger than the voltages V_DDand V_SRC. Further, a voltage difference between the read pass voltage V_READand the voltages V_DDand V_SRCis larger than the threshold voltage when the memory cell MC functions as an NMOS transistor, regardless of the data stored in the memory cell MC. Therefore, an electron channel is formed in the channel region of the unselected memory cell MC, and the voltages V_DDand V_SRCare transferred to the selected memory cell MC.

Further, in the read operation, the read voltage V_CGRis supplied to the selected word line WL_S. Although FIG. 9 shows an example in which the memory cell MC stores 1 bit of data, a read voltage supplied to the selected word line WL_Smay be the read voltages V_CGARto V_CGCRdescribed with reference to FIG. 10A, or may be the read voltages V_CG1Rto V_CG15Rdescribed with reference to FIG. 11A. For example, as described with reference to FIG. 10, when the memory cell MC stores 2 bits of data and the read operation of the middle page of this memory cell MC is executed, the read voltages V_CGARand V_CGCRare sequentially supplied to the selected word line WL_S. More specifically, the read voltage V_CGARis supplied to the selected word line WL_Sto execute a sensing operation to be described below, and then the read voltage V_CGCRis supplied to the selected word line WL_Sto further execute the sensing operation.

A voltage difference between the read voltage V_CGRor the like and V_SRCis larger than the threshold voltage of the memory cell MC in which a part of data is stored. Therefore, the memory cell MC in which a part of data is stored is turned ON. Therefore, a current flows through the bit line BL connected to this memory cell MC. On the other hand, the voltage difference between the read voltage V_CGRor the like and V_SRCis smaller than the threshold voltage of the memory cell MC in which a part of data is stored. Therefore, the memory cell MC in which a part of data is stored is turned OFF. Therefore, no current flows through the bit line BL connected to this memory cell MC.

Further, in the read operation, the sense amplifier module SAM (see FIG. 6) detects the current that flows through the bit line BL, thereby detecting the ON state/OFF state of the memory cell MC. Hereinafter, such an operation will be referred to as the “sensing operation”. In the sensing operation, for example, the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX described with reference to FIG. 7 are set to “L, H, H, H, L, and L”. As a result, the bit line BL and the sense node SEN are conductive with each other, the charges of the sense node SEN are discharged or maintained, and the sense transistor 41 is turned OFF or ON. Next, for example, the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to “H, L, H, H, L, and L”. As a result, the charges of the wiring LBUS are maintained or discharged. Furthermore, any one of the latch circuits in the sense amplifier unit SAU is conductive with the wiring LBUS, and the data of the wiring LBUS is stored by this latch circuit.

FIGS. 14 and 15 are schematic block diagrams illustrating data processing executed during the read operation.

When the memory cell MC stores 1 bit of data, for example, as shown in FIG. 14, the page portion PGP stores data DAT0 corresponding to one page PG. After the read operation is executed, this data DAT0 is stored in any latch portion (in the illustrated example, the latch portion DL0P) in the sense amplifier module SAM. In this case, data DAT0 is transferred to the cache memory CM (see FIG. 6).

When the memory cell MC stores multiple bits of data, for example, as shown in FIG. 15, a plurality of pieces of data DAT1 and DAT2 corresponding to the plurality of pages PG are stored in the page portion PGP. Further, after the read operation is executed, one or a plurality of pieces of data (in the illustrated example, DATA and DATB) is stored in any latch portion (in the illustrated example, the latch portions DL0P and DL1P) in the sense amplifier module SAM. For example, as described with reference to FIG. 10, when the memory cell MC stores 2 bits of data and the read operation of the middle page of this memory cell MC is executed, data DATA corresponds to data acquired by the sensing operation corresponding to the read voltage VEGAR. Data DATB corresponds to data acquired by the sensing operation corresponding to the read voltage V_CGCR. In this case, the sense amplifier module SAM can acquire data DAT2 corresponding to the middle page by, for example, performing AND operation of inverted data of data DATA and data DATB, and acquiring inverted data of the result of the AND operation. In this manner, the sense amplifier module SAM executes computation processing such as AND operation and OR operation, and calculates data (for example, data DAT2) corresponding to one page PG. This data is also transferred to the cache memory CM (see FIG. 6).

Data Output Operation

The data transferred to the cache memory CM (see FIG. 6) by the read operation is transferred to the controller CD by a data output operation. The data output operation will be described below.

FIG. 16 is a timing chart illustrating the data output operation.

FIG. 16 illustrates a command set CS_Othat is input to the memory die MD during the data output operation. This command set CS_Oincludes data 05h, CA1, CA2, RA1, RA2, RA3 and data E0h.

At timing t141, the controller CD inputs data 05h to the memory die MD as command data D_CMD. Data 05h is a command input at the start of the data output operation. At timing t142, the controller CD inputs data CA1 to the memory die MD as address data D_ADD.

At timing t143, the controller CD inputs data CA2 to the memory die MD as address data D_ADD.

At timing t144, the controller CD inputs data RA1 to the memory die MD as address data D_ADD.

At timing t145, the controller CD inputs data RA2 to the memory die MD as address data D_ADD.

At timing t146, the controller CD inputs data RA3 to the memory die MD as address data D_ADD.

At timing t147, the controller CD inputs data E0h to the memory die MD as command data D_CMD. Data E0h is a command indicating that the input of a command set related to the data output operation is completed.

At timing t148, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. Further, the data output operation is executed in the memory die MD.

At timing t149, the data output operation with respect to the memory die MD ends. The terminal RY//BY changes from the “L” state to the “H” state, and access to the memory die MD is permitted.

At timing t151, the controller CD causes data D101 to be output from the memory die MD. That is, in a state where “L” is input to the external control terminal CLE and “L” is input to the external control terminal ALE, the signals between the external control terminals/RE and RE are switched. Accordingly, the voltages of the data input/output terminals DQ0 to DQ7 are set to “H” or “L” according to each bit of data D101. The controller CD acquires this 8 bits of data D101. Data D101 is 8 bits of data among data DAT read from the memory cell MC by the read operation.

At timing t152, the controller CD causes data D102 to be output from the memory die MD. Data D102 is 8 bits of data among DAT read from the memory cell MC by the read operation. Similarly, the controller CD causes data DAT to be output by 8 bits from the memory die MD.

The controller CD can perform bit error detection/correction or the like on the data output from the memory die MD. The controller CD can transfer data which is subjected to the bit error detection/correction or the like to the host computer 20 (see FIG. 1).

Write Operation

Next, the write operation will be described.

FIG. 17 is a timing chart illustrating the write operation.

FIG. 17 illustrates a command set CS_Wthat is input to the memory die MD during the write operation. This command set CS_Wincludes data 80h, CA1, CA2, RA1, RA2, RA3, D201, D202 to D2XX, and data 10h.

At timing t201, the controller CD inputs data 80h to the memory die MD as command data D_CMD. Data 80h is a command input at the start of the write operation.

At timing t202, the controller CD inputs data CA1 to the memory die MD as address data D_ADD.

At timing t203, the controller CD inputs data CA2 to the memory die MD as address data D_ADD.

At timing t204, the controller CD inputs data RA1 to the memory die MD as address data D_ADD.

At timing t205, the controller CD inputs data RA2 to the memory die MD as address data D_ADD.

At timing t206, the controller CD inputs data RA3 to the memory die MD as address data D_ADD.

At timing t207, the controller CD inputs data D201 to the memory die MD as data DAT. That is, in a state where the voltages of the data input/output terminals DQ0 to DQ7 are set to “H” or “L” according to each bit of data D201, “L” is input to the external control terminal CLE, and “L” is input to the external control terminal ALE, the input signals between the toggle signal input/output terminals DQS and/DQS are switched (toggled). Data D201 is 8 bits of data among DAT written to the memory cell MC by the write operation.

At timing t208, the controller CD inputs data D202 to the memory die MD as data DAT. Data D202 is 8 bits of data among DAT written to the memory cell MC by the write operation. Similarly, the controller CD inputs data by 8 bits to the memory die MD as DAT.

At timing t209, the controller CD inputs data D2XX to the memory die MD as data DAT. Data D2XX is 8 bits of data among data DAT written to the memory cell MC by the write operation.

At timing t210, the controller CD inputs data 10h to the memory die MD as command data D_CMD. Data 10h is a command indicating that the input of a command set related to the write operation is completed.

At timing t211, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. The write operation is executed in the memory die MD.

At timing t212, the write operation with respect to the memory die MD ends. Further, the terminal RY//BY changes from the “L” state to the “H” state, and access to the memory die MD is permitted.

At timing t213, the controller CD inputs data 70h to the memory die MD, for example, as command data D_CMD. Data 70h is a command requesting output of status data D_STstored in the status register STR (see FIG. 6).

At timing t214, the controller CD causes, for example, data D211 to be output from the memory die MD. Data D211 is status data D_ST(see FIG. 6).

FIG. 18 is a schematic flowchart illustrating the write operation.

In step S101, the number of times of loops n_Wis set to 1. The number of times of loops n_Wis a variable indicating the number of times of write loops. For example, data DAT written to the memory cell MC is stored in the latch circuits DL0 to DLn of the sense amplifier unit SAU (see FIG. 7).

In step S102, a program operation is executed. The program operation is an operation in which a program voltage is supplied to the selected word line WL_Sto increase the threshold voltage of the memory cell MC.

In step S103, a verification operation is performed. The verification operation is an operation for supplying a verification voltage to the selected word line WL_S, detecting the ON state/OFF state of the memory cell MC, and determining whether the threshold voltage of the memory cell MC reaches a target value.

In step S104, the result of the verification operation is determined. For example, when the number of memory cells MC of which threshold voltages do not reach the target value is greater than or equal to a certain number by referring to a counter circuit (not shown), it is determined that the verification is FAIL, and the process proceeds to step S105. Meanwhile, when the number of memory cells MC of which threshold voltages do not reach the target value is less than a certain number, it is determined that the verification is PASS, and the process proceeds to step S107.

In step S105, it is determined whether the number of times of loops n_Wreaches a predetermined number N_W. When the number of times of loops n_Wdoes not reach the predetermined number N_W, the process proceeds to step S106. When the number of loops times of n_Wreaches the predetermined number N_W, the process proceeds to step S108.

In step S106, 1 is added to the number of times of loops n_W, and the process proceeds to step S102. In step S106, for example, a predetermined voltage AV is added to a program voltage VPGM. Therefore, the program voltage VPGM increases as the number of times of loops n_Wincreases.

In step S107, status data D_STindicating that the write operation ends normally is stored in the status register STR (see FIG. 6), and the write operation ends. Status data D_STis output to the controller CD (see FIG. 1) by a status read operation.

In step S108, status data D_STindicating that the write operation does not end normally is stored in the status register STR (see FIG. 6), and the write operation ends.

FIGS. 19 and 20 are schematic block diagrams illustrating data processing executed during the program operation.

When storing 1 bit of data in the memory cell MC, for example, as shown in FIG. 19, the latch portion SDLP in the sense amplifier module SAM is caused to store data DAT3 to be written by the write operation.

When the memory cell MC stores multiple bits of data, for example, as shown in FIG. 20, a plurality of pieces of data DAT4 and DAT5 corresponding to the plurality of pages PG to be written by the write operation are stored in any latch portion (in the illustrated example, the latch portions DL0P and DL1P) in the sense amplifier module SAM. In the sense amplifier module SAM, computation processing such as AND operation and OR operation is executed on these data DAT4 and DAT5, and data DAT6 indicating the memory cell MC of which threshold voltage is increased and the memory cell MC of which threshold voltage is not increased is calculated. This data DAT6 is stored in the latch portion SDLP in the sense amplifier module SAM.

FIG. 21 is a schematic cross-sectional view diagram illustrating the program operation.

In the program operation, for example, the voltage V_SRCis supplied to a bit line BL_Wconnected to the memory cell MC of which threshold voltage is adjusted among the plurality of selected memory cells MC. The voltage V_DDis supplied to a bit line BL_Pconnected to the memory cell MC of which threshold voltage is not adjusted among the plurality of selected memory cells MC. For example, as described with reference to FIGS. 19 and 20, data to be written by the write operation is stored in the latch portion SDLP in the sense amplifier module SAM. In this state, when the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX described with reference to FIG. 7 are set to “L, L, H, H, L, and H”, the voltage V_SRCis supplied to the bit line BL_W, and the voltage V_DDis supplied to bit line BL_P. Hereinafter, among the plurality of selected memory cells MC, the memory cells MC of which threshold voltage is adjusted may be referred to as a “write memory cell MC”, and the memory cells MC of which threshold voltage is not adjusted may be referred to as a “inhibited memory cell MC”.

In the program operation, the voltage V_SGDis supplied to the drain-side select gate line SGD.

The voltage V_SGDis larger than the voltage V_SRC. A voltage difference between the voltage V_SGDand the voltage V_SRCis larger than the threshold voltage when the drain-side select transistor STD functions as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the drain-side select transistor STD connected to the bit line BL_W, and the voltage V_SRCis transferred.

On the other hand, a voltage difference between the voltage V_SGDand the voltage V_DDis smaller than the threshold voltage when the drain-side select transistor STD functions as an NMOS transistor. Therefore, the drain-side select transistor STD connected to the bit line BL_Pis turned OFF.

In the program operation, the voltage V_SRCis supplied to the source line SL and the ground voltage V_SSis supplied to the source-side select gate line SGS. With this, the source-side select transistor STS is turned OFF.

In the program operation, a write pass voltage V_PASSis supplied to the unselected word line WL_U. The write pass voltage V_PASSis larger than the read pass voltage V_READ. A voltage difference between the write pass voltage V_PASSand the voltage V_SRCis larger than the threshold voltage when the memory cell MC functions as an NMOS transistor, regardless of the data stored in the memory cell MC. Therefore, an electron channel is formed in the channel region of the unselected memory cell MC, and the voltage V_SRCis transferred to the write memory cell MC.

In the program operation, the program voltage VPGM is supplied to the selected word line WL_S. The program voltage VPGM is larger than the write pass voltage V_PASS.

Here, the voltage V_SRCis supplied to the channel of the semiconductor pillar 120 connected to the bit line BL_W. A relatively large electric field is generated between this semiconductor pillar 120 and the selected word line WL_S. As a result, electrons in the channel of the semiconductor pillar 120 tunnel into the charge storage film 132 (see FIG. 5) via the tunnel insulating film 131 (see FIG. 5). With this, the threshold voltage of the write memory cell MC increases.

On the other hand, the channel of the semiconductor pillar 120 connected to the bit line BL_Pis in an electrically floating state, and a potential of this channel rises to about the write pass voltage V_PASSdue to capacitive coupling with the unselected word line WL_U. Only an electric field smaller than the electric field described above is generated between this semiconductor pillar 120 and the selected word line WL_S. Therefore, electrons in the channel of the semiconductor pillar 120 do not tunnel into the charge storage film 132 (see FIG. 5). Therefore, the threshold voltage of the inhibited memory cell MC does not increase.

FIG. 22 is a schematic cross-sectional view diagram illustrating the verification operation.

The verification operation is basically executed in the same manner as the read operation.

However, in the verification operation, the selected word line WL_Sis supplied with a verification voltage VVFY instead of the read voltage V_CGR. FIG. 9 shows the example in which the memory cell MC stores 1 bit of data. The verification voltage supplied to the selected word line WL_Smay be the verification voltages V_VEYAto V_VFYCdescribed with reference to FIG. 10A, or the verification voltages V_VFY1to V_VFY15described with reference to FIG. 11A. For example, as described with reference to FIGS. 10A and 10B, when storing 2 bits of data in the memory cell MC, the verification voltages V_VEYAto V_VFYCare appropriately supplied to the selected word line WL_S.

In the read operation, for example, the voltage V_DDis supplied to all bit lines BL corresponding to the page PG. On the other hand, in the verification operation, for example, the voltage V_DDmay be supplied to the bit line BL connected to the memory cell MC corresponding to a specific state and the voltage V_SRCmay be supplied to the other bit lines BL, based on the data in the latch circuits DL0 to DLnL.

Execution Order of Write Operations

Next, an execution order of the write operations will be described. FIG. 23 is a schematic cross-sectional view diagram illustrating the execution order of the write operations. FIG. 24 is a schematic histogram illustrating the execution order of the write operations. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC.

FIG. 23 illustrates two memory blocks BLK. In the example of FIG. 23, the memory block BLK includes five word lines WL and five string units SUa to SUe. Therefore, in the example of FIG. 23, the memory block BLK includes 25 page portions PGP. For example, as shown in FIG. 11, when the memory cell MC stores 4 bits of data, the memory block BLK stores data corresponding to 100 pages PG.

Furthermore, FIG. 23 illustrates the execution order of the write operations. In the example of FIG. 23, first, the write operations are sequentially executed on five page portions PGP corresponding to the first word line WL counting from the bottom. In each write operation, as shown in FIG. 24, data corresponding to four pages PG is collectively stored in the page portion PGP which is in the erased state. That is, the memory cell MC corresponding to the lower state (Er state and S0 state) is controlled into 16 states by one write operation. Next, the write operations are sequentially executed on the five page portions PGP corresponding to the second word line WL counting from the bottom. Similarly, the write operations are sequentially executed on 15 page portions PGP corresponding to the third to fifth word lines WL counting from the bottom.

Here, the larger the number of pieces of data stored in the memory cell MC, the smaller a voltage margin between the states. For example, as shown in FIG. 9, when the memory cell MC stores 1 bit of data, a voltage margin between the threshold voltage distribution corresponding to the lower state and the threshold voltage distribution corresponding to the upper state is relatively large. On the other hand, as shown in FIG. 11, when the memory cell MC stores 4 bits of data, a voltage margin between the threshold voltage distribution corresponding to the S1 state and the threshold voltage distribution corresponding to the S2 state is relatively small. If the voltage margin is small, for example, when the threshold voltage of the memory cell MC fluctuates, there is a risk that a rate of erroneous reading may increase.

Here, when the write operations are executed in the order described with reference to FIG. 23, for example, during the fifth to ninth write operations (write operation to the five page portions PGP corresponding to the second word line WL counting from the bottom), the threshold voltage of the memory cells MC corresponding to the zeroth to fourth write operations (write operation to five page portions PGP corresponding to the first word line WL counting from the bottom) may increase. This is thought to be caused by, for example, the accumulation of electrons in the charge storage film 132 even in the vicinity of the conductive layer 110 provided in the lower part due to the supply of the program voltage VPGM to the conductive layer 110 provided in the upper part when assuming two conductive layers 110 (word line WL) arranged in the Z-direction as shown in FIG. 5.

Such an increase in the threshold voltage can be significantly prevented by, for example, executing the write operation of data corresponding to the lower page and the middle page (hereinafter referred to as an “MLC write operation”) and the write operation of data corresponding to the upper page and the top page (hereinafter referred to as a “Fine write operation”) separately. Such a method will be described below.

FIG. 25 is a schematic cross-sectional view diagram illustrating another execution order of the write operations. FIG. 26 is a schematic histogram illustrating the other execution order of the write operations. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC.

FIG. 25 illustrates the other execution order of the write operations.

In the example of FIG. 25, first, the MLC write operation is sequentially executed on five page portions PGP corresponding to the first word line WL counting from the bottom. In the MLC write operation, as shown in FIG. 26, data corresponding to two pages PG is stored in the page portion PGP which is in the erased state. That is, the memory cell MC corresponding to the lower state (Er state and S0 state) is controlled into four states.

Next, the MLC write operation is executed on the page portion PGP corresponding to the second word line WL counting from the bottom and the string unit SUa. Next, the Fine write operation is executed on the page portion PGP corresponding to the first word line WL counting from the bottom and the string unit SUa. Next, the MLC write operation is executed on the page portion PGP corresponding to the second word line WL counting from the bottom and the string unit SUb. Next, the Fine write operation is executed on the page portion PGP corresponding to the first word line WL counting from the bottom and the string unit SUb. Similarly, the execution of the MLC write operation on the page portion PGP corresponding to the second word line WL counting from the bottom and the execution of the Fine write operation on the page portion PGP corresponding to the first word line WL counting from the bottom are performed alternately.

Similarly, the execution of the MLC write operations on the page portions PGP corresponding to the third to fifth word lines WL counting from the bottom and the execution of the Fine write operations on the page portions PGP corresponding to the second to fourth word lines WL counting from the bottom are performed alternately. Next, the Fine write operation is sequentially executed on the five page portions PGP corresponding to the fifth word line WL counting from the bottom.

Here, when the write operations are executed in the order described with reference to FIG. 25, for example, during the fifth write operation (MLC write operation to the page portion PGP corresponding to the second word line WL counting from the bottom), the threshold voltages of the memory cells MC corresponding to the zeroth write operation (MLC write operation to the page portion PGP corresponding to the first word line WL counting from the bottom) may increase. However, the final threshold voltages of these memory cells MC can be adjusted by the Fine write operation.

Further, for example, during the sixteenth write operation (Fine write operation to the page portion PGP corresponding to the second word line WL counting from the bottom), the threshold voltages of the memory cells MC corresponding to the sixth write operation (Fine write operation to the page portion PGP corresponding to the first word line WL counting from the bottom) may increase. However, compared to the write operation described with reference to FIG. 24, the Fine write operation has less influence on the unselected page portion PGP adjacent to the selected page portion PGP in the Z-direction.

To address such issues, in the memory system 10 according to the first embodiment, the write operations are executed in the order described with reference to FIGS. 25 and 26.

Data Processing Executed During the MLC Write Operation

FIG. 27 is a schematic block diagram illustrating data processing executed during the MLC write operation. As shown in FIG. 27, during the MLC write operation, data DAT11 corresponding to the lower page and data DAT12 corresponding to the middle page are input from the controller CD to the memory die MD. In the example of FIG. 27, these data DAT11 and DAT12 are stored in the latch portions DL0P and DL1P, respectively.

FIG. 28 is a timing chart illustrating the data processing in FIG. 27.

FIG. 28 illustrates two command sets input to the memory die MD during the data processing in FIG. 27. One of the two command sets corresponds to data DAT11 corresponding to the lower page. The other of the two command sets corresponds to data DAT12 corresponding to the middle page.

The command set corresponding to data DAT11 is basically the same as the command set CS_Wdescribed with reference to FIG. 17. However, this command set includes data A1h and 01h that are input before data 80h is input. Data 1Ah is included instead of data 10h. Data A1h is a command designating the MLC write operation, or the read operation to the page portion PGP for which the MLC write operation is executed and the Fine write operation is not executed. Data 01h is a command input when designating the lower page. Data 1Ah is a command indicating that the input of a command set related to the write operation is completed and that a further command set is to be input continuously.

When the command set corresponding to data DAT11 is input, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. Data processing regarding data DAT11 is executed over a time TBD. For example, data DAT11 is transferred to the latch portion DL0P.

The command set corresponding to data DAT12 is basically the same as the command set CS_Wdescribed with reference to FIG. 17. However, this command set includes data A1h and 02h that are input before data 80h is input. Data 02h is a command input when designating the middle page.

When the command set corresponding to data DAT12 is input, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. The MLC write operation is executed over a time tPROG.

Example of Using Internal Data During the Fine Write Operation

FIG. 29 is a schematic block diagram illustrating an example of data processing executed during the Fine write operation. During the Fine write operation, data in the memory die MD (hereinafter sometimes referred to as “internal data”) may be used. For example, as shown in FIG. 29, during the Fine write operation, data DAT11 and DAT12 may be read from the lower page and the middle page of the page portion PGP that is a target of the write operation, and these data DAT11 and DAT12 may be stored in the latch portions DL0P and DL1P. Data DAT13 corresponding to the upper page and data DAT14 corresponding to the top page are input from the controller CD to the memory die MD. In the example of FIG. 29, these pieces of data DAT13 and DAT14 are stored in the latch portions DL2P and DL3P, respectively.

FIG. 30 is a timing chart illustrating the data processing in FIG. 29.

FIG. 30 illustrates two command sets input to the memory die MD during the data processing in FIG. 29. One of the two command sets corresponds to data DAT13 corresponding to the upper page. The other of the two command sets corresponds to data DAT14 corresponding to the top page.

The command set corresponding to data DAT13 is basically the same as the command set CS_Wdescribed with reference to FIG. 17. However, this command set includes data 03h that is input before data 80h is input. Data 1Ah is included instead of data 10h. Data 03h is a command input when designating the upper page.

When the command set corresponding to data DAT13 is input, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. Data processing regarding data DAT13 is executed over the time TBD. For example, data DAT13 is transferred to the latch portion DL2P.

The command set corresponding to data DAT14 is basically the same as the command set CS_Wdescribed with reference to FIG. 17. However, this command set includes data 04h that is input before data 80h is input. Data 04h is a command input when designating the top page.

When the command set corresponding to data DAT14 is input, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. The Fine write operation is executed over the time tPROG.

Example of Inputting External Data During the Fine Write Operation

FIG. 31 is a schematic block diagram illustrating another example of the data processing executed during the Fine write operation. In the following description, description of aspects similar to the example of FIG. 29 will be omitted.

During the Fine write operation, data outside the memory die MD (hereinafter sometimes referred to as “external data”) may be input to the memory die MD and used. For example, as shown in FIG. 31, the controller CD may store data DAT11 and DAT12, that are written by the MLC write operation and for which the Fine write operation to the corresponding page portion PGP is not completed, in the storage device MEM. During the Fine write operation, data DAT11 and DAT12 may be read from the storage device MEM, and these data DAT11 and DAT12 may be stored in the latch portions DL0P and DL1P.

FIG. 32 is a timing chart illustrating the data processing in FIG. 31.

FIG. 32 illustrates four command sets input to the memory die MD during the data processing in FIG. 31. The four command sets correspond to data DAT11 to DAT14, respectively.

The command set corresponding to data DAT11 is basically the same as the first command set described with reference to FIG. 28. However, this command set does not include data A1h.

The command set corresponding to data DAT12 is basically the same as the second command set described with reference to FIG. 28. However, this command set does not include data A1h. Data 1Ah is included instead of data 10h.

When the command set corresponding to data DAT12 is input, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. Data processing regarding data DAT12 is executed over the time TBD. For example, data DAT12 is transferred to the latch portion DL1P.

The command set corresponding to data DAT13 is the same as the first command set described with reference to FIG. 30.

The command set corresponding to data DAT14 is the same as the second command set described with reference to FIG. 30.

Another Example of Inputting External Data During the Fine Write Operation

FIG. 33 is a schematic block diagram illustrating still another example of the data processing executed during the Fine write operation. In the following description, description of aspects similar to the example of FIG. 29 will be omitted.

As shown in FIG. 33, during the Fine write operation, data DAT11 and DAT12 may be read from the lower page and the middle page of the page portion PGP that is the target of the write operation, and these pieces of data DAT11 and DAT12 may be input to the controller CD. The controller CD may perform processing such as bit error detection/correction on these data DAT11 and DAT12 by the ECC processing unit 64 (see FIG. 8). Further, these pieces of data DAT11 and DAT12 may be input to the memory die MD as external data and stored in the latch portions DL0P and DL1P.

FIG. 34 is a timing chart illustrating the data processing in FIG. 33. In the data processing in FIG. 33, the processing corresponding to FIG. 34 is executed, and then the processing described with reference to FIG. 32 is executed.

FIG. 34 illustrates four command sets input to the memory die MD during the data processing in FIG. 33. The four command sets correspond to the read operation of data DAT11, the data output operation of data DAT11, the read operation of data DAT12, and the data output operation of data DAT12, respectively.

The command set corresponding to the read operation of data DAT11 is basically the same as the command set CS_Rdescribed with reference to FIG. 12. However, this command set includes data A1h and 01h that are input before data 00h is input.

When the command set corresponding to the read operation of data DAT11 is input, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. Further, the read operation of data DAT11 is executed over a time tR.

The command set corresponding to the data output operation of data DAT11 is the same as the command set CS_Odescribed with reference to FIG. 16.

The command set corresponding to the read operation of data DAT12 is basically the same as the command set CS_Rdescribed with reference to FIG. 12. However, this command set includes data A1h and 02h that are input before data 00h is input.

When the command set corresponding to the read operation of data DAT12 is input, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD s prohibited. Further, the read operation of data DAT12 is executed over the time tR.

The command set corresponding to the data output operation of data DAT12 is the same as the command set CS_Odescribed with reference to FIG. 16.

Processing Executed by the Controller CD During the Execution of the Write Operation

The data processing executed during the MLC write operation is described above. As examples of the data processing executed during the Fine write operation, one example in which internal data is used (see FIGS. 29 and 30) as data DAT11 and DAT12 corresponding to the lower page and the middle page, and two examples in which external data is input to the memory die MD (see FIGS. 31 to 34) are described.

Here, in the example of using internal data, the input of data DAT11 and DAT12 is omitted. Therefore, compared to, for example, the examples of FIGS. 31 and 32, the time required to input two command sets including data DAT11 and DAT12 and the time TBD required for data processing are reduced, thereby enabling high-speed processing.

However, for example, when a predetermined period of time elapses after the execution of the MLC write operation, electrons may escape from the charge storage film 132 (see FIG. 5), the threshold voltage of the memory cell MC may decrease, and data fluctuation may occur. When the Fine write operation is executed using internal data (data DAT11 and DAT12) in such a state, there is a risk that erroneous data may be written to some memory cells MC. In this regard, in the examples described with reference to FIGS. 31 and 32, since data DAT11 and DAT12 are stored in the external storage device MEM, data fluctuation can be prevented. Further, in the example described with reference to FIGS. 33 and 34, since data can be corrected by the ECC processing unit 64 (see FIG. 8), it is possible to input the corrected data DAT11 and DAT12 to the memory die MD.

To address such issues, in the present embodiment, when executing the Fine write operation before a threshold time elapses after the MLC write operation is executed, internal data is used. Further, when executing the Fine write operation after the threshold time elapses after the MLC write operation is executed, external data is input to the memory die MD.

With this, it is possible to reduce the time required to write data while preventing deterioration in reliability.

Next, with reference to FIG. 35, an operation of the controller CD when executing the write operation will be described in more detail. FIG. 35 is a schematic flowchart illustrating the operation of the controller CD when executing the write operation. FIG. 35 illustrates the operation of the controller CD when a request for the write operation occurs.

In step S111, address data D_ADDof the page portion PGP on which the write operation is to be executed is acquired. For example, when a memory block BLK on which the write operation is being executed exists in the memory cell array MCA, this memory block BLK is selected. For example, when there is no memory block BLK on which the write operation is being executed in the memory cell array MCA, the memory block BLK is selected based on the PECycle storage unit 62 (see FIG. 8) or the like. In the selected memory block BLK, the page portion PGP may be selected in the order described with reference to FIG. 25. In this step, the acquired address data D_ADDmay be stored in the logical-to-physical address conversion table 60 (see FIG. 8).

In step S112, it is determined whether the write operation to be executed is the MLC write operation. If the write operation to be executed is the MLC write operation, the process proceeds to step S113. If the write operation to be executed is not the MLC write operation, that is, if the write operation to be executed is the Fine write operation, the process proceeds to step S115.

In step S113, the two command sets described with reference to FIG. 28 are input to the memory die MD and the MLC write operation is executed.

In step S114, a time when the command set is issued (hereinafter referred to as a “command set issue time”) is stored. The command set issue time may be, for example, a time immediately before issuing the two command sets described with reference to FIG. 28, or may be a time immediately after issuing the two command sets.

In step S115, an elapsed time t from the command set issue time is acquired with reference to the time stored in step S114.

In step S116, it is determined whether the elapsed time t is smaller than the threshold time. If the elapsed time t is smaller than n the threshold time, the process proceeds to step S117. If the elapsed time t is not smaller than the threshold time, the process proceeds to step S118.

In step S117, for example, as described with reference to FIGS. 29 and 30, the Fine write operation is executed using internal data.

In step S118, for example, as described with reference to FIGS. 31 to 34, external data is input to the memory die MD and the Fine write operation is executed.

Second Embodiment

As described above, in the first embodiment, depending on whether the elapsed time t from the execution time of the MLC write operation (command set issue time) is smaller than the threshold time (step S116 in FIG. 35), it is determined whether to use internal data or input external data to the memory die MD during the Fine write operation.

However, such a method is merely an example, and a specific method may be adjusted as appropriate. For example, the number of error bits FBC may be monitored for the page portion PGP on which the MLC write operation is executed and the Fine write operation is not executed. Further, depending on the number of error bits FBC, it may be determined whether to use internal data or input external data to the memory die MD during the Fine write operation.

A memory system according to a second embodiment will be described below with reference to FIGS. 36 and 37. In the following description, the same element as in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

The memory system according to the second embodiment is basically configured similarly to the memory system according to the first embodiment. However, in the second embodiment, instead of the operation described with reference to FIG. 35, an operation described with reference to FIGS. 36 and 37 is executed.

FIG. 36 is a schematic flowchart illustrating the operation of the controller CD when executing patrol read. The patrol read is background processing that is executed at regular intervals when there is no instruction from the host computer 20 (see FIG. 1).

In step S201, read operations of the lower page and the middle page are executed on the page portion PGP on which the MLC write operation is executed and the Fine write operation is not executed. Further, error detection is executed by the ECC processing unit 64 (see FIG. 8), and the number of error bits FBC is calculated.

In step S202, it is determined whether the number of error bits FBC is greater than a threshold value. If the number of error bits FBC is greater than the threshold value, the process proceeds to step S203. If the number of error bits FBC is not greater than the threshold value, the patrol read ends.

In step S203, the page portion PGP on which the read operation is executed in step S201 is marked as a page portion of which reliability deteriorates (hereinafter referred to as a “page portion with deteriorated reliability”).

Next, with reference to FIG. 37, the operation of the controller CD when executing the write operation will be described. FIG. 37 is a schematic flowchart illustrating the operation of the controller CD when executing the write operation. FIG. 37 illustrates an example of the operation of the controller CD when a request for the write operation occurs.

The operation shown in FIG. 37 is basically executed in the same manner as the operation described with reference to FIG. 35. However, in the operation shown in FIG. 37, step S114 in FIG. 35 is not executed. Further, in the operation shown in FIG. 37, steps S215 and S216 are executed instead of steps S115 and S116 in FIG. 35.

In step S215, the result of the determination in step S202 of the patrol read (see FIG. 36), that is, the determination result of whether the page portion PGP on which the write operation is to be executed is the page portion with deteriorated reliability is acquired.

In step S216, it is determined whether the page portion PGP on which the write operation is to be executed is the page portion with deteriorated reliability. If the page portion PGP on which the write operation is to be executed is not the page portion with deteriorated reliability, the process proceeds to step S117. If the page portion PGP on which the write operation is the page portion with deteriorated reliability, the process proceeds to step S118.

Background processing other than the patrol read includes garbage collection (compaction), refresh, and wear-leveling.

The garbage collection is also referred to as compaction. Since the memory die MD has different erase units of data and read/write units of data, when the rewrite of the memory cells MC of the memory die MD progresses, the memory block BLK is fragmented due to invalid data. When the number of such fragmented memory blocks BLK increases, the number of available memory blocks BLK decreases. The garbage collection is a process for increasing the number of available memory blocks BLK, and means, for example, a process of collecting valid data from a plurality of active blocks including valid data and invalid data and rewriting the valid data to another memory block BLK to secure a free block.

The active block indicates a memory block BLK in which valid data is stored. The free block indicates a memory block BLK in which no valid data is stored. After being erased, the free block can be reused as an erased memory block BLK. In the present embodiment, the free block includes both the memory block BLK before erasure in which no valid data is stored and the erased memory block BLK. Valid data is data that is correlated with a logical address, and invalid data is data that is not correlated with the logical address. The erased memory block BLK becomes an active block when data is written thereto.

The refresh is a process in which, for example, when deterioration of data in a certain memory block BLK is detected, such as an increase in the number of corrected bits in error correction processing in the ECC processing unit 64, the data in the memory block BLK is rewritten to another memory block BLK.

The wear-leveling is a process of leveling the number of times of rewrite of the memory block BLK of the memory die MD by, for example, replacing data stored in the memory block BLK having a large number of times of rewrite and number of times of erase of data with data stored in the memory block BLK having a small number of times of rewrite and number of times of erase of data.

Third Embodiment

Next, a memory system according to a third embodiment will be described with reference to FIGS. 38 to 41. In the following description, the same elements as in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

The memory system according to the third embodiment is basically configured similarly to the memory system according to the first embodiment. However, H in the third embodiment, instead of the operation described with reference to FIG. 35, an operation described with reference to FIGS. 38 to 41 is executed.

FIG. 38 is a schematic flowchart illustrating the operation of the controller CD when executing the write operation. FIG. 38 illustrates the operation of the controller CD when a request for the write operation occurs.

The operation shown in FIG. 38 is basically executed in the same manner as the operation described with reference to FIG. 35. However, in the operation shown in FIG. 38, steps S114 to S118 in FIG. 35 are not executed. In the operation shown in FIG. 38, step S313 is executed after executing step S112 and before executing step S113. Further, in the operation shown in FIG. 38, step S318 is executed instead of steps S115 to S118 in FIG. 35.

Next, steps S113 and S313 in FIG. 38 will be described with reference to FIG. 39. FIG. 39 is a schematic block diagram illustrating data processing executed during the MLC write operation.

In step S113 in FIG. 38, as shown in FIG. 39, the MLC write operation is executed on the page portion PGP of the selected memory block BLK, and data DAT11 corresponding to the lower page and data DAT12 corresponding to the middle page are written to the page portion PGP.

In step S313 in FIG. 38, as shown in FIG. 39, data DAT11 corresponding to the lower page is written to the page portion PGP of the memory block BLK different from the selected memory block BLK (memory block BLK including the page portion PGP on which the MLC write operation is executed). Data DAT12 corresponding to the middle page is written to another page portion PGP of this memory block BLK. Each of the plurality of memory cells MC in these two page portions PGP stores 1 bit of data, as described with reference to FIG. 9, for example. Hereinafter, the write operation for storing data by 1 bit in the memory cells MC in the page portion PGP is referred to as an “SLC write operation”.

Next, step S318 in FIG. 38 will be described with reference to FIG. 40. FIG. 40 is a schematic block diagram illustrating data processing executed during the Fine write operation according to the third embodiment.

In step S318 in FIG. 38, for example, as shown in FIG. 40, data DAT11 corresponding to the lower page and data DAT12 corresponding to the middle page are acquired from the two page portions PGP on which the SLC write operation is executed. Hereinafter, the read operation to the page portion PGP on which the SLC write operation is executed is referred to as an “SLC read operation”. Further, data DAT13 corresponding to the upper page and data DAT14 corresponding to the top page are input from outside the memory die MD.

In step S318 in FIG. 38, the two command sets described with reference to FIG. 30 are input and the Fine write operation is executed.

FIG. 41 is a timing chart illustrating the data processing in FIG. 40. In the data processing in FIG. 40, the processing corresponding to FIG. 41 is executed, and then the processing described with reference to FIG. 30 is executed.

FIG. 41 illustrates the four command sets input to the memory die MD during the data processing in FIG. 39. The four command sets correspond to the read operation of data DAT11, a transfer of data DAT11 to the latch portion DL0P, the read operation of data DAT12, and a transfer of data DAT12 to the latch portion DL1P, respectively.

The command set corresponding to the read operation of data DAT11 is basically the same as the command set CS_Rdescribed with reference to FIG. 12. However, this command set includes data A2h that is input before data 00h is input. Data A2h is a command designating the SLC write operation or the SLC read operation.

When the command set corresponding to the read operation of data DAT11 is input, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. The read operation of data DAT11 is executed over a time tRSLC. The time tRSLC is shorter than the time tR described with reference to FIG. 34.

The command set corresponding to the transfer of data DAT11 to the latch portion DL0P includes data 01h, 85h, CA1, CA2, RA1, RA2, RA3, and data 1Ah. Data 01h is a command designating the latch portion DL0P. Data 85h is a command input when the transfer of data in the cache memory CM to the latch portion starts. Data 1Ah is a command indicating that the input of the command set related to this data transfer is completed.

When the command set corresponding to the transfer of data DAT11 to the latch portion DL0P is input, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. The transfer of data DAT11 is executed over the time TBD.

When the command set corresponding to the read operation of data DAT12 is input, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. The read operation of data DAT12 is executed over the time tRSLC.

The command set corresponding to the transfer of data DAT12 to the latch portion DL1P is basically the same as the command set corresponding to the transfer of data DAT11 to the latch portion DL0P. However, the command set corresponding to the transfer of data DAT12 to the latch portion DL1P includes data 02h instead of data 01h. Data 02h is a command designating the latch portion DL1P.

When the command set corresponding to the transfer of data DAT12 to the latch portion DL1P is input, the terminal RY//BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. The transfer of data DAT12 is executed over the time TBD.

As described above, during the MLC write operation according to the third embodiment, data DAT11 corresponding to the lower page and data DAT12 corresponding to the middle page are written to two page portions PGP by the SLC write operation.

Here, the smaller the number of pieces of data stored in the memory cell MC, the larger a voltage margin between the states. For example, as shown in FIG. 9, when the memory cell MC stores 1 bit of data, a voltage margin between the threshold voltage distribution corresponding to the lower state and the threshold voltage distribution corresponding to the upper state is relatively large. In this memory cell MC, even if electrons escape from the charge storage film 132 (see FIG. 5) and the threshold voltage of the memory cell MC decreases, data fluctuation is unlikely to occur.

Since there is a low possibility that data fluctuation occurs in data DAT11 and DAT12 read from the two page portions PGP in step S318 in FIG. 38, bit error detection/correction for the data DAT11 and DAT12 may be omitted in the third embodiment. Further, the data output operation and the input of data DAT11 and DAT12 to the memory die MD, which are necessary for the bit error detection/correction, may be omitted. With this, it is possible to reduce the time required to write data while preventing deterioration in reliability.

FIG. 38 shows an example in which the SLC write operation is executed in step S313, and then the MLC write operation is executed in step S113. However, such a method is merely an example, and step S313 may be executed after executing step S113.

Fourth Embodiment

In the third embodiment, the MLC write operation and the SLC write operation are successively executed. However, for example, when the elapsed time from the execution time of the MLC write operation to the execution time of the Fine write operation is sufficiently short, it can be considered to omit the execution of the SLC write operation. With this, it is possible to reduce the execution time of the SLC write operation that occurs during the execution of the MLC write operation. Further, the number of page portions PGP for executing the SLC write operation can be reduced.

A memory system according to a fourth embodiment will be described below with reference to FIGS. 42 and 43. In the following description, the same elements as in the third embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

The memory system according to the fourth embodiment is basically configured similarly to the memory system according to the third embodiment. However, in the fourth embodiment, instead of the operation described with reference to FIG. 38, the operation described with reference to FIGS. 42 and 43 is executed.

FIG. 42 is a schematic flowchart illustrating the operation of the controller CD when executing the write operation. FIG. 42 illustrates the operation of the controller CD when a request for the write operation occurs.

The operation shown in FIG. 42 is basically executed in the same manner as the operation described with reference to FIG. 35. However, in the operation shown in FIG. 42, step S416 is executed instead of steps S115 and S116 in FIG. 35. Further, in the operation shown in FIG. 42, step S318 described with reference to FIG. 38 is executed instead of step S118 in FIG. 35.

In step S416, it is determined whether the SLC write operation is executed on data corresponding to the lower page and the middle page stored in the page portion PGP on which the Fine write operation is to be executed. If the SLC write operation is not executed, the process proceeds to step S117. If the SLC write operation is executed, the process proceeds to step S318.

FIG. 43 is a schematic flowchart illustrating the operation of the controller CD when executing background processing that is executed at regular intervals when there is no instruction from the host computer 20 (see FIG. 1). In step S401, the elapsed time t from the command set issue time is acquired.

In step S402, it is determined whether the elapsed time t is smaller than the threshold time. If the elapsed time t is smaller than the threshold time, the process ends. If the elapsed time t is not smaller than the threshold time, the process proceeds to step S403.

In step S403, the SLC write operation is executed. Step S403