0-WL(n)_(m) are similar to aforementioned content about the NAND strings NAND0_0-NAND(m)_0. For the sake of brevity, similar content will not be repeated here.

Through the connection relationships between the plurality of bit lines, the plurality of NAND strings, the plurality of word lines, the plurality of string select lines and the plurality of ground select lines mentioned above, the reference array RA forms a three-dimensional (3D) structure as shown in FIG. 2. In addition, the structure of the data array (not shown) in the memory searching engine 100 is similar to the reference array RA. For the sake of brevity, the details will not be repeated here.

In some embodiments, in each of the NAND strings, two adjacent transistors coupled to the word lines correspond to one bit of In-Memory-Search (IMS). Take the instance in FIG. 3 for example, in the NAND string NAND0_0, the transistors coupled to the word lines WL0_0 and WL1_0 correspond to the first bit of IMS, the transistors coupled to the word lines WL2_0 and WL3_0 correspond to the second bit of IMS, and so on.

In some embodiments, according to the configuration and conduction status of the plurality of transistors in the NAND string, a pattern data is stored in each NAND string, and all NAND strings connected to the same bit line store the same pattern data. Take the instance in FIG. 3 for example, the NAND strings NAND0_0-NAND(m)_0 connected to the bit line BL0 store the same pattern data.

In some embodiments, each of the data array (not shown) and the reference array RA in the memory searching engine 100 stores the pattern data, wherein the pattern data stored by the data array and the pattern data stored by the reference array RA have the same number of features. In addition, in some embodiments, the memory searching engine 100 is configured to perform a data searching based on the received input data and the pattern data stored in the data array, and then outputs a corresponding searching result.

Since the pattern data of the data array and the reference array RA may have different patterns, the logic value output by the bit line depends on the relationship between its discharge curve and the reference time or reference voltage. Please refer to FIG. 4A and FIG. 4B. FIG. 4A and FIG. 4B are graphs of discharge curves of the bit lines BL1 and BL2 in accordance with some embodiments of the present disclosure. The discharge curves in FIG. 4A are similar to the discharge curves in FIG. 4B. The difference is that in the embodiment of FIG. 4A, the outputs of the bit lines BL1 and BL2 are determined according to a reference voltage Vref, while in the embodiment of FIG. 4B, the outputs of the bit lines BL1 and BL2 are determined according to a reference time Tref.

First, please refer to FIG. 4A. In the embodiments of FIG. 4A, the reference voltage Vref is the reference voltage (e.g., set by a logic unit in the memory searching engine 100) used to determine the logic values of the bit lines BL1 and BL2. At sensing time Ts, the voltage of the bit line BL1 has decreased to the voltage lower than the reference voltage Vref, thus the bit line BL1 will generate an output corresponding to logic “1”. On the other hand, at sensing time Ts, although the voltage of the bit line BL2 has decreased, it still remains higher than the reference voltage Vref, thus the bit line BL2 will generate an output corresponding to logic “0”.

Next, please refer to FIG. 4B. In the embodiments of FIG. 4B, the reference time Tref is the reference time (e.g., set by a logic unit in the memory searching engine 100) used to determine the logic values of the bit lines BL1 and BL2. Since the time required for the voltage of the bit line BL1 to drop from the start of discharge to the sensing voltage Vs is less than the reference time Tref, the bit line BL1 will generate an output corresponding to logic “1”. On the other hand, since the time required for the voltage of the bit line BL1 to drop from the start of discharge to the sensing voltage Vs is more than the reference time Tref, the bit line BL2 will generate an output corresponding to logic “0”.

It should be noted that the discharge curves and the output configurations of logic values in FIG. 4A and FIG. 4B in present disclosure is only an example, and is not intended to limit the present disclosure. Other discharge curves and output configurations of logic values are within the scope of the present disclosure.

As mentioned above, in some embodiments, the memory searching engine 100 stores at least one reference time Tref and at least one reference voltage Vref, and these reference times Tref and reference voltage Vref correspond to a plurality of Hamming distances (HD).

Specifically, Hamming distance represents the amount of bit difference between input data and stored data. For example, the stored data is a binary string “000000”, when the input data is a binary string “000001”, since there is one bit difference between the input data and the stored data, the Hamming distance is 1; when the input data is a binary string “011011”, since there are four bit differences between the input data and the stored data, the Hamming distance is 4, and so on. Depending on the difference between the input data and the stored data (i.e., the Hamming distance), the bit lines will have different discharge curves. Therefore, in order to determine the logic values for discharge curves with different Hamming distances, the memory searching engine 100 stores at least one reference time Tref and at least one reference voltage Vref corresponding to the plurality of Hamming distances.

However, long-term data storage or temperature changes of the memory may cause the electronic properties of the memory searching engine 100 to shift, thereby changing the discharge curves of the bit lines and affecting the outputs of the bit lines. Therefore, the reference time or reference voltage in the memory searching engine 100 may need to be updated. For example, the discharge curve of the bit line BL1 in FIG. 4A may be shifted to the position of the discharge curve of the bit line BL2, resulting in outputting different logic values. Therefore, in some embodiments, the memory searching engine 100 may perform a reference calibrating periodically or before performing specific operations (e.g., data searching) to adjust the stored reference time Tref and reference voltage Vref.

FIG. 5A is a schematic diagram of calibrating the reference time corresponding to changes in the discharge curve in accordance with some embodiments of the present disclosure. FIG.