302 between adjacent gate structures 304, 306, 308, may include an active region of the substrate 302. In various embodiments, each of the gate structures 304, 306, 308 may include an interfacial layer formed over the substrate 302, a gate dielectric layer formed over the interfacial layer, and a metal gate (MG) layer 310 formed over the gate dielectric layer. In some embodiments, each of the interfacial layer, the dielectric layer, and the metal gate layer 310 of the gate structures 304, 306, 308 may be substantially the same as those described above with respect to the transistor 100 and the FinFET 150. In addition, each of the gate structures 304, 306, 308 may include sidewall spacer layers 312, 314. In some cases, each of the sidewall spacer layers 312, 314 include materials having different dielectric constant values (e.g., k values).

The method 200 proceeds to block 204 where a dielectric layer is deposited over the substrate. Still referring to FIG. 3, and in an embodiment of block 204, a dielectric layer 316 is formed over the substrate 302 and over each of the gate structures 304, 306, 308. By way of example, the dielectric layer 316 may include an inter-layer dielectric (ILD) layer that may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The dielectric layer 316 may be deposited by a subatmospheric CVD (SACVD) process, a flowable CVD process, or other suitable deposition technique.

The method 200 proceeds to block 206 where a first pattern is formed in the dielectric layer. With reference to FIGS. 3 and 4, and in an embodiment of block 206, a first pattern, that includes openings 318, 320, is formed within the dielectric layer 316. In some cases, the openings 318, 320 provide access to an adjacent source, drain, or body contact region. By way of example, the openings 318, 320 may be formed by a suitable combination of lithographic patterning and etching (e.g., wet or dry etching) processes.

The method 200 proceeds to block 208 where a second pattern is formed in the dielectric layer. With reference to FIGS. 4 and 5, and in an embodiment of block 208, a second pattern, including an opening 322, is formed within the dielectric layer 316. The opening 322 may also be formed by a suitable combination of lithographic patterning and etching (e.g., wet or dry etching) processes. In some cases, the opening 322 provides access to the metal gate layer 310 of the gate structure 306. Further, as illustrated in FIG. 5, the opening 322 may merge with the opening 318 to form a composite opening 324. After deposition of one or more metal layers, as described below, the composite opening 324 thus provides for a direct contact between a metal gate layer and an adjacent source, drain, and/or body region.

FIG. 5 also illustrates various key feature distances which are critical for process window determination. For example, double-arrow A provides a distance between the opening 322 (e.g., including subsequently deposited metal disposed therein) and the metal gate layer 310 of the gate structure 304. In at least some current processes, the distance A is too small, resulting in an unacceptable amount of leakage current. Double-arrow B provides a distance by which the opening 322 (e.g., including subsequently deposited metal disposed therein) overlaps the metal gate layer 310 of the gate structure 306. This overlap may be referred to as the “landing window”. In at least some current processes, the distance B and thus the landing window is too small, which can directly impact the quality and reliability of a connection made to the metal gate layer 310 of the gate structure 306. Double-arrow C provides a distance between the opening 322 (e.g., including subsequently deposited metal disposed therein) and the opening 320 (e.g., including subsequently deposited metal disposed therein). In at least some current processes, the distance C is too small, which may also result in an unacceptable amount of leakage current. Thus, for at least some conventional processes, the process window of semiconductor fabrication processes used to form contacts to a metal gate layer, and between the metal gate layer and an adjacent source, drain, and/or body region, has become too narrow and can no longer satisfy process window requirements.

The method 200 proceeds to block 210 where metallization and chemical mechanical polishing processes are performed. With reference to FIGS. 5 and 6, and in an embodiment of block 210, a silicidation process may initially be performed to form a silicide layer on exposed portions of the substrate 302 (e.g., exposed by the composite opening 324 and the opening 320), thus providing a low resistance contact. In some examples, and in a further embodiment of block 210, a glue or barrier layer 326 may be formed within each of the composite opening 324 and the opening 320. In some cases, the glue or barrier layer 326 may include Ti, TiN, Ta, TaN, W, or other appropriate material. Additionally, and in an embodiment of block 210, a metal layer 328 may be formed on the glue or barrier layer 326 within each of the composite opening 324 and the opening 320. In some examples, the metal layer 328 may include W, Cu, Co, Ru, Al, Rh, Mo, Ta, Ti, or other appropriate material. After deposition of the metal layer 328, and in an embodiment of block 210, a chemical mechanical planarization (CMP) process may be performed to remove excess material and planarize the top surface of the device 300. Thus, after deposition of the metal layer 328, a direct contact between a metal gate layer and an adjacent source, drain, and/or body region is provided. As described above, and because of the narrow process window in at least some existing processes, the device 300 may suffer from an unacceptable amount of leakage current (e.g., between the metal layer 328 and the metal gate layer 310 of the gate structure 304 and/or between the metal layer 328 deposited in each of the composite opening 324 and the opening 320). In addition, the landing window on which the metal layer 328 contacts the metal layer 310 of the gate structure 306 may be too small, negatively impacting the quality and reliability of the electrical connection made to the metal gate layer 310 of the gate structure 306. Thus, existing techniques have not proved entirely satisfactory in all respects.

Embodiments of the present disclosure offer advantages over the existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and no particular advantage is required for all embodiments. For example, embodiments discussed herein include methods and structures directed to a via-first metal gate contact fabrication process. In at least some embodiments, a via-first metal gate contact process is provided in which rather than directly contacting a metal gate to a metal contact layer, as in at least some conventional processes, a gate via is first formed on the metal gate, after which the metal contact layer is formed on the gate via. In various examples, the metal contact layer may further connect to an adjacent source, drain, and/or body region. In some embodiments, the gate via is centered on the metal gate and may provide a larger landing window for the metal contact layer (e.g., as compared to directly contacting the metal gate to the contact metal layer). As a result of adding the gate via between the metal gate and the metal contact layer, the process window is improved (e.g., increased). In addition, employing a gate via as described herein results in the metal contact layer (e.g., which contacts the gate via) to be disposed an increased distance ‘Z’ (e.g., as compared to at least some conventional processes), in a direction normal to the substrate, thus providing greater isolation between the metal contact layer and neighboring metal gates to which the metal contact layer is not connected. As such, leakage current between the metal contact layer and one or more neighboring metal gates, to which the metal contact layer is not connected, is reduced. Additional details of embodiments of the present disclosure are provided below, and additional benefits and/or other advantages will become apparent to those skilled in the art having benefit of the present disclosure.

Referring now to FIG. 7, illustrated is a method 700 of forming a via-first metal gate contact, in accordance with some embodiments. The method 700 is described below in more detail with reference to FIGS. 8-14. The method 700 may be implemented on a single-gate planar device, such as the exemplary transistor 100 described above with reference to FIG. 1A, as well as on a multi-gate device, such as the FinFET device 150 described above with reference to FIG. 1B. Thus, one or more aspects discussed above with reference to the transistor 100 and/or the FinFET 150 may also apply to the method 700. To be sure, in various embodiments, the method 700 may be implemented on other devices such as gate-all-around (GAA) devices, Omega-gate (Ω-gate) devices, or Pi-gate (Π-gate) devices, as well as strained-semiconductor devices, silicon-on-insulator (SOI) devices, partially-depleted SOI (PD-SOI) devices, fully-depleted SOI (FD-SOI) devices, or other devices as known in the art.

It is understood that parts of the method 700 and/or any of the exemplary transistor devices discussed with reference to the method 700 may be fabricated by a well-known complementary metal-oxide-semiconductor (CMOS) technology process flow, and thus some processes are only briefly described herein. For the sake of clarity, certain aspects of the method 700 that are shared with the method 200 may be only discussed briefly. Further, it is understood that any exemplary transistor devices discussed herein may include various other devices and features, such as additional transistors, bipolar junction transistors, resistors, capacitors, diodes, fuses, etc., but are simplified for a better understanding of the inventive concepts of the present disclosure. Further, in some embodiments, the exemplary transistor device(s) disclosed herein may include a plurality of semiconductor devices (e.g., transistors), which may be interconnected. In addition, in some embodiments, various aspects of the present disclosure may be applicable to either one of a gate-last process or a gate-first process.

In addition, in some embodiments, the exemplary transistor devices illustrated herein may include a depiction of a device at an intermediate stage of processing, as may be fabricated during processing of an integrated circuit, or portion thereof, that may comprise static random access memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as P-channel field-effect transistors (PFETs), N-channel FETs (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and/or combinations thereof.

The method 700 begins at block 702 where a substrate having a gate structure is provided. With reference to FIG. 8, and in an embodiment of block 702, a device 800 having a substrate 802 and including gate structures 804, 806, 808 is provided. In some embodiments, the substrate 802 may be substantially the same as either of the substrates 102, 152, described above. A region of the substrate 802 upon which the gate structures 804, 806, 808 are formed, and including regions of the substrate 802 between adjacent gate structures 804, 806, 808, may include an active region of the substrate 802. It will be understood that the device 800 is merely illustrative, and is provided for clarity of discussion regarding subsequent formation of the via-first metal gate contact. For example, in some cases, the device 800 may include a planar device, such as the transistor 100. Alternatively, in some examples, the device 800 may include a multi-gate device, such as the FinFET 150. Moreover, in some cases, the device 800 may include a GAA device, an Ω-gate device, a Π-gate device, a strained-semiconductor device, an SOI device, a PD-SOI device, a FD-SOI device, or other device as known in the art. In some embodiments, the device 800 includes regions 810, 812, adjacent to the gate structures 804, 806, 808, where the regions 810, 812 may include a source region, a drain region, or a body contact region. In various embodiments, each of the gate structures 804, 806, 808 may include an interfacial layer formed over the substrate 802, a gate dielectric layer formed over the interfacial layer, and a metal gate (MG) layer 814 formed over the gate dielectric layer. In some embodiments, each of the interfacial layer, the dielectric layer, and the metal gate layer 814 of the gate structures 804, 806, 808 may be substantially the same as those described above with respect to the transistor 100 and the FinFET 150. In addition, each of the gate structures 804, 806, 808 may include sidewall spacer layers 816, 818. In some cases, each of the sidewall spacer layers 816, 818 include materials having different dielectric constant values (e.g., k values). In various embodiments, the sidewall spacer layers 816, 818 include SiO_x, SiN, SiO_xN_y, SiC_xN_y, SiO_xC_yN_z, AlO_x, AlO_xN_y, AlN, HfO, ZrO, HfZrO, CN, poly-Si, combinations thereof, or other suitable dielectric materials. In some embodiments, the sidewall spacer layers 816, 818 include multiple layers, such as main spacer walls, liner layers, and the like. By way of example, the sidewall spacer layers 816, 818 may be formed by depositing a dielectric material over the device 800 and anisotropically etching back the dielectric material. In some embodiments, the etch-back process (e.g., for spacer formation) may include a multiple-step etching process to improve etch selectivity and provide over-etch control.

The method 700 proceeds to block 704 where a first dielectric layer is deposited over the substrate. Still referring to FIG. 8, and in an embodiment of block 704, a dielectric layer 820 is formed over the substrate 802 and over each of the gate structures 804, 806, 808. By way of example, the dielectric layer 820 may include an inter-layer dielectric (ILD) layer that may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The dielectric layer 820 may be deposited by a subatmospheric CVD (SACVD) process, a flowable CVD process, or other suitable deposition technique. In some embodiments, the dielectric layer 820 has a thickness of about 5-40 nm.

The method 700 proceeds to block 706 where a pattern is formed in the dielectric layer. With reference to FIGS. 8 and 9, and in an embodiment of block 706, a pattern, that includes openings 822, 824, is formed within the dielectric layer 820. In some cases, the openings 822, 824 provide access to regions 810, 812, adjacent to the gate structures 804, 806, 808, where the regions 810, 812 may include a source region, a drain region, or a body contact region. By way of example, the openings 822, 824 may be formed by a suitable combination of lithographic patterning and etching (e.g., wet or dry etching) processes. In some embodiments, the openings 822, 824 have a width of about 12-25 nm.

The method 700 proceeds to block 708 where metallization and chemical mechanical polishing processes are performed. With reference to FIGS. 9 and 10, and in an embodiment of block 708, a silicidation process may initially be performed to form a silicide layer on exposed portions of the substrate 802 (e.g., exposed by the openings 822, 824) in the regions 810, 812, thus providing a low resistance contact thereto. In some examples, and in a further embodiment of block 708, a glue or barrier layer 826 may be formed within each of the openings 822, 824. In some cases, the glue or barrier layer 826 may include Ti, TiN, Ta, TaN, W, or other appropriate material. In some embodiments, the glue or barrier layer 826 has a thickness of about 1-4 nm. Additionally, and in an embodiment of block 708, metal layers 828, 829 may be formed on the glue or barrier layer 826 within each of the openings 822, 824. In some examples, the metal layers 828, 829 may include W, Cu, Co, Ru, Al, Rh, Mo, Ta, Ti, TiN, TaN, WN, silicides, or other suitable conductive material. In some cases, the metal layers 828 and 829 may include the same material and may deposited together as part of a single deposition process. In some embodiments, the metal layers 828, 829 may have a width of about 10-20 nm and a height of about 30-60 nm. After deposition of the metal layers 828, 829, and in an embodiment of block 708, a chemical mechanical planarization (CMP) process may be performed to remove excess material and planarize the top surface of the device 800.

The method 700 proceeds to block 710 where a contact etch stop layer and a second dielectric layer are deposited over the substrate. Referring to FIGS. 10 and 11, and in an embodiment of block 710, a contact etch stop layer (CESL) 830 is formed over the substrate 802, and a dielectric layer 832 is formed over the contact etch stop layer 830. By way of example, the contact etch stop layer 830 may include Ti, TiN, TiC, TiCN, Ta, TaN, TaC, TaCN, W, WN, WC, WCN, TiAl, TiAlN, TiAlC, TiAlCN, or combinations thereof. In some embodiments, the dielectric layer 832 may include an inter-layer dielectric (ILD) layer that may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. Thus, in some cases, the dielectric layer 832 may be substantially the same as the dielectric layer 820. In various embodiments, the CESL 830 and the dielectric layer 832 may be deposited by a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable deposition technique. In some examples, the CESL 830 has a thickness of about 5-20 nm, and the dielectric layer 832 has a thickness of about 5-40 nm.

The method 700 proceeds to block 712 where a gate via opening is formed. With reference to FIGS. 11 and 12, and in an embodiment of block 712, a gate via opening 834 is formed. By way of example, the gate via opening 834 provides access to the metal gate layer 814 of the gate structure 806. By way of example, the gate via opening 834 may be formed by a suitable combination of lithographic patterning and etching (e.g., wet or dry etching) processes. In some cases, the gate via opening 834 has a width of about 12-25 nm. In some embodiments, one or more etching processes may be used to etch through each of the dielectric layer 832, the contact etch stop layer 830, and the dielectric layer 820, in sequence. In various embodiments, the gate via opening 834 is substantially aligned (e.g., centered) with the metal gate layer 814 of the gate structure 806. In addition, it will be understood that similar gate via openings may be formed to provide access to the metal gate layer 814 of the gate structures 804, 808, or to other gate structures not explicitly shown.

The method 700 proceeds to block 714 where a contact opening is formed. With reference to FIGS. 12 and 13, and in an embodiment of block 714, a contact opening 836 is formed. The contact opening 836 may also be formed by a suitable combination of lithographic patterning and etching (e.g., wet or dry etching) processes. In some examples, the contact opening 836 has a width of about 30-60 nm. In some embodiments, one or more etching processes may be used to etch through each of the dielectric layer 832 and the contact etch stop layer 830, in sequence. In some cases, the contact opening 836 provides access to the metal layer 828. Further, as illustrated in FIG. 13, the contact opening 836 may merge/overlap with the gate via opening 834 to form a composite opening 838. In some embodiments, the contact opening 836 and the gate via opening 834 overlap each other by about 0-20 nm. After deposition of one or more metal layers, as described below, the composite opening 838 thus provides for contact between a metal gate layer and an adjacent source, drain, and/or body region. However, because of the via-first process described herein, shortcomings of at least some current processes may be overcome.

For example, FIG. 13 also illustrates various key feature distances which are critical for process window determination. In particular, when compared with the feature distances of at least some current processes (e.g., shown in FIG. 5), the benefits of the present disclosure are clear. For example, double-arrow A-prime (A′) provides a distance between the contact opening 836 (e.g., including subsequently deposited metal disposed therein) and the metal gate layer 814 of the gate structure 804. Compared to some current processes, and in some embodiments, the distance represented by double-arrow A′ (FIG. 13) is greater than the distance represented by double-arrow A (FIG. 5). Thus, in some embodiments, and because of the increased distance ‘Z’ (e.g., in a direction normal to the substrate) of the metal within the contact opening 836, embodiments of the present disclosure provide greater isolation between the metal within the contact opening 836 and neighboring metal gates to which the metal contact layer is not connected (e.g., such as the metal gate layer 814 of the gate structure 804). As such, leakage current between the metal within the contact opening 836 and the metal gate layer 814 of the gate structure 804 is reduced.

As another example, double-arrow B-prime (B′) provides a distance of an available landing window within which the contact opening 836 (e.g., including subsequently deposited metal disposed therein) may overlap the gate via opening 834 (e.g., including subsequently deposited metal disposed therein). Compared to some current processes, and in some embodiments, the distance represented by double-arrow B′ (FIG. 13) is greater than the distance represented by double-arrow B (FIG. 5). Thus, in some embodiments, and because of the increased landing window provided by the via-first process disclosed herein, embodiments of the present disclosure provide higher quality and more robust gate connections.

As a further example, double-arrow C-prime (C′) provides a distance between the contact opening 836 (e.g., including subsequently deposited metal disposed therein) and the metal layer 829. Compared to some current processes, and in some embodiments, the distance represented by double-arrow C′ (FIG. 13) is greater than the distance represented by double-arrow C (FIG. 5). Thus, in some embodiments, and because of the increased distance ‘Z’ (e.g., in a direction normal to the substrate) of the metal within the contact opening 836, embodiments of the present disclosure provide greater isolation between the metal within the contact opening 836 and the metal layer 829. As such, leakage current between the metal within the contact opening 836 and the metal layer 829 is reduced.

Thus, embodiments of the present disclosure provide for an improved (i.e., increased) process window for the formation of contacts to a metal gate layer, and between the metal gate layer and an adjacent source, drain, and/or body region. In some cases, the process window may be improved by 10 nm (e.g., with respect to the key feature distance represented by double-arrow A′). In some embodiments, the process window may be improved by at least 3 nm (e.g., with respect to key feature distances represented by double-arrow B′ and C′).

The method 700 proceeds to block 716 where metallization and chemical mechanical polishing processes are performed. With reference to FIGS. 13 and 14, and in an embodiment of block 716, a glue or barrier layer 840 may be formed within the composite opening 838. In some cases, the glue or barrier layer 840 may include Ti, TiN, Ta, TaN, W, or other appropriate material. In some embodiments, the glue or barrier layer 840 has a thickness of about 1-4 nm. Additionally, and in an embodiment of block 716, a metal layer 842 may be formed on the glue or barrier layer 840 within the composite opening 838. In some examples, the metal layer 842 may include W, Cu, Co, Ru, Al, Rh, Mo, Ta, Ti, or other conductive material. It is noted that metal layer 842 within the composite opening 838 may be equivalently described as the metal layer 842 formed within each of the contact opening 836 and the gate via opening 834, where the contact opening 836 and the gate via opening 834 merge/overlap, as described above. Thus, in some embodiments and within a region of the contact opening 836, the metal layer 842 may have a width of about 30-60 nm and a height of about 10-30 nm. Additionally, in some embodiments and within a region of the gate via opening 834, the metal layer 842 may have a width of about 10-25 nm and a height of about 20-45 nm. In some examples, the width of the metal layer 842 across the length of the composite opening 838, including both the contact opening 836 and the gate via opening 834, may be about 30-85 nm. After deposition of the metal layer 842, and in an embodiment of block 716, a chemical mechanical planarization (CMP) process may be performed to remove excess material and planarize the top surface of the device 800. Thus, after deposition of the metal layer 842, contact is made, through a metal gate via, between a metal gate layer and an adjacent source, drain, and/or body region. As described above, and because of the improved (i.e., increased) process window provided by the embodiments disclosed herein, the device 800 is more robust (e.g., as compared to at least some current devices).

With reference to FIG. 15, illustrated therein is a layout design 900, which effectively provides a top schematic view of the device 800, discussed above. In some embodiments, the cross-section views of the device 800 shown in FIGS. 8-14 are provided along a plane substantially parallel to the line X-X′, illustrated in FIG. 15. The layout design 900 of FIG. 15 further illustrates metal gate layers 914, which may be the metal gate layers 814 described above; metal layers 928 and 929, which may be the metal layers 828, 829 described above; metal layer 942, which may be the metal layer 842 described above; and gate via 934, which may be the gate via formed in the gate via opening 834 described above. By way of example, and in some embodiments, the metal layer 942 may have a length of about 30-60 nm along an X-axis, and a width of about 10-30 nm along a Y-axis. In some examples, the gate via 934 may have a length of about 10-25 nm along the X-axis, and a width of about 10-25 nm along the Y-axis. Additionally, in some embodiments, the metal gate layers 914 may have a width of about 4-10 nm along the X-axis, and the metal layers 928, 928 may have a width of about 10-30 nm along the X-axis.

Referring now to FIG. 16, illustrated is an alternative method 1600 of forming a via-first metal gate contact, in accordance with some embodiments. Generally, while the method 700 described a via-first process including a via on a gate structure, the method 1600 shows a via-first process including a via on a gate structure and a via on metal contact to an adjacent source region, a drain region, or a body contact region. The method 1600 is described below in more detail with reference to FIGS. 17-23. The method 1600 may be implemented on a single-gate planar device, such as the exemplary transistor 100 described above with reference to FIG. 1A, as well as on a multi-gate device, such as the FinFET device 150 described above with reference to FIG. 1B. Thus, one or more aspects discussed above with reference to the transistor 100 and/or the FinFET 150 may also apply to the method 1600. To be sure, in various embodiments, the method 1600 may be implemented on other devices such as gate-all-around (GAA) devices, Omega-gate (Ω-gate) devices, or Pi-gate (Π-gate) devices, as well as strained-semiconductor devices, silicon-on-insulator (SOI) devices, partially-depleted SOI (PD-SOI) devices, fully-depleted SOI (FD-SOI) devices, or other devices as known in the art.

It is understood that parts of the method 1600 and/or any of the exemplary transistor devices discussed with reference to the method 1600 may be fabricated by a well-known complementary metal-oxide-semiconductor (CMOS) technology process flow, and thus some processes are only briefly described herein. For the sake of clarity, certain aspects of the method 1600 that are shared with the method 200 or the method 700 may be only discussed briefly. Further, it is understood that any exemplary transistor devices discussed herein may include various other devices and features, such as additional transistors, bipolar junction transistors, resistors, capacitors, diodes, fuses, etc., but are simplified for a better understanding of the inventive concepts of the present disclosure. Further, in some embodiments, the exemplary transistor device(s) disclosed herein may include a plurality of semiconductor devices (e.g., transistors), which may be interconnected. In addition, in some embodiments, various aspects of the present disclosure may be applicable to either one of a gate-last process or a gate-first process.

The method 1600 begins at block 1602 where a substrate having a gate structure is provided. With reference to FIG. 17, and in an embodiment of block 1602, a device 1700 having a substrate 1702 and including gate structures 1704, 1706, 1708 is provided. In some embodiments, the substrate 1702 may be substantially the same as either of the substrates 102, 152, described above. A region of the substrate 1702 upon which the gate structures 1704, 1706, 1708 are formed, and including regions of the substrate 1702 between adjacent gate structures 1704, 1706, 1708, may include an active region of the substrate 1702. It will be understood that the device 1700 is merely illustrative, and is provided for clarity of discussion. Additionally, in some cases, the device 1700 may include a planar device, a multi-gate device, or other device, as described above. In some embodiments, the device 1700 includes regions 1710, 1712, adjacent to the gate structures 1704, 1706, 1708, where the regions 1710, 1712 may include a source region, a drain region, or a body contact region. In various embodiments, each of the gate structures 1704, 1706, 1708 may include an interfacial layer formed over the substrate 1702, a gate dielectric layer formed over the interfacial layer, and a metal gate (MG) layer 1714 formed over the gate dielectric layer. In some embodiments, each of the interfacial layer, the dielectric layer, and the metal gate layer 1714 of the gate structures 1704, 1706, 1708 may be substantially the same as those described above with respect to the transistor 100 and the FinFET 150. In addition, each of the gate structures 1704, 1706, 1708 may include sidewall spacer layers 1716, 1718. In some cases, each of the sidewall spacer layers 1716, 1718 include materials having different dielectric constant values (e.g., k values), may include one or more of the materials described above, and may be formed by the methods described above.

The method 1600 proceeds to block 1604 where a first dielectric layer is deposited over the substrate. Still referring to FIG. 17, and in an embodiment of block 1604, a dielectric layer 1720 is formed over the substrate 1702 and over each of the gate structures 1704, 1706, 1708. By way of example, the dielectric layer 1720 may include an inter-layer dielectric (ILD) layer that that may include one or more of the materials described above, and may be formed by one or more of the methods described above. In some embodiments, the dielectric layer 1720 has a thickness of about 5-40 nm.

The method 1600 proceeds to block 1606 where a pattern is formed in the dielectric layer. With reference to FIGS. 17 and 18, and in an embodiment of block 1606, a pattern, that includes openings 1722, 1724, is formed within the dielectric layer 1720. In some cases, the openings 1722, 1724 provide access to regions 1710, 1712, adjacent to the gate structures 1704, 1706, 1708, where the regions 1710, 1712 may include a source region, a drain region, or a body contact region. The openings 1722, 1724 may be formed by a suitable combination of lithographic patterning and etching (e.g., wet or dry etching) processes. In some embodiments, the openings 1722, 1724 have a width of about 12-25 nm.

The method 1600 proceeds to block 1608 where metallization and chemical mechanical polishing processes are performed. With reference to FIGS. 18 and 19, and in an embodiment of block 1608, a silicidation process may initially be performed to form a silicide layer on exposed portions of the substrate 1702 (e.g., exposed by the openings 1722, 1724) in the regions 1710, 1712, thus providing a low resistance contact thereto. In some examples, and in a further embodiment of block 1608, a glue or barrier layer 1726 may be formed within each of the openings 1722, 1724. In some cases, the glue or barrier layer 1726 may include Ti, TiN, Ta, TaN, W, or other appropriate material. In some embodiments, the glue or barrier layer 1726 has a thickness of about 1-4 nm. Additionally, and in an embodiment of block 1608, metal layers 1728, 1729 may be formed on the glue or barrier layer 1726 within each of the openings 1722, 1724. In some examples, the metal layers 1728, 1729 may include W, Cu, Co, Ru, Al, Rh, Mo, Ta, Ti, TiN, TaN, WN, silicides, or other suitable conductive material. In some cases, the metal layers 1728 and 1729 may include the same material and may deposited together as part of a single deposition process. In some embodiments, the metal layers 1728, 1729 may have a width of about 10-20 nm and a height of about 30-60 nm. After deposition of the metal layers 1728, 1729, and in an embodiment of block 1608, a chemical mechanical planarization (CMP) process may be performed to remove excess material and planarize the top surface of the device 1700. In contrast to block 708 of the method 700, where a portion of the dielectric layer 820 remains after the CMP process, the CMP process of block 1608 may polish down to (e.g., stops on) a top surface of the metal gate layer 1714, thus removing substantially all of the dielectric layer 1720.

The method 1600 proceeds to block 1610 where a contact etch stop layer and a second dielectric layer are deposited over the substrate. Referring to FIGS. 19 and 20, and in an embodiment of block 1610, a contact etch stop layer (CESL) 1730 is formed over the substrate 1702, and a dielectric layer 1732 is formed over the contact etch stop layer 1730. By way of example, the contact etch stop layer