According to a further aspect of the present invention there may be provided a method of controlling warp in a layered semiconductor structure, the method comprising the steps of: providing a layered semiconductor structure comprising a first layer of III-nitride semiconductor material on a substrate, the layered semiconductor structure having a first warp; and

- forming a porous region of III-nitride semiconductor material over the first layer of III-nitride semiconductor material,
- in which the layered semiconductor structure comprising the porous region has a second warp different from the first warp.

As discussed above, providing a layered semiconductor structure comprising a first layer of semiconductor structure on a substrate frequently introduces a “warp”, or curvature out of flat, into what was originally a flat substrate. This is caused primarily by differences in the material properties between the substrate wafer itself and the material from which the first layer of III-nitride semiconductor material is formed.

The warp in the structure at any point in time may be defined as the difference between the maximum and the minimum distances of the median surface of a free, un-clamped semiconductor structure from a reference plane. As is typical in the art, the reference plane may be defined by three corners of an equilateral triangle.

Wafer warp can be measured according to conventional techniques well known in the art.

The first warp in this case is therefore the warp of the first layer and the substrate before the porous region has been formed.

By forming a porous region over the first layer of III-nitride material on the substrate, the inventors have found that the overall warp of the structure can be altered, and particularly advantageously that it can be reduced or eliminated so that the resulting structure is flat, or at least less warped than it was prior to formation of the porous region.

The second warp in this case is therefore the bow of the semiconductor structure including the porous region, the first layer, and the substrate after the porous region has been formed.

The second warp is preferably closer to zero warp than the first warp. In other words, the semiconductor structure including the porous region, the first layer, and the substrate after the porous region has been formed is flatter, or closer to being completely flat, than the semiconductor structure before the porous region is formed. The method may include the step of tuning the second warp, in which tuning the second warp comprises tuning at least one of the porosity, or the thickness, or the lateral shape and size of the porous region. The thickness and lateral shape and size of the porous region may be tuned by controlling the thickness, shape and size of the n-doped region of III-nitride material deposited prior to porosification. The thickness of the porous region may also be tuned by controlling the depth to which porosification extends downwards into the III-nitride material during electrochemical porosification. The porosity of the porous region may be tuned by controlling the electrochemical porosification parameters and/or by controlling the doping concentration of the n-doped region of III-nitride material deposited prior to porosification.

Tuning the second warp may comprise compensating the first warp that results from the substrate and the first layer of III-nitride material having different thermal coefficients of expansion.

The method may comprise the step of forming, over the porous region, one or more further layers of III-nitride material.

The method may comprise any of the features discussed above in relation to the first aspect of the invention.

Method of Manufacturing a Semiconductor Device

According to a first aspect of the present invention there is provided a method of manufacturing a semiconductor device, the method comprising the steps of manufacturing a layered semiconductor structure having a porous region according to the first aspect of the invention; and forming, over the porous region, a semiconductor device structure.

The method may comprise the step of forming a second layer of III-nitride material over the porous region before forming the semiconductor device structure on the second layer of III-nitride material.

The semiconductor structure may be an LED, a mini-LED, a micro-LED, a power electronics device, or an RF electronics device.

Semiconductor Structure

According to a third aspect of the present invention there is provided a layered semiconductor structure having controllable bow comprising:

- a first layer of III-nitride semiconductor material on a substrate; and
- a porous region of III-nitride semiconductor material over the first layer of III-nitride semiconductor material,
- in which the layered semiconductor structure comprising the porous region has a second bow, and wherein the second bow is tunable by tuning a porosity and/or thickness of the porous region.

The substrate and the first layer of III-nitride semiconductor material may have different thermal coefficients of expansion.

The first III-nitride layer may contain one or more layers or stacks of the following in any sequence: GaN, Al_xGa_1-xN in which x=0-1, or In_yGa_1-yN in which y=0-1.

The porous region may comprise one or more porous layers or stacks of the following in any sequence: GaN, Al_xGa_1-xN in which x=0-1, or In_yGa_1-yN in which y=0-1.

The semiconductor structure may comprise a second layer of III-nitride material over the porous region.

The second III-nitride layer may contain one or more layers or stacks of the following in any sequence: GaN, Al_xGa_1-xN in which x=0-1, or In_yGa_1-yN in which y=0-1.

The porous region may preferably have a porosity of between 10% and 90% porous, preferably between 15% and 80% porous, or between 20% and 70% porous.

The porous region may have a thickness of between 100 nm and 10000 nm, preferably at least 500 nm or 1000 nm.

The porous region may be a porous layer, such that the semiconductor structure comprises a porous layer of III-nitride material over the first layer of III-nitride material. In some embodiments, the porous region may comprise a plurality of porous layers, and optionally a plurality of non-porous layers. In preferred embodiments of the invention, the porous region is a stack of alternating porous and non-porous layers, with the top surface of the stack defining the top of the porous region, and the bottom surface of the stack defining the bottom of the porous region. Further layers of III-nitride material may be formed over a porous region comprising a stack of porous layers of III-nitride material.

In preferred embodiments, an overgrown semiconductor device may be positioned over a single porous layer or a stack of multiple porous layers of III-nitride material. Thus, rather than being a single porous layer of III-nitride material, the porous region may also be a stack of layers of III-nitride material in which at least some layers are porous.