In some embodiments, steps S200, S202, S204 and S206 are executed by the first MMU of the processor or the other component (such as those mentioned above) of the electronic device, and step S208 is executed by the second MMU of the processor or the other component of the electronic device, but the present invention is not limited thereto. In some embodiments, steps S200, S202, S204, S206 and step S208 are executed by the second MMU of the processor or the other component of the electronic device.

FIG. 3 is a schematic diagram of steps S200 to S206 in FIG. 2 in accordance with some embodiments of the present invention. As shown in FIG. 3, a memory space 300 for IPAs of a memory and a memory space 302 for PAs of the memory are present.

Referring to FIG. 2 together with FIG. 3, in steps S200˜S202, the method of the present invention monitors an extant mapping from IPAs to PAs of the memory and determines an allocated block (such as block A in FIG. 3) and a maximum usage location (such as a limitation dotted line 312 in FIG. 3). It should be noticed that, although not illustrating, the allocated block A and the maximum usage location 312 in the memory space 300 correspond to an allocated block A′ and a maximum usage location 312′ in the memory space 302, respectively.

Referring to FIG. 2 together with FIG. 3, in step S204, the method of the present invention determines an offset block (such as block D in FIG. 3) from a rank boundary 310 to the maximum usage location (the limitation dotted line 312). In step S206, the method of the present invention determines a shifted offset block (such as block E in FIG. 3), then an unallocated block is determined (such as block B in FIG. 3). The marks “Free RAM” and “Free PA” in FIG. 3 indicate the corresponding blocks haven't been allocated to any application.

Refers to FIG. 2 together with FIG. 3, in step S208, the method of the present invention executes the remapping from the IPAs to the PAs of the memory, wherein when performing the remapping, the allocated block (such as block A in FIG. 3) is remapped to a target block (such as block F in FIG. 3) of the first rank (such as Rank #0 in FIG. 3). Besides, wherein when performing the remapping, the unallocated block (such as block B in FIG. 3) are remapped to the shifted offset block (such as block E in FIG. 3) of the first rank (such as Rank #0 in FIG. 3), and the remaining IPAs of the first and second ranks (such as block C in FIG. 3) are remapped to the PAs (such as block G in FIG. 3) of the second rank (such as Rank #1 in FIG. 3).

As a result, as shown in FIG. 3, the allocated block A is remapped to a target block F in Rank #0 of a memory. As a result, the present invention reduces the frequencies of switching between different ranks when an application accesses the memory.

In some embodiments, the present invention may allocate the IPAs starting from block D of the memory space 300 (because block A of the memory space 300 has been allocated) to a new application, so that rank 1 (Rank #1) of the memory space 302 may be allocated to the new application. Thus, the present invention also increases the possibility of concentrating the PAs used by a new application to a same rank (such as Rank #1) of the memory.

In some embodiments, the memory space 300 may be an address space of a memory and the memory space 302 may be the physical address space of the memory, but the present invention is not limited thereto.

FIG. 4 is a detailed flow chart of the steps S100˜S102 in FIG. 1 in accordance with some embodiments of the present invention. In some embodiments, when the size of the allocated block is larger than the size of a rank of the memory, the steps in FIG. 4 are executed.

As shown in FIG. 4, the step S100 in FIG. 1 includes the following step. The extant mapping from the IPAs to the PAs of the memory is monitored according to an allocation result of the memory (step S400). The details of step S400 is the same as step S200, so the detailed description for step S400 is omitted herein.

As shown in FIG. 4, the step S102 in FIG. 1 includes the following steps. An allocated block and a maximum usage location are determined in the IPAs (step S402). The allocated block is classified as a permanent part and a transient part (step S404). The size of the transient part is reduced to generate a compressed transient part according to a size limitation, and the permanent part and the compressed transient part form an updated allocated block (step S406). An offset block between a rank boundary of a first rank and an updated maximum usage location is determined in the IPAs, wherein the offset block is a block that has not been allocated and the updated maximum usage location is determined based on the updated allocated block (step S408). A shifted offset block is determined in the PAs of the memory, wherein the shifted offset block starts from the head of the first rank of the memory and has the same size of the offset block (step S410). The remapping from the at least one IPA of the memory to the at least one PA of the memory is executed, wherein when performing the remapping, the updated allocated block in the IP As is remapped to a target block in the PAs of the first rank (step S412). The details of step S402 is the same as step S202, so the detailed description for step S402 is omitted herein. The details of steps S408˜S412 are the same as steps S204˜S208, respectively, so the detailed description for steps S408˜S412 are omitted herein.

FIG. 5 is a schematic diagram of steps S400 to S412 in FIG. 4 in accordance with some embodiments of the present invention. As shown in FIG. 5, a memory space 400 for IPAs of a memory and a memory space 402 for PAs of a memory are present.

Referring to FIG. 4 together with FIG. 5, in steps S400˜S402, the method of the present invention monitors the extant mapping from the IPAs to the PAs of the memory and determines an allocated block (for example, marked as Allocated at block 420 in FIG. 5) and a maximum usage location (for example, marked as solid line 430 in FIG. 5). As shown in FIG. 5, the size (also marked as 430) of the allocated block is larger than the size (for example, marked as 410) of a rank of the memory. Although not illustrating, the allocated block and the maximum memory usage location in the memory space 400 correspond to an allocated block and a maximum memory usage location in the memory space 402, respectively.

Referring to FIG. 4 together with FIG. 5, in step S404, the method of the present invention classifies the allocated block to a permanent part (for example, marked as Permanent at block 424 in FIG. 5) and a transient part (for example, marked as Transient at block 422 in FIG. 5).

Referring to FIG. 4 together with FIG. 5, in step S406, the method of the present invention reduces the size of the transient part (for example, block 422) to generate the compressed transient part (for example, marked as Transient (compressed) in block 426) according to a size limitation (for example, marked as 412), and the permanent part and the compressed transient part form an updated allocated block (for example, block 428 in memory space 400), it should be noticed that, although not illustrating, there is an updated allocated block in memory space 402 which maps to block 428. In some embodiments, in the step S406, the method of the present invention compresses, hot-cold page selects, and/or swaps the transient part to generate the compressed transient part.

Referring to FIG. 4 together with FIG. 5, after step S406, the method of the present invention implements steps S408˜S412. The details of steps S408˜S412 are the same as steps S204˜S208, respectively, so the detailed description for steps S408˜S412 are omitted.

FIG. 6 is a detailed flow chart of steps S100˜S102 in FIG. 1 in accordance with some embodiments of the present invention. The flow chart of FIG. 6 may be executed in the period of memory allocation or in the period of accessing the memory.

As shown in FIG. 6, the step S100 in FIG. 1 includes the following step. The extant mapping from the IPAs and PAs used by the application is monitored according to an allocation result of the memory (step S600). In some embodiments, the details of step S600 is the same as step S200, so the detailed description for step S600 is omitted herein.

As shown in FIG. 6, the step S102 in FIG. 1 includes the following steps. An interesting rank among the ranks of the memory is selected for an application (step 602). In some embodiments, the method of the present invention selects one rank with the most accesses by an application among the ranks as the interesting rank. At least one IPA used by the application that is not mapping to at least one PA of the interesting rank is found, and at least one PA of the interesting rank that has not been allocated is found and reserved (step S604). The remapping from the found at least one IPA to the found at least one PA is executed (step S606). Some embodiments, when executing the steps S602˜S604, can use the memory footprint of the memory as assistant information, but the present invention is not limited thereto.

FIGS. 7A and 7B are schematic diagrams of steps S600 to S606 in FIG. 6 in accordance with some embodiments of the present invention. For example, As shown in FIGS. 7A and 7B, applications 700 and 702 are accessing a dual-rank DRAM. A first mapping from the VAs to the IP As for the application 700 may be shown as follows. Block 0 in the VAs may map to block 6 in the IPAs. Block 1 in the VAs may map to block 11 in the IPAs. Block 5 in the VAs may map to block 14 in the IPAs. In addition, the first mapping from the VAs to the IPAs for the application 702 may be shown as follows. Block 0 in the VAs may map to block 7 in the IPAs. Block 2 in the VAs may map to block 9 in the IPAs. Block 4 in the VAs may map to block 13 in the IPAs. Also, as shown in FIG. 7A, before remapping, an extant mapping from the IPAs to the PAs for the application 700 may be shown as follows. Block 6 in the IPAs may map to block 6 in the PAs. Block 11 in the IPAs may map to block 11 in the PAs. Block 14 in the IP As may map to block 14 in the PAs. In addition, an extant mapping from the IPAs to the PAs for the application 702 may be shown as follows. Block 7 in the IPAs may map to block 7 in the PAs. Block 9 in the IPAs may map to block 9 in the PAs. Block 13 in the IPAs may map to block 13 in the PAs. In some embodiment, the mapping relationship between the VAs and the IPAs, or/and the mapping relationship between the IPAs and the PAs are indicated by an allocation result of the memory.

Referring to FIG. 6 together with FIG. 7A, in step S600, the method of the present invention monitors an extant mapping from the IPAs and PAs used by an application according to an allocation result of the memory. For example, as shown in FIG. 7A, before remapping, an extant mapping from the IPAs to the PAs for the application 700 may be monitored as follows. Block 6 in the IPAs maps to block 6 in the PAs. Block 11 in the IPAs maps to block 11 in the PAs. Block 14 in the IPAs maps to block 14 in the PAs. In addition, an extant mapping from the IPAs to the PAs for the application 702 may be monitored as follows. Block 7 in the IPAs maps to block 7 in the PAs. Block 9 in the IPAs maps to block 9 in the PAs. Block 13 in the IPAs maps to block 13 in the PAs.

Referring to FIG. 6 together with FIG. 7A, in step S602, the method of the present invention selects an interesting rank among the ranks for the application. For example, as shown in FIG. 7A, blocks 0˜9 correspond to rank 0 (Rank #0) and blocks 10˜18 correspond to rank 1 (Rank #1). Since most of the PAs (for example, blocks 11 and 14) the application 700 accesses are in rank 1, but only one PA (for example, block 6) the application 700 accesses is in rank 0, the method of the present invention selects rank 1 as the interesting rank of application 700. Similarly, since most of the PAs (for example, blocks 7 and 9) the application 702 accesses are in rank 0, only one PA (for example, block 13) the application