108. This, in part, is because the sidewall spacer structure 110 is etched more slowly than the etch stop layer 114 and/or the second ILD layer 108 during the etching process. Thus, damage to the second ILD layer 108 may be mitigated during the etching process, thereby mitigating time dependent dielectric breakdown (TDDB) of the interconnect dielectric structure and mitigating current leakage paths between the adjacent conductive wires 112. This increases an endurance and reliability of the integrated chip 300a.

A first spacer height h1 of the sidewall spacer structure 110 is defined between a lower surface of the sidewall spacer structure 110 and a top surface 110ts of the sidewall spacer structure 110. A second spacer height h2 of the sidewall spacer structure 110 is defined between the lower surface of the sidewall spacer structure 110 and the upper surface 110us of the sidewall spacer structure 110. A height h3 of the conductive wires 112 is defined between a lower surface of the conductive wires 112 and the top surface 112ts of the conductive wires 112. In some embodiments, the second spacer height h2 is greater than the height h3 of the conductive wires 112, and the first spacer height h1 is greater than the second spacer height h2. In further embodiments, an overlying upper conductive via 116 continuously extends from the upper surface 110us of the sidewall spacer structure 110, along a sidewall of the sidewall spacer structure 110, to the top surface 112ts of the conductive wire 112. In yet further embodiments, the overlying upper conductive via 116 is laterally offset from the second ILD layer 108 by a non-zero distance.

FIG. 3B illustrates a cross-sectional view of some embodiments of an integrated chip 300b according to some alternative embodiments of the integrated chip 300a of FIG. 3A, where the upper conductive vias 116 are each spaced laterally between opposing sidewalls of the sidewall spacer structure 110.

FIG. 3C illustrates a cross-sectional view of some embodiments of an integrated chip 300c according to some alternative embodiments of the integrated chip 300a of FIG. 3A, where the air-gaps (109 of FIG. 3A) are omitted from the second ILD layer 108. In some embodiments, this may increase a structural integrity of the second ILD layer 108.

FIGS. 4-16 illustrate cross-sectional views 400-1600 of some embodiments of a first method of forming an integrated chip having a plurality of conductive wires and a sidewall spacer structure disposed along sidewalls of the plurality of conductive wires according to the present disclosure. Although the cross-sectional views 400-1600 shown in FIGS. 4-16 are described with reference to a first method, it will be appreciated that the structures shown in FIGS. 4-16 are not limited to the first method but rather may stand alone separate of the first method. Furthermore, although FIGS. 4-16 are described as a series of acts, it will be appreciated that these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

As shown in cross-sectional view 400 of FIG. 4, a lower conductive via 106 is formed over a substrate 102 and within a first inter-level dielectric (ILD) layer 104. In some embodiments, the substrate 102 may, for example, be or comprise a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or another suitable material. In further embodiments, the lower conductive via 106 is formed by a dual damascene process or a single damascene process. In further embodiments, before forming the lower conductive via 106, the first ILD layer 104 is formed over the substrate 102. In some embodiments, the first ILD layer 104 may be deposited by a chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable deposition or growth process. In some embodiments, the lower conductive via 106 may, for example, be or comprise copper, aluminum, cobalt, ruthenium, molybdenum, iridium, chromium, tungsten, nickel, another conductive material, or any combination of the foregoing.

Further, as illustrated in the cross-sectional view 400 of FIG. 4, a conductive layer 402 is deposited over the first ILD layer 104. A lower hard mask layer 404 is deposited over the conductive layer 402. Further, an upper hard mask layer 406 is deposited over the lower hard mask layer 404. In addition, a photoresist mask 408 is formed over the upper hard mask layer 406. In further embodiments, the conductive layer 402, the lower hard mask layer 404, and/or the photoresist mask 408 may, for example, respectively be deposited by PVD, CVD, spin-on, or another suitable deposition or growth process. In yet further embodiments, the upper hard mask layer 406 may, for example, be deposited by PVD, CVD, or another suitable deposition or growth process. In some embodiments, the conductive layer 402 may, for example, be or comprise copper, aluminum, cobalt, ruthenium, molybdenum, iridium, chromium, tungsten, another conductive material, or any combination of the foregoing. In further embodiments, the lower hard mask layer 404 may, for example, be or comprise titanium, titanium nitride, titanium oxide, aluminum oxide, another material, or any combination of the foregoing. In yet further embodiments, the upper hard mask layer 406 may, for example, be or comprise silicon dioxide, silicon, silicon nitride, silicon carbon nitride, silicon oxynitride, another material, or any combination of the foregoing.

As shown in cross-sectional view 500 of FIG. 5, a patterning process is performed on the conductive layer (402 of FIG. 4), the lower hard mask layer 404, and the upper hard mask layer 406 according to the photoresist mask (408 of FIG. 4), thereby forming a plurality of conductive wires 112. In some embodiments, the patterning process includes performing a dry etch process, an ion-beam etching (IBE) process, a reactive-ion etching (RIE) process, a wet etch process, another suitable etch process, or any combination of the foregoing. The patterning process includes exposing the conductive layer (402 of FIG. 4), the lower hard mask layer 404, and the upper hard mask layer 406 to one or more etchants. In further embodiments, the one or more etchants may, for example, be or comprise oxygen (e.g., O₂), chlorine (e.g., Cl₂), fluorine (e.g., F₂), methanol (e.g., CH₃OH), argon, helium, another suitable etchant, or any combination of the foregoing. In yet further embodiments, after performing the patterning process, a removal process is performed to remove the photoresist mask (408 of FIG. 4). In some embodiments, the conductive wires 112 may be formed by a single damascene process, a dual damascene process, or another suitable formation process.

In some embodiments, forming the plurality of conductive wires 112 as illustrated and/or described in FIGS. 4-5 may prevent an issue with voids and/or openings forming within and/or around the plurality of conductive wires. For example, if the conductive wires 112 are formed by depositing a conductive layer (e.g., 402 of FIG. 4) within a conductive feature opening disposed within a dielectric structure, then voids and/or openings may be present within and/or around the conductive wires 112. This may be due to a limitation in deposition tools, which is exacerbated as a sized of the conductive wires 112 is reduced. Thus, forming the plurality of conductive wires 112 as illustrated and/or described in FIGS. 4-5 increases a reliability and endurance of the integrated chip.

As shown in cross-sectional view 600 of FIG. 6, a sidewall spacer structure 110 is formed over the first ILD layer 104, the plurality of conductive wires 112, and the upper hard mask layer 406. In some embodiments, the sidewall spacer structure 110 is deposited by CVD, ALD, or another suitable deposition or growth process. In some embodiments, the sidewall spacer structure 110 may, for example, be or comprise silicon nitride, silicon carbide, silicon oxynitride, aluminum oxide (e.g., Al₂O₃), another dielectric material, or any combination of the foregoing. The sidewall spacer structure 110 is formed such that it extends continuously along a top surface of the first ILD layer 104 and along opposing sidewalls of each conductive wire 112. In yet further embodiments, the sidewall spacer structure 110 and the lower hard mask layer 404 may comprise a same material (e.g., aluminum oxide (e.g., Al₂O₃)).

In some embodiments, the sidewall spacer structure 110 is formed with a thickness t1 that may, for example, be within a range of about 2 to 25 nanometers (nm), 2 to 12 nm, 12 to 25 nm, etc. It will be appreciated that other values for the thickness t1 are also within the scope of the disclosure. In further embodiments, if the thickness t1 is relatively large (e.g., greater than about 25 nm), then an effective dielectric constant of the dielectric materials around the conductive wires 112 may be increased, thereby increasing capacitance between adjacent conductive wires 112. This may decrease a performance of the integrated chip. In yet further embodiments, if the thickness t1 is relatively small (e.g., less than about 2 nm), then the sidewall spacer structure 110 may be over-etched in subsequent processing steps, thereby causing damage to adjacent dielectric structures. This may decrease an overall performance of dielectric structures and/or layers (e.g., delamination, time dependent dielectric breakdown (TDDB), etc.) around the conductive wires 112.

As shown in cross-sectional view 700 of FIG. 7, a second ILD layer 108 is formed over the sidewall spacer structure 110. The second ILD layer 108 is formed such that it is spaced laterally between adjacent conductive wires 112. In some embodiments, the second ILD layer 108 may, for example, be or comprise silicon dioxide (e.g., SiO2), a low-k dielectric material, an extreme low-k dielectric material, another dielectric material, or any combination of the foregoing. In further embodiments, the second ILD layer 108 is formed in such a manner that it comprises a plurality of air-gaps 109 and has porosity. The air-gaps 109 are configured to reduce an effective dielectric constant of the second ILD layer 108 such that, in some embodiments, the effective dielectric constant of the second ILD layer 108 is within a range of about 2 to 3 or another suitable value. By reducing the dielectric constant between adjacent conductive wires 112, a capacitance between the adjacent conductive wires 112 is reduced, thereby increasing a performance of the plurality of conductive wires 112 and the lower conductive via 106. In yet further embodiments, a porosity of the second ILD layer 108 may, for example, be within a range of about 0.1% to 40% or another suitable value.

In some embodiments, the air-gaps 109 may be introduced in the second ILD layer 108 by choosing a suitable formation process. A suitable process for forming the second ILD layer 108 with air-gaps 109 can be a non-conformal deposition process such as, for example, plasma enhance chemical vapor deposition (PECVD). Non-conformal deposition processes create air-gaps 109 in recessed areas such as between adjacent conductive wires 112. An exemplary non-conformal deposition process is PECVD, however, other deposition or growth processes are amenable. In some embodiments, by forming the second ILD layer 108 with a porosity within a range of about 0.1% to 40%, an effective dielectric constant of the second ILD layer 108 may be within a range of about 2 to 3.

As shown in cross-sectional view 800 of FIG. 8, a planarization process (e.g., a chemical mechanical polishing (CMP) process) is performed into the structure of FIG. 7. In some embodiments, the planarization process is performed until an upper surface of the lower hard mask layer 404 is reached. Thus, the planarization process may remove a portion of the second ILD layer 108, a portion of the sidewall spacer structure 110, and/or may remove the upper hard mask layer (406 of FIG. 7).

As shown in cross-sectional view 900 of FIG. 9, a patterning process is performed on the structure of FIG. 8. In some embodiments, the patterning process is configured to remove the lower hard mask layer (404 of FIG. 8) and expose a top surface of the plurality of conductive wires 112. In some embodiments, the patterning process includes performing a dry etch process, a wet etch process, another suitable removal process, or any combination of the foregoing. In yet further embodiments, during the patterning process, the lower hard mask layer (404 of FIG. 8) is etched more quickly than the sidewall spacer structure 110 and/or the second ILD layer 108. In further embodiments, the patterning process may remove a portion of the sidewall spacer structure 110 such that a top surface of the sidewall spacer structure 110 is disposed below a top surface of the second ILD layer 108 (not shown).

As shown in cross-sectional view 1000 of FIG. 10, an etch stop layer 114 is deposited over the second ILD layer 108, the sidewall spacer structure 110, and the conductive wires 112. In some embodiments, the etch stop layer 114 is deposited by, for example, CVD, PVD, ALD, or another suitable deposition or growth process. In further embodiments, the etch stop layer 114 may, for example, be or comprise silicon carbide, silicon oxynitride, silicon oxycarbide, another dielectric material, or any combination of the foregoing. In yet further embodiments, the etch stop layer 114 comprises a different material than the sidewall spacer structure 110.

As shown in cross-sectional view 1100 of FIG. 11, a third ILD layer 118 is deposited over the etch stop layer 114. In some embodiments, the third ILD layer 118 may, for example, be deposited by CVD, PVD, ALD, or another suitable deposition or growth process.

As shown in cross-sectional view 1200 of FIG. 12, a masking layer 1202 is formed over the third ILD layer 118. In some embodiments, the masking layer 1202 is formed such that it comprises a plurality of sidewalls defining a plurality of openings 1204 that overlie the plurality of conductive wires 112. In yet further embodiments, an overlay mismatch between the conductive wires 112 and the masking layer 1202 does not occur during formation of the masking layer 1202. Thus, each opening 1204 directly overlies a corresponding conductive wire 112. In further embodiments, the masking layer 1202 may, for example, be or comprise a hard mask layer, a photoresist layer, another masking layer, or any combination of the foregoing.

As shown in cross-sectional view 1300 of FIG. 13, a first etching process is performed on the third ILD layer 118 according to the masking layer 1202, thereby forming a plurality of openings 1302 within the third ILD layer 118. In some embodiments, the first etching process may over-etch into the etch stop layer 114. The first etching process may, for example, include performing a dry etch process, a reactive-ion etching (RIE) process, another suitable etch process, or any combination of the foregoing. The first etching process may include exposing the third ILD layer 118 to one or more etchants. The one or more etchants may, for example, be or comprise chlorine (e.g., Cl₂), carbon tetrafluoride (e.g., CF₄), fluorine (e.g., F₂), argon, helium, hydrogen, another suitable etchant, or any combination of the foregoing. In further embodiments, because overlay mismatch does not occur between the masking layer 1202 and the conductive wires 112, each opening 1302 directly overlies a corresponding conductive wire 112 and is spaced laterally between opposing sidewalls of the sidewall spacer structure 110.

As shown in cross-sectional view 1400 of FIG. 14, a second etching process is performed on the etch stop layer 114, thereby expanding the openings 1302 and exposing the top surface of the upper conductive wires 112. The second etching process may, for example, include performing a dry etch process, a RIE process, a wet etch process, another suitable etch process, or any combination of the foregoing. The second etching process may include exposing the etch stop layer 114 to one or more etchants. The one or more etchants may, for example, be or comprise carbon tetrafluoride (e.g., CF₄), methylene (e.g., CH₂), hexafluorocyclobutene (e.g., C₄F₆), fluorine (e.g., F₂), chlorine (e.g., Cl₂), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), another suitable etchant, or any combination of the foregoing. In yet further embodiments, a removal process is performed to remove the masking layer (1202 of FIG. 13).

As shown in cross-sectional view 1500 of FIG. 15, a conductive structure 1502 is deposited over the third ILD layer 118, thereby filling the openings (1302 of FIG. 14). The conductive structure 1502 may, for example, be deposited by CVD, PVD, electroless plating, electro plating, sputtering, or another suitable deposition or growth process. In some embodiments, the conductive structure 1502 may, for example, be or comprise copper, aluminum, cobalt, ruthenium, molybdenum, iridium, chromium, tungsten, nickel, another conductive material, or any combination of the foregoing.

As shown in cross-sectional view 1600 of FIG. 16, a planarization process (e.g., a CMP process) is performed into the conductive structure (1502 of FIG. 15), thereby forming a plurality of upper conductive vias 116. In some embodiments, because the overlay mismatch did not occur between the conductive wires 112 and the masking layer (1202 of FIG. 13) (see FIG. 12), each upper conductive via 116 is spaced laterally between opposing sidewalls of the sidewall spacer structure 110 such that the upper conductive vias 116 are laterally offset from the sidewall spacer structure 110 by one or more non-zero distances.

FIGS. 17-21 illustrate cross-sectional views 1700-2100 of some embodiments of a second method of forming an integrated chip having a plurality of conductive wires and a sidewall spacer structure disposed along sidewalls of the plurality of conductive wires according to the present disclosure. Although the cross-sectional views 1700-2100 shown in FIGS. 17-21 are described with reference to a second method, it will be appreciated that the structures shown in FIGS. 17-21 are not limited to the second method but rather may stand alone separate of the second method. Furthermore, although FIGS. 17-21 are described as a series of acts, it will be appreciated that these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

The second method of FIGS. 17-21 may illustrate some alternative embodiments of the first method of FIGS. 4-16. For example, FIGS. 17-21 illustrate cross-sectional views 1700-2100 of some embodiments of acts that may be performed in place of the acts at FIGS. 12-16, such that the first method of FIGS. 4-16 may alternatively proceed from FIGS. 4-11 to FIGS. 17-21 (skipping FIGS. 12-16).

As shown in cross-sectional view 1700 of FIG. 17, a masking layer 1702 is formed over the third ILD layer 118. In some embodiments, a process for forming the masking layer 1702 includes depositing a masking layer material over the third ILD layer 118 and subsequently pattering the masking layer material according to a photomask (not shown) to form a plurality of opposing sidewalls 1703os1, 1703os2. The plurality of opposing sidewalls 1703os1, 1703os2 define a plurality of openings 1703 within the masking layer 1702. In further embodiments, the masking layer 1702 may, for example, be or comprise a hard mask layer, a photoresist layer, another masking layer, or any combination of the foregoing.

In some embodiments, a center of each opening 1703 is aligned with a first substantially straight line 1704 and a center of each conductive wire 112 is aligned with a second substantially straight line 1706. Due to an overlay mismatch between the conductive wires 112 and the photomask (not shown) used to form the masking layer 1702, the center of each opening 1703 is laterally offset from the center of each corresponding conductive wire 112 by a lateral distance d. In some embodiments, as illustrated in FIG. 17, the lateral distance d is non-zero. This overlay mismatch may be due to limitations of light diffraction of photolithography, limitations of mask alignment, limitations of photolithography tools, or the like used to formed the masking layer 1702. Further, occurrence of this overlay mismatch may increase as a size of the conductive wires 112 decreases (i.e., as the integrated chip is scaled down). In further embodiments, the third ILD layer 118 and layers and/or structures underlying the third ILD layer 118 may be formed as illustrated and/or described in FIGS. 4-11.

As shown in cross-sectional view 1800 of FIG. 18, a first etching process is performed on the third ILD layer 118 according to the masking layer 1702, thereby forming a plurality of openings 1802 within the third ILD layer 118. In some embodiments, the first etching process may over-etch into the etch stop layer 114 (not shown). The first etching process may, for example, include performing a dry etch process, a RIE process, another suitable etch process, or any combination of the foregoing. The first etching process may include exposing the third ILD layer 118 to one or more etchants. The one or more etchants may, for example, be or comprise chlorine (e.g., Cl₂), carbon tetrafluoride (e.g., CF₄), fluorine (e.g., F₂), argon, helium, hydrogen, another suitable etchant, or any combination of the foregoing. In further embodiments, due to the overlay mismatch illustrated and/or described in FIG. 17, the openings 1802 directly overlie at least a portion of the sidewall spacer structure 110. In yet further embodiments, during the first etching process, the third ILD layer 118 is etched more quickly than the etch stop layer 114.

As shown in cross-sectional view 1900 of FIG. 19, a second etching process is performed on the etch stop layer 114, thereby expanding the openings 1802 and exposing a top surface of the conductive wires 112. In some embodiments, the second etching process may, for example, include performing a dry etch process, a RIE process, a wet etch process, another suitable etch process, or any combination of the foregoing. The second etching process may include exposing the etch stop layer 114 and/or the sidewall spacer structure 110 to one or more etchants. The one or more etchants may, for example, be or comprise carbon tetrafluoride (e.g., CF₄), methylene (e.g., CH₂), hexafluorocyclobutene (e.g., C₄F₆), fluorine (e.g., F₂), chlorine (e.g., Cl₂), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), another suitable etchant, or any combination of the foregoing.

The second etching process is performed according to the masking layer 1702, and due to the overlay mismatch illustrated and/or described in FIG. 17, the openings 1802 expose an upper surface 110us of the sidewall spacer structure 110. During the second etching process the sidewall spacer structure 110 is etched at a first etch rate and the etch stop layer 114 is etched at a second etch rate. In some embodiments, due to a material, shape, and/or thickness of the sidewall spacer structure 110, the first etch rate is less than the second etch rate, such that the etch stop layer 114 may be etched more quickly than the sidewall spacer structure 110. This, in part, ensures that the second etching process does not over-etch into the second ILD layer 108, thereby mitigating issues related to the overlay mismatch. Thus, damage to the second ILD layer 108 may be mitigated during the second etching process, thereby mitigating a time dependent breakdown (TDDB) of the dielectric layers and/or structures adjacent to the conductive wires 112 and mitigating current leakage between adjacent conductive wires 112. In yet further embodiments, after performing the second etching process, a removal process is performed to remove the masking layer 1702 (not shown). In further embodiments, by virtue of the thickness t1 of the sidewall spacer structure 110 being sufficiently thick (e.g., greater than about 2 nm) the second etching process may not over-etch through the thickness t1 of sidewall spacer structure 110 and damage the second ILD layer 108.

As shown in cross-sectional view 2000 of FIG. 20, a conductive structure 2002 is deposited over the third ILD layer 118, thereby filling the openings (1802 of FIG. 19). In some embodiments, the conductive structure 2002 fills the openings (1802 of FIG. 19) such that the conductive structure 2002 continuously extends from the sidewall spacer structure 110 to the top surface of the conductive wires 112. In yet further embodiments, the sidewall spacer structure 110 is disposed between the conductive structure 2002 and the second ILD layer 108, such that the conductive structure 2002 does not contact the second ILD layer 108. The conductive structure 2002 may, for example, be deposited by CVD, PVD, electroless plating, electro plating, sputtering, or another suitable deposition or growth process. In some embodiments, the conductive structure 2002 may, for example, be or comprise copper, aluminum, cobalt, ruthenium, molybdenum, iridium, chromium, tungsten, nickel, another conductive material, or any combination of the foregoing.

As shown in cross-sectional view 2100 of FIG. 21, a planarization process (e.g., a CMP process) is performed into the conductive structure (2002 of FIG. 20), thereby forming a plurality of upper conductive vias 116. In some embodiments, due to the overlay mismatch between the conductive wires and the masking layer (1702 of FIG. 17) (see FIG. 17), the upper conductive vias 116 continuously extend from the sidewall spacer structure 110 to the conductive wires 112.

FIG. 22 illustrates a method 2200 of forming an integrated chip having a plurality of conductive wires and a sidewall spacer structure disposed along sidewalls of the plurality of conductive wires according to the present disclosure. Although the method 2200 is illustrated and/or described as a series of acts or events, it will be appreciated that the method 2200 is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.