Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

FIG. 1 illustrates a schematic top plan view of a light-emitting display device according to one or more embodiments.

Referring to FIG. 1, a light-emitting display device 1 (hereinafter, also simply referred to as a “display device”) includes a display panel 10, a flexible printed circuit film 20, a driving integrated circuit chip 30, a printed circuit board 40, a power module 50, and the like.

The display panel 10 may include a display area DA corresponding to a screen that displays an image, and circuits and/or wires for generating and/or transmitting various signals applied to the display area DA, and/or a non-display area NA in which wires are located. The non-display area NA may be adjacent to the display area DA, and may surround the display area DA. In FIG. 1, an inner area and an outer area of a boundary line B may be the display area DA and the non-display area NA, respectively.

The display panel 10 may include a display portion 100 and a color-converting portion 200. The display portion 100 and the color-converting portion 200 may be bonded by a sealant 300 located around an edge of the display panel 10 between the display portion 100 and the color-converting portion 200. The color-converting portion 200 may entirely overlap the display portion 100, but the display portion 100 may include an area not covered by the color-converting portion 200 for connection or bonding of the flexible printed circuit film 20. The display portion 100 may include a pad portion for connection or bonding of the flexible printed circuit film 20, and an area in which the pad portion is located may be such that the pad portion may be exposed to the outside. For example, in a lower end portion of the display panel 10, the color-converting portion 200 may be shorter than the display portion 100. The display portion 100 and the color-converting portion 200 may include areas corresponding to the display area DA and the non-display area NA of the display panel 10, respectively.

In the display area DA of the display panel 10, pixels PX may be arranged in a matrix format. In addition, a data line DL for transmitting a data voltage Vdata, a driving voltage line VL1 for transmitting a driving voltage ELVdd, a common voltage line VL2 for transmitting a common voltage ELVss, an initialization voltage line VL3 for transmitting an initialization voltage Vint, and a reference voltage line VL4 for transmitting a reference voltage Vref, may be located in the display area DA. The driving voltage line VL1, the common voltage line VL2, the initialization voltage line VL3, and the reference voltage line VL4 may extend in the second direction DR2. The driving voltage line VL1, the common voltage line VL2, the initialization voltage line VL3, and/or the reference voltage line VL4 may be connected to an auxiliary voltage line extending in the first direction DR1. Each pixel PX may receive the data voltage Vdata, the driving voltage ELVdd, the common voltage ELVss, the initialization voltage Vint, and the reference voltage Vref from these voltage lines DL, VL1, VL2, VL3, and VL4. The driving voltage ELVdd and the common voltage ELVss are power voltages applied to each pixel PX, and the driving voltage line VL1 and the common voltage line VL2 that transmit the power voltages may be referred to as power voltage lines. The driving voltage ELVdd may be a higher voltage than the common voltage ELVss. The driving voltage ELVdd may be referred to as a first power voltage or a high potential power voltage. The common voltage ELVss may be referred to as a second power voltage or a low potential power voltage.

In the non-display area NA of the display panel 10, gate drivers may be located at both sides of the display area DA. The gate driver may be integrated in the non-display area NA. The pixels PX may receive a gate signal generated by the gate driver to receive the data voltage ELVss at a timing (e.g., predetermined timing).

A driving-voltage-transmitting line DVL connected to the driving voltage line VL1, and a common-voltage-transmitting line CVL connected to the common voltage lines VL2 may be located in the non-display area NA of the display panel 10. The driving-voltage-transmitting line DVL and the common-voltage-transmitting line CVL may include portions substantially extending in the second direction DR2, and portions substantially extending in the first direction DR1, respectively. The common-voltage-transmitting line CVL may surround the display area DA. The common voltage lines VL2 may be connected to the common-voltage-transmitting line CVL at lower and upper sides of the display area DA, thereby uniformly providing the common voltage ELVss to the entire display area DA.

One end of the flexible printed circuit film 20 may be connected to or bonded to the display portion 100 of the display panel 10, and the other end thereof may be connected to or bonded to the printed circuit board 40. The driving integrated circuit chip 30 including a data driver for applying the data voltage Vdata to the data line DL may be located in the flexible printed circuit film 20.

The power module 50 that generates the power voltage, such as the driving voltage ELVdd and the common voltage ELVss, may be located in the printed circuit board 40. The power module 50 may be provided in a form of an integrated circuit chip. A signal controller that controls the data driver and the gate driver may be located on the printed circuit board 40.

FIG. 2 illustrates a circuit diagram of one pixel of a light-emitting display device according to one or more embodiments.

Referring to FIG. 2, one pixel PX may include first to fifth transistors T1 to T5, a storage capacitor Cst, a hold capacitor Chold, and a light-emitting diode LED. The light-emitting diode LED may be an organic or inorganic light-emitting diode. The first to fifth transistors T1 to T5 may be N-type transistors. The first to fifth transistors T1 to T5 may include an oxide semiconductor as a semiconductor layer. Some of the first to fifth transistors T1 to T5 may include a silicon semiconductor as a semiconductor layer. Some of the first to fifth transistors T1 to T5 may be P-type transistors.

The first transistor T1 may include a gate electrode (hereinafter referred to as a first gate electrode) connected to a first electrode (hereinafter, also referred to as a first storage electrode) of the storage capacitor Cst, a first electrode connected to a second electrode of the fifth transistor T5, and a second electrode connected to a first electrode of the light-emitting diode LED and to a second electrode (hereinafter referred to as a second storage electrode) of the storage capacitor Cst. The first transistor T1 may be a driving transistor that supplies a driving current to the light-emitting diode LED according to a voltage stored in the storage capacitor Cst. An amount of the driving current may be adjusted according to the data voltage Vdata. The first transistor T1 may further include a lower electrode (also referred to as a lower gate electrode) overlapping a channel area of a semiconductor layer. The lower electrode may be connected to the first electrode of the light-emitting diode LED and to a second electrode of the hold capacitor Chold. The lower electrode may allow to the characteristics of the first transistor T1 to be maintained without being changed during a light-emitting period.

The second transistor T2 may include a gate electrode (hereinafter, also referred to as a second gate electrode) connected to the first gate line GL1, a first electrode connected to the data line DL, and a second electrode connected to the gate electrode of the first transistor T1 and to the second electrode of the storage capacitor Cst. The second transistor T2 may be turned on according to a first gate signal GW to transmit the data voltage Vdata to the gate electrode of the first transistor T1. In this case, the data voltage Vdata may be stored in the first electrode of the storage capacitor Cst.

The third transistor T3 may include a gate electrode (hereinafter, also referred to as a third gate electrode) connected to a second gate line GL2, a first electrode connected to the reference voltage line VL4, and a second electrode connected to the gate electrode of the first transistor T1 and to the first electrode of the storage capacitor Cst. The third transistor T3 may be turned on by a second gate signal GR to transmit the reference voltage Vref to the gate electrode of the first transistor T1 to thereby initialize the gate electrode of the first transistor T1.

The fourth transistor T4 may include a gate electrode (hereinafter, also referred to as a fourth gate electrode) connected to a third gate line GL3, a first electrode connected to the initialization voltage line VL3, and a second electrode connected to the first electrode of the light-emitting diode LED and to the second electrode of the storage capacitor Cst. The fourth transistor T4 may be turned on by a third gate signal GI to transmit the initialization voltage Vint to the first electrode of the light-emitting diode LED to thereby initialize the voltage of the first electrode of the light-emitting diode LED. In this case, the fourth transistor T4 may initialize the lower electrode of the first transistor T1, the second electrode of the storage capacitor Cst, and the second electrode of the hold capacitor Chold.

The fifth transistor T5 may include a gate electrode (hereinafter, also referred to as a fifth gate electrode) connected to a fourth gate line GL4, a first electrode connected to the driving voltage line VL1, and a second electrode connected to the first electrode of the first transistor T1. The fifth transistor T5 may be turned on by a fourth gate signal EM (also referred to as a light-emitting signal) to apply the driving voltage ELVdd to the first electrode of the first transistor T1.

The storage capacitor Cst may include the first electrode connected to the gate electrode of the first transistor T1 and the second electrode connected to the first electrode of the light-emitting diode LED. Depending on the voltage stored in the storage capacitor Cst, the voltage of the gate electrode of the first transistor T1 may be changed, and the driving current outputted from the first transistor T1 may be changed. The storage capacitor Cst may maintain the voltage of the gate electrode of the first transistor T1 constant for one frame.

The hold capacitor Chold may include a first electrode (hereinafter, also referred to as a first hold electrode) connected to the driving voltage line VL1, and a second electrode (hereinafter, also referred to as a second hold electrode) connected to the lower electrode of the first transistor T1 and to the first electrode of the light-emitting diode LED. The hold capacitor Chold may maintain the voltages of the lower electrode of the first transistor T1 and the first electrode of the light-emitting diode LED to be constant during the light-emitting period.

The light-emitting diode LED may include a first electrode connected to the second electrode of the first transistor T1, to the second electrode of the storage capacitor Cst, and to the second electrode of the hold capacitor Chold, and may also include a second electrode connected to the common voltage line VL2. The first electrode and the second electrode of the light-emitting diode LED may be an anode and a cathode, respectively. The first electrode and the second electrode of the light-emitting diode LED may be referred to as a pixel electrode and a common electrode, respectively. The light-emitting diode LED may emit light of luminance (grayscale) according to a driving current generated by the first transistor T1.

An example of the operation of the circuit shown in FIG. 2, for example an operation during one frame, will be described in a case in which all of the first to fifth transistors T1 to T5 are N-type transistors.

One frame may include an initialization period, a compensation period, a write period, and a light-emitting period. When one frame starts, a high-level second gate signal GR may be applied to the third transistor T3 in the initialization period, whereby the gate electrode of the first transistor T1 and the first electrode of the storage capacitor Cst may be initialized to the reference voltage Vref. The reference voltage Vref may be at a level capable of turning on the first transistor T1. In addition, in the initialization period, a high-level third gate signal GI may be applied to the fourth transistor T4, whereby the first electrode of the light-emitting diode LED, the second electrode of the storage capacitor Cst, and the second electrode of the hold capacitor Chold may be initialized to the initialization voltage Vint. In the initialization period, the first gate signal GW and the fourth gate signal EM may be at a low level.

In the compensation period, the third gate signal GI may be changed to a low level, and a high level fourth gate signal EM may be applied, whereby the driving voltage ELVdd may be transmitted to the first electrode of the first transistor T1. In the compensation period, the first gate signal GW may be maintained at a low level, and the third gate signal GI may be maintained at a high level. In the initialization period, because the second electrode of the storage capacitor Cst is charged with the initialization voltage Vint, and because the first transistor T1 is turned on by the reference voltage Vref, in the compensation period, the driving voltage ELVdd applied to the first electrode of the first transistor T1 is transmitted to the second storage electrode of the storage capacitor Cst, so that the voltage of the second storage electrode may increase. When the voltage of the second storage electrode increases and then becomes lower than the voltage of the gate electrode of the first transistor T1 by the threshold voltage Vth of the first transistor T1, the first transistor T1 may be turned off. Because the reference voltage Vref is applied to the gate electrode of the first transistor T1, the voltage of the second storage electrode when the first transistor T1 is turned off may be represented as Equation (1) below.

Voltage
⁢

of
⁢

second
⁢

electrode

=

V
⁢
ref

-

V
⁢
th

(
1
)

Because the second storage electrode and the lower electrode of the first transistor T1 are connected, the voltage of the lower electrode of the first transistor T1 may be represented as Equation (1).

In the write period, the fourth gate signal EM may be changed to a low level, and the first gate signal GW of a high level may be applied, whereby the data voltage Vdata is transmitted to the gate electrode of the first transistor T1 and to the first storage electrode of the storage capacitor Cst through the second transistor T2. In the write period, the second gate signal GR may be changed to a low level, and the third gate signal GI may be maintained at a low level. As the voltage of the first storage electrode is changed, the voltage of the second storage electrode may also be changed. For example, because the reference voltage Vref is previously applied in the write period, and then the data voltage Vdata is applied in the write period, the first storage electrode may be varied by a value obtained by subtracting the reference voltage Vref from the data voltage Vdata. Accordingly, the voltage of the second storage electrode may be varied by the value obtained by subtracting the reference voltage Vref from the data voltage Vdata at the maximum. Because the voltage of the second storage electrode before entering the write period is represented as Equation (1), the voltage of the second storage electrode after the write period may be represented as Equation (2) below.

Voltage
⁢

of
⁢

second
⁢

storage
⁢

electrode

=

V
⁢
ref

-

V
⁢
th

+

α
⁢

(

Vdata
-

V
⁢
ref

)

(
2
)

In the light-emitting period, the high level fourth gate signal EM may be applied, whereby the driving voltage ELVdd may be applied to the first electrode of the first transistor T1 through the fifth transistor T5. In the light-emitting period, the first gate signal GW, the second gate signal GR, and the third gate signal GI may be at a low level. As the driving voltage ELVdd is applied to the first electrode of the first transistor T1, the first transistor T1 may generate and output a driving current, and the light-emitting diode LED may emit light by the driving current. An amount of the driving current that determines the luminance of the light-emitting diode LED may be determined according to a value obtained by subtracting the voltage of the second electrode of the first transistor T1 and the threshold voltage Vth from the voltage of the gate electrode of the first transistor T1. Because the voltage of Equation (2) is the same as the voltage of the second electrode of the first transistor T1, and because the voltage of the gate electrode of the first transistor T1 is the same as the data voltage Vdata, the driving current may be proportional to a value obtained by subtracting the voltage of Equation (2) and the threshold voltage Vth from the data voltage Vdata. In summary, the driving current outputted by the first transistor T1 is represented as Equation (3).

Driving
⁢

current

∝

(

1
-

α

)

⁢

(

Vdata
-

V
⁢
ref

)

(
3
)

As shown in Equation (3), because the driving current is determined regardless of the threshold voltage Vth of the first transistor T1, even if the threshold voltage Vth of the first transistor T1 is varied depending on the pixels PX, the driving current is not affected and display quality may be improved. However, the first transistor T1 may be greatly affected by parasitic capacitance due to a large change in the threshold voltage Vth. Accordingly, stains may occur at a low grayscale and display quality may be deteriorated. Hereinafter, a structure of the display device that may reduce the parasitic capacitance affecting the first transistor T1 will be described.

FIG. 3 illustrates a top plan view of a pixel area of a light-emitting display device according to one or more embodiments, and FIG. 4, FIG. 5, and FIG. 6 respectively illustrate a top plan view according to a manufacturing sequence of the light-emitting display device illustrated in FIG. 3. FIG. 7 illustrates a schematic cross-sectional view of a light-emitting display device according to one or more embodiments.

In FIG. 3 to FIG. 6, a pixel area corresponding to substantially three pixels PX is illustrated, and for example, a first pixel PX1, a second pixel PX2, and a third pixel PX3 are located from left to right. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be a red pixel, a green pixel, and a blue pixel, respectively. In FIG. 3 to FIG. 6, the light-emitting diode LED is not shown, and instead a pixel circuit located thereunder is shown. FIG. 7 schematically illustrates some components for indicating a positional relationship between conductive layers and insulating layers, and may correspond to a schematic cross section of the display portion 100 of the display panel 10 in FIG. 1.

Referring to FIG. 3 to FIG. 7, a first conductive layer that may include first to fourth gate lines GL1 to GL4, an auxiliary driving voltage line VL1a, initialization voltage lines VL3G and VL3RB, a reference voltage line VL4, a lower electrode G1B, and a first storage electrode CE1 may be located on the substrate SB. The first to fourth gate lines GL1 to GL4, the auxiliary driving voltage line VL1a, the initialization voltage lines VL3G and VL3RB, and the reference voltage line VL4 may substantially extend in the first direction DR1.

The initialization voltage lines VL3G and VL3RB may include the first initialization voltage line VL3G for transmitting the initialization voltage Vint applied to the second pixel PX2, and the second initialization voltage line VL3RB for transmitting the initialization voltage Vint applied to the first and third pixels PX1 and PX3. The first initialization voltage line VL3G and the second initialization voltage line VL3RB may transmit the initialization voltages Vint having different levels.

The lower electrode G1B may overlap the first semiconductor C1, for example the channel area of the first transistor T1, and may configure a lower gate electrode of the first transistor T1. The lower electrode G1B may reduce or prevent external light from reaching the channel area of the first transistor T1. Accordingly, the leakage current of the first transistor T1 may be reduced.

The substrate SB may include a material having a rigid characteristic, such as glass, or a material having a flexible characteristic, such as plastic. For example, the substrate SB may be a glass substrate. The substrate SB may include a polymer material, such as polyimide, polyamide, or polyethylene terephthalate. The first conductive layer may include a metal, such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or tungsten (W), and may be a single layer or a multilayer. For example, the first conductive layer may have a double-layered structure, such as titanium (Ti)-copper (Cu).

A first insulating layer IL1 may be located on the substrate SB and the first conductive layer. The first insulating layer IL1 may include an inorganic insulating material, such as a silicon nitride (SiN_x), a silicon oxide (SiO_x), or a silicon oxynitride (SiO_xN_y). The first insulating layer IL1 may be referred to as a buffer layer.

A semiconductor layer that may include first to fifth semiconductors C1 to C5 may be located on the first insulating layer IL1. The first to fifth semiconductors C1 to C5 may include channel areas of the first to fifth transistors T1 to T5, respectively. The semiconductor layer may further include a second storage electrode CE2, a second hold electrode CE3, and a shielding electrode SE.

One end and the other end of the first semiconductor C1 may be connected to the second storage electrode CE2 and the fifth semiconductor C5, respectively. One end and the other end of the second semiconductor C2 may be connected to the data line DL and the third semiconductor C3, respectively. One end and the other end of the third semiconductor C3 may be connected to the reference voltage line VL4 and the second semiconductor C2, respectively. One end and the other end of the fourth semiconductor C4 may be connected to the initialization voltage line VL3 and the second hold electrode CE3, respectively. One end and the other end of the fifth semiconductor C5 may be connected to the auxiliary driving voltage line VL1a and the first semiconductor C1, respectively. One end of the shielding electrode SE may be connected to the fifth semiconductor C5 and the auxiliary driving voltage line VL1a. The second semiconductor C2 and the third semiconductor C3 may be integrally formed. The shielding electrode SE, the fifth semiconductor C5, the first semiconductor C1, the second storage electrode CE2, the second hold electrode CE3, and the fourth semiconductor C4 may be integrally formed. The shielding electrode SE may be located between the first gate line GL1 and the third gate line GL3 in the second direction DR2. The second storage electrode CE2 may overlap the first storage electrode CE1 to form the storage capacitor Cst together with the first storage electrode CE1. The second hold electrode CE3 may overlap the auxiliary driving voltage line VL1a. A portion of the auxiliary driving voltage line VL1a overlapping the second hold electrode CE3 may function as the first hold electrode, and may configure the hold capacitor Chold together with the second hold electrode CE3.

The semiconductor layer may include an oxide semiconductor. For example, the semiconductor layer may include oxide semiconductors, such as an indium-gallium-zinc oxide (IGZO) containing at least one of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and a mixture thereof.

A second insulating layer IL2 may be located on the semiconductor layer. The second insulating layer IL2 may be located in an area overlapping first to fifth gate electrodes G1 to G5 and an auxiliary electrode AE. Alternatively, the second insulating layer IL2 may be formed to substantially cover the entire substrate SB. The second insulating layer IL2 may be an inorganic insulating layer including an inorganic insulating material, such as a silicon oxide, a silicon nitride, or a silicon oxynitride, and may be a single layer or a multilayer. The second insulating layer IL2 may be referred to as a gate insulating layer.

A second conductive layer including the first to fifth gate electrodes G1 to G5 and the auxiliary electrodes AE may be located on the second insulating layer IL2. The first gate electrode G1 may overlap the first semiconductor C1 and the lower electrode G1B. The second gate electrode G2 may overlap the second semiconductor C2 and the first gate line GL1. The third gate electrode G3 may overlap the third semiconductor C3 and the second gate line GL2. The fourth gate electrode G4 may overlap the fourth semiconductor C4 and the third gate line GL3. The fifth gate electrode G5 may overlap the fifth semiconductor C5 and the fourth gate line GL4. In the first to fifth semiconductors C1 to C5, portions overlapping the first to fifth gate electrodes G1 to G5 may be channel areas of the first to fifth transistors T1 to T5.

The auxiliary electrode AE may be adjacent to the first gate electrode G1. The auxiliary electrode AE may at least partially overlap the shielding electrode SE. The auxiliary electrode AE may be in an electrically floating state. The auxiliary electrode AE may overlap the first gate electrode G1 in the first direction DR1 (e.g., may be aligned with the first gate electrode G1 in the first direction DR1). A length of the auxiliary electrode AE may be equal to or greater than a length of the first gate electrode G1. The auxiliary electrode AE may reduce the parasitic capacitance between the first gate electrode G1 and the data line DL and the parasitic capacitance between the first gate electrode G1 and the shielding electrode SE. The second conductive layer may include a metal, such as copper (Cu), aluminum (AI), titanium (Ti), molybdenum (Mo), or tungsten (W), and may be a single layer or a multilayer. For example, the second conductive layer may have a double-layered structure, such as titanium (Ti)-copper (Cu).

After the second conductive layer is formed, portions of the semiconductor layer that are not covered with the second conductive layer may be doped through plasma treatment or doping treatment. As a result, the portions of the semiconductor layer not covered with the second conductive layer may become conductive, and the portions of the semiconductor layer covered with the second conductive layer may become channel areas.

A third insulating layer IL3 may be located on the second conductive layer. The third insulating layer IL3 may be an inorganic insulating layer including an inorganic insulating material, such as a silicon oxide, a silicon nitride, or a silicon oxynitride, and may be a single layer or a multilayer. The third insulating layer IL3 may be referred to as an interlayer insulating layer.

A third conductive layer that may include the data line DL, the driving voltage line VL1, and the auxiliary reference voltage line VL4a may be located on the third insulating layer IL3. The data line DL, the driving voltage line VL1, and the auxiliary reference voltage line VL4a may substantially extend in the second direction DR2. The third conductive layer may further include connecting members SD1, SD2, SD3, SD4, SD5, SDB, SV1, SV3G, SV3RB, and SV4.

The data line DL may be connected to the second semiconductor C2 through a contact hole formed in the third insulating layer IL3. The data line DL may overlap the shielding electrode SE. The shielding electrode SE may be located under the data line DL to shield the voltage of other portions of the pixel PX from being varied even when the data voltage Vdata transmitted through the data line DL varies. A width of the shielding electrode SE may be greater than a width of the data line DL.

The driving voltage line VL1 may be connected to the auxiliary driving voltage line VL1a through a contact hole formed in the first and third insulating layers IL1 and IL3. Accordingly, the driving voltage line VL1 and the auxiliary driving voltage line VL1a may be located in a mesh form, and the driving voltage ELVdd of a substantially uniform level may be transmitted throughout the display area DA. The auxiliary driving voltage line VL1a may be electrically connected to the fifth semiconductor C5 through the connecting member SV1. Because the shielding electrode SE is connected to the fifth semiconductor C5, the driving voltage ELVdd may be applied to the shielding electrode SE. A DC voltage (for example, the common voltage ELVss) other than the driving voltage ELVdd may be applied to the shielding electrode SE. The common voltage line VL2 transmitting the common voltage ELVss may be located at a position of the driving voltage line VL1, and the driving voltage line VL1 and the common voltage line VL2 may be alternately located along the first direction DR1.

The auxiliary reference voltage line VL4a may be connected to the reference voltage line VL4 through a contact hole formed in the first and third insulating layers IL1 and IL3. Accordingly, the reference voltage line VL4 and the auxiliary reference voltage line VL4a may be located in a mesh shape, and the reference voltage Vref of a substantially uniform level may be transmitted throughout the display area DA. The reference voltage line VL4 may be electrically connected to the third semiconductor C3 by the connecting member SV4. A first auxiliary initialization voltage line VL3Ga for transmitting the initialization voltage Vint applied to the second pixel PX2 may be located at the position of the auxiliary reference voltage line VL4a to be connected to the first initialization voltage line VL3G, or a second auxiliary initialization voltage line VL3RBa for transmitting the initialization voltage Vint applied to the first and third pixels PX1 and PX3 may be located thereat to be connected to the second initialization voltage line VL3RB. The auxiliary reference voltage line VL4a, the first auxiliary initialization voltage line VL3Ga, and/or the second auxiliary initialization voltage line VL3RBa may be alternately located along the first direction DR1.

The connecting member SD1 may be connected to the second semiconductor C2 and the first gate electrode G1 through contact holes formed in the third insulating layer IL3, and may be connected to the first storage electrode CE1 through a contact hole formed in the first and third insulating layers IL1 and IL3. The second storage electrode CE2 may include an opening CEO so that the connecting member SD1 may be connected to the first storage electrode CE1. The first gate electrode G1, the first storage electrode CE1, and the second electrode of the second transistor T2 may be electrically connected by the connecting member SD1.

The connecting member SD2 may be connected to the second gate electrode G2 through a contact hole formed in the third insulating layer IL3, and may be connected to the first gate line GL1 through a contact hole formed in the first and third insulating layers IL1 and IL3. The second gate electrode G2 may be electrically connected to the first gate line GL1 by the connecting member SD2.

The connecting member SD3 may be connected to the third gate electrode G3 through a contact hole formed in the third insulating layer IL3, and may be connected to the second gate line GL2 through a contact hole formed in the first and third insulating layers IL1 and IL3. The third gate electrode G3 may be electrically connected to the second gate line GL2 by the connecting member SD3.

The connecting member SD4 may be connected to the fourth gate electrode G4 through a contact hole formed in the third insulating layer IL3, and may be connected to the third gate line GL3 through a contact hole formed in the first and third insulating layers IL1 and IL3. The fourth gate electrode G4 may be electrically connected to the third gate line GL3 by the connecting member SD4.

The connecting member SD5 may be connected to the fifth gate electrode G5 through a contact hole formed in the third insulating layer IL3, and may be connected to the fourth gate line GL4 through a contact hole formed in the first and third insulating layers IL1 and IL3. The fifth gate electrode G5 may be electrically connected to the fourth gate line GL4 by the connecting member SD5.

The connecting member SDB may be connected to the second storage electrode CE2 through a contact hole formed in the third insulating layer IL3, and may be connected to the lower electrode G1B through a contact hole formed in the first and third insulating layers IL1 and IL3. The second storage electrode CE2 and the lower electrode G1B may be electrically connected by the connecting member SDB. The connecting member SDB may be electrically connected to the second electrode of the first transistor T1 through the second storage electrode CE2.

The connecting member SV3G may be connected to the fourth semiconductor C4 of the second pixel PX2 through a contact hole formed in the third insulating layer IL3, and may be connected to the first initialization voltage line VL3G through a contact hole formed in the first and third insulating layers IL1 and IL3. The connecting member SV3RB may be connected to the first pixel PX1 or the fourth semiconductor C4 of the third pixel PX3 through a contact hole formed in the third insulating layer IL3, and may be connected to the second initialization voltage line VL3RB through a contact hole formed in the first and third insulating layers IL1 and IL3. The first electrode of the fourth transistor T4 may be electrically connected to the initialization voltage lines VL3G and VL3RB by the connecting members SV3G and SV3RB.

The third conductive layer may include a metal, such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or tungsten (W), and may be a single layer or a multilayer.

A fourth insulating layer IL4 may be located on the third conductive layer. The fourth insulating layer IL4 may include an organic insulating material, such as a general purpose polymer, such as poly(methyl methacrylate) and polystyrene, a polymer derivative having a phenol-based group, an acryl-based polymer, an imide-based polymer, a polyimide, or a siloxane-based polymer. The fourth insulating layer IL4 may be referred to as a planarization layer.

A first electrode E1 of the light-emitting diode LED may be located on the fourth insulating layer IL4. The first electrode E1 may be connected to the connecting member SDB through a contact hole formed in the fourth insulating layer IL4. Because the connecting member SDB is electrically connected to the second electrode of the first transistor T1, a driving current outputted from the first transistor T1 may be transmitted to the first electrode E1. The first electrode E1 may be referred to as a pixel electrode. The first electrode E1 may be made of a reflective conductive material or a translucent conductive material, or it may be made of a transparent conductive material. The first electrode E1 may include a transparent conductive material, such as an indium tin oxide (ITO) or an indium zinc oxide (IZO). The first electrode E1 may include a metal, such as lithium (Li), calcium (Ca), aluminum (AI), silver (Ag), magnesium (Mg), or gold (Au). The first electrode E1 may have a multi-layered structure, and for example, may have a triple-layered structure, such as ITO-silver (Ag)-ITO.

A pixel defining layer PDL having an opening OP overlapping the first electrode E1 may be located on the first electrode E1. The pixel defining layer PDL may include an organic insulating material, such as an acryl-based polymer, an imide-based polymer, or an amide-based polymer.

A light-emitting layer EL may be located on the first electrode E1. The light-emitting layer EL may be located across the pixels or may be individually located for each pixel. The light-emitting layer EL may include a light-emitting material emitting blue light. The light-emitting layer EL may include a light-emitting material that emits red light or green light in addition to blue light. The light-emitting layer EL may include a plurality of light-emitting layers, and the plurality of light-emitting layers may include light-emitting layers emitting light of the same color or light-emitting layers emitting light of different colors. For example, the light-emitting layer EL may have a structure in which three blue light-emitting layers are stacked. As another example, the light-emitting layer EL may have a structure in which three blue light-emitting layers and one green light-emitting layer are stacked. A functional layer including at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer may be located on the first electrode E1 in addition to the light-emitting layer EL.

A second electrode E2 may be located on the light-emitting layer EL. The second electrode E2 may be located across the pixels. The second electrode E2 may be continuously located on the entire display area DA. The second electrode E2 may be connected to the common voltage line VL2 through a connection electrode that may be located as a same layer as the first electrode E1, and may receive the common voltage ELVss. The second electrode E2 may be referred to as a common electrode. The second electrode E2 may include a metal, such as calcium (Ca), barium (Ba), magnesium (Mg), aluminum (AI), silver (Ag), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and lithium (Li). The second electrode E2 may include a transparent conductive oxide, such as an indium tin oxide (ITO) or an indium zinc oxide (IZO). The second electrode E2 may have a multi-layered structure, and for example, may have a double-layered structure, such as magnesium (Mg)-silver (Ag).

The first electrode E1, the light-emitting layer EL, and the second electrode E2 may configure the light-emitting diode LED, which may be an organic light-emitting diode. The first electrode E1 may be individually provided for each pixel to receive the driving current. The second electrode E2 may be commonly provided to the pixels to receive the common voltage ELVss. The first electrode E1 may be an anode that is a hole injection electrode and the second electrode E2 may be a cathode that is an electron injection electrode, and vice versa. The opening OP of the pixel defining layer PDL may correspond to the light-emitting area of the light-emitting diode LED.

An encapsulation layer TFE may be located on the second electrode E2. The encapsulation layer TFE may seal the light-emitting diodes LED, and may reduce or prevent moisture or oxygen from penetrating from the outside. The encapsulation layer TFE may have a multilayer structure, and for example, may have a triple-layered structure, such as an inorganic layer-organic layer-inorganic layer. Meanwhile, the color-converting portion 200 described with reference to FIG. 1 may be located on the encapsulation layer TFE.

FIG. 8 illustrates an enlarged top plan view of a vicinity where an auxiliary electrode is located in FIG. 3, and FIG. 9 illustrates a schematic cross-sectional view of one or more embodiments taken along the line A-A′ of FIG. 8. In FIG. 9, the constituent elements located on the fourth insulating layer IL4 in FIG. 7 are not shown.

Referring to FIG. 8 and FIG. 9, the auxiliary electrode AE may be located between the shielding electrode SE and the data line DL (e.g., in a thickness direction/third direction DR3). The auxiliary electrode AE may be in an electrically floating state. That is, the auxiliary electrode AE may be an island electrode that is insulated without being connected to another conductor to which a voltage is applied. The auxiliary electrode AE may be biased toward the first gate electrode G1 with respect to a central line of the data line DL with respect to the second direction DR2. Similarly, the auxiliary electrode AE may be biased toward the first gate electrode G1 with respect to a central line of the second direction DR2 of the shielding electrode SE. At least a portion of the auxiliary electrode AE may be located between the data line DL and the first gate electrode G1 (e.g., in plan view). Accordingly, bypass capacitance is formed between the shield electrode SE and the data line DL at the opposite side of the first gate electrode G1, so that parasitic capacitance between the data line DL and the first gate electrode G1 may be reduced.

The auxiliary electrode AE may include a portion overlapping the data line DL and a portion not overlapping the data line (e.g., in the third direction DR3). The auxiliary electrode AE might not overlap the central line of the data line DL with respect to the second direction DR2. In a plan view, a distance d1 between the auxiliary electrode AE and the first gate electrode G1 may be less than a distance d2 between the data line DL and the first gate electrode G1. That is, the auxiliary electrode AE may protrude from the data line DL toward the first gate electrode G1. That is, a portion of the auxiliary electrode AE that does not overlap the data line DL may be located between the data line DL and the first gate electrode G1 in plan view. Accordingly, the auxiliary electrode AE may reduce coupling between the data line DL and the first gate electrode G1, and may reduce parasitic capacitance between the data line DL and the first gate electrode G1. Meanwhile, in a cross-sectional view, a distance between the auxiliary electrode AE and the first gate electrode G1 may be less than a distance between the data line DL and the first gate electrode G1.

The auxiliary electrode AE may not overlap the central line of the shielding electrode SE with respect to the second direction DR2. In a plan view, the distance d1 between the auxiliary electrode AE and the first gate electrode G1 may be less than a distance d3 between the shielding electrode SE and the first gate electrode G1. That is, the auxiliary electrode AE may protrude from the shielding electrode SE toward the first gate electrode G1 in plan view. A portion of the auxiliary electrode AE that does not overlap the shielding electrode SE may be located between the shielding electrode SE and the first gate electrode G1. Accordingly, the auxiliary electrode AE may reduce coupling between the shielding electrode SE and the first gate electrode G1, and may reduce parasitic capacitance between the shielding electrode SE and the first gate electrode G1. Meanwhile, in a cross-sectional view, a distance between the auxiliary electrode AE and the first gate electrode G1 may be less than a distance between the shielding electrode SE and the first gate electrode G1.

The auxiliary electrode AE may be made of the same material as, and in the same process as, the first gate electrode G1. For example, a metal layer may be formed on the second insulating layer IL2 and then patterned to form the second conductive layer including the first gate electrode G1, the auxiliary electrode AE, and the like. The auxiliary electrode AE may be formed of a conductive layer that is different from that of the first gate electrode G1. The auxiliary electrode AE may be formed of a conductive layer that may be located between the shielding electrode SE and the data line DL.

The first transistor T1 including an oxide semiconductor as the first semiconductor C1 may be significantly affected by parasitic capacitance due to a relatively large change in the threshold voltage Vth. Because the data voltage Vdata transmitted through the data line DL is not constant and fluctuates, the change in the gate voltage of the first transistor T1 due to the parasitic capacitance between the first transistor T1 and the data line DL may affect the driving current outputted from the first transistor T1. Accordingly, display quality may be deteriorated, for example, stains may occur in an image displayed in a low grayscale. By forming and arranging the auxiliary electrode AE in the manner described, the parasitic capacitance that affects the operation of the first transistor T1 may be reduced, thereby improving display quality.

FIG. 10 illustrates a top plan view of a pixel area of a light-emitting display device according to one or more embodiments, and FIG. 11, FIG. 12, and FIG. 13 respectively illustrate a top plan view according to a manufacturing sequence of the light-emitting display device illustrated in FIG. 10. FIG. 14 illustrates an enlarged top plan view of a vicinity where an auxiliary electrode is located in FIG. 10, and FIG. 15 illustrates a schematic cross-sectional view of one or more embodiments taken along the line B-B′ of FIG. 14.

In FIG. 10 to FIG. 13, a pixel area corresponding to substantially three pixels PX is illustrated, and for example, a first pixel PX1, a second pixel PX2, and a third pixel PX3 that may respectively correspond to a red pixel, a green pixel, and a blue pixel are located from left to right. In FIG. 10 to FIG. 13, the light-emitting diode LED is not shown, and a pixel circuit located thereunder is shown. In FIG. 15, the constituent elements located on the fourth insulating layer IL4 in FIG. 7 are not shown. Differences from the above-described embodiments will be mainly described, and the same features (for example, the material, such as the substrate, the insulating layer, the conductive layer, the process feature, and the like) will be omitted or briefly described.

Referring to FIG. 10 to FIG. 15, a first conductive layer that may include first to fourth gate lines GL1 to GL4, an auxiliary driving voltage line VL1a, an initialization voltage line VL3, reference voltage lines VL4G and VL4RB, a lower electrode G1B, a first storage electrode CE1, and a shielding electrode SE may be located on a substrate SB. The first to fourth gate lines GL1 to GL4, the auxiliary driving voltage line VL1a, the initialization voltage line VL3, and the reference voltage lines VL4G and VL4RB may substantially extend in the first direction DR1.

The reference voltage lines VL4G and VL4RB may include the first reference voltage line VL4G for transmitting the reference voltage Vref applied to the second pixel PX2, and the second reference voltage line VL4RB for transmitting the reference voltage Vref applied to the first and third pixels PX1 and PX3. The first reference voltage line VL4G and the second reference voltage line VL4RB may transmit the reference voltages Vref having different levels.

The lower electrode G1B may overlap the first semiconductor C1, for example the channel area of the first transistor T1, and may configure the lower gate electrode of the first transistor T1. The lower electrode G1B may reduce or prevent external light from reaching the channel area of the first transistor T1. Accordingly, the leakage current of the first transistor T1 may be reduced. The shielding electrode SE may be connected to the auxiliary driving voltage line VL1a, and the driving voltage ELVdd may be applied to the shielding electrode SE. The shielding electrode SE may be integrally formed with the auxiliary driving voltage line VL1a. The shielding electrode SE may be located between the first gate line GL1 and the fourth gate line GL4 in the second direction DR2 (e.g., in plan view).

A first insulating layer IL1 may be located on the substrate SB and the first conductive layer.

A semiconductor layer that may include first to fifth semiconductors C1 to C5 may be located on the first insulating layer IL1. The first to fifth semiconductors C1 to C5 may include channel areas of the first to fifth transistors T1 to T5, respectively. The semiconductor layer may further include a second storage electrode CE2.

Ends of the first semiconductor C1 may be connected to the second storage electrode CE2 and the fifth semiconductor C5, respectively. Ends of the second semiconductor C2 may be connected to the data line DL and the third semiconductor C3, respectively. Ends of the third semiconductor C3 may be connected to the reference voltage lines VL4G, VL4RB and the second semiconductor C2, respectively. Ends of the fourth semiconductor C4 may be connected to the initialization voltage line VL3 and the second storage electrode CE2, respectively. Ends of the fifth semiconductor C5 may be connected to the driving voltage line VL1 or the auxiliary driving voltage line VL1a and the first semiconductor C1, respectively. One end of the shielding electrode SE may be connected to the fifth semiconductor C5 and the auxiliary driving voltage line VL1a. The second semiconductor C2 and the third semiconductor C3 may be integrally formed. The fifth semiconductor C5, the first semiconductor C1, the second storage electrode CE2, and the fourth semiconductor C4 may be integrally formed. The second storage electrode CE2 may overlap the first storage electrode CE1 to form the storage capacitor Cst together with the first storage electrode CE1.

The semiconductor layer may include an oxide semiconductor. For example, the semiconductor layer may include oxide semiconductors, such as an indium-gallium-zinc oxide (IGZO) containing at least one of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and a mixture thereof.

A second insulating layer IL2 may be located on the semiconductor layer. The second insulating layer IL2 may be located in an area overlapping first to fifth gate electrodes G1 to G5 and an auxiliary electrode AE. Alternatively, the second insulating layer IL2 may be formed to substantially cover the entire substrate SB.

A second conductive layer including the first to fifth gate electrodes G1 to G5 and the auxiliary electrodes AE may be located on the second insulating layer IL2. The first gate electrode G1 may overlap the first semiconductor C1 and the lower electrode G1B. The second gate electrode G2 may overlap the second semiconductor C2 and the first gate line GL1. The third gate electrode G3 may overlap the third semiconductor C3 and the second gate line GL2. The fourth gate electrode G4 may overlap the fourth semiconductor C4 and the third gate line GL3. The fifth gate electrode G5 may overlap the fifth semiconductor C5 and the fourth gate line GL4. In the first to fifth semiconductors C1 to C5, portions overlapping the first to fifth gate electrodes G1 to G5 may be channel areas of the first to fifth transistors T1 to T5.

The auxiliary electrode AE may be adjacent to the first gate electrode G1. The auxiliary electrode AE may at least partially overlap the shielding electrode SE. The auxiliary electrode AE may be in an electrically floating state. That is, the auxiliary electrode AE may be an island electrode that is insulated without being connected to another conductor to which a voltage is applied. The auxiliary electrode AE may reduce the parasitic capacitance between the first gate electrode G1 and the data line DL along with the parasitic capacitance between the first gate electrode G1 and the shielding electrode SE.