When a gate-off signal generated by the gate driver 200 is supplied to the switching transistor Tsw1, the switching transistor Tsw1 may be turned off. When the switching transistor Tsw1 is turned off, a data voltage may not be supplied to the pixel P any longer.

The gate signal GS supplied to the gate line GL may include the gate pulse GP and the gate-off signal.

In order to supply the gate pulses GP1 to GPg to gate lines GL1 to GLg, the gate driver 200 may include stages ST1 to STg connected to the gate lines GL1 to GLg, as illustrated in FIG. 4.

Each of the stages ST1 to STg may be connected to one gate line GL, but may also be connected to at least two gate lines GL. Hereinafter, for convenience of description, as illustrated in FIG. 4, a gate driver 200 in which each of the stages ST1 to STg is connected to one gate line GL will be described as an example of the present disclosure.

At least one of the signals output from the stage ST in which the gate pulse GP is output may be supplied to another stage ST to drive another stage ST. Accordingly, a gate pulse may be output in another stage ST.

The gate control signals GCS may be supplied to the stages ST through the gate control signal line GCL.

The gate control signals GCS may be supplied to the stages ST through the gate control signal line GCL.

The gate control signal line GCL may be, for example, a line which supplies the gate clock needed at the stage ST, or a line which supplies the power needed at the stage ST. Accordingly, at least one gate control signal line GCL may be provided in the non-display area NDA.

In the following description, as illustrated in FIG. 4, a region equipped with a gate control signal line GCL in the non-display areas NDA may be referred to as a line non-display area NDA_L, and a region equipped with non-display transistors configuring the stages ST in the non-display areas NDA may be referred to as a transistor non-display area NDA_T.

A schematic structure of the stage ST performing the above-described function is illustrated in FIG. 5.

The stage ST may include a plurality of non-display transistors. In order to describe a schematic structure of the stage ST, in FIG. 5, a stage ST including four non-display transistors Tst, Trs, Tu, and Td is illustrated as an example of a stage ST applied to a light emitting display apparatus according to the present disclosure.

In this case, a high voltage line 11 to which a high voltage GVDD is supplied, a gate clock line 12 to which a gate clock GCLK is supplied, a first low voltage line 13 to which a first low voltage GVSS1 is supplied, and a second low voltage line to which a second low voltage GVSS2 is supplied may be included in gate control signal lines GCL.

A start transistor Tst may be turned on based on a start signal Vst and may supply a high voltage GVDD to a gate of the pull-up transistor Tu through a circuit unit or circuit and a Q node Q. Here, the start signal Vst may be transferred from the control driver 400, or may be a signal which is transferred from a previous stage. In this case, the previous stage may be a stage which is directly adjacent to a currently driven stage ST, or may be a stage which is separated from the currently driven stage with at least one stage therebetween.

The pull-up transistor Tu may be turned on by the high voltage GVDD to output the gate pulse GP to the gate line GL. In this case, a gate pulse GP having a high level may be output to the gate line GL.

In this case, the pull-down transistor Td may be turned off by the first low voltage GVSS1 supplied to the gate of the pull-down transistor Td through the circuit unit C and a Qb node Qb. Accordingly, only the gate pulse GP passing through the pull-up transistor Tu may be output to the gate line GL.

When the start transistor Tst is turned off and the reset transistor Trs is turned on by a reset signal Rest, the first low voltage GVSS1 may be supplied to the pull-up transistor Tu through the reset transistor Trs and the circuit unit C, and thus, the pull-up transistor Tu may be turned off.

In this case, the high voltage GVDD may be supplied to the gate of the pull-down transistor Td through the circuit unit C and the Qb node Qb, and thus, the pull-down transistor Td may be turned on. When the pull-down transistor Td is turned on, the second low voltage GVSS2 may be supplied to the gate line GL through the pull-down transistor Td. The second low voltage GVSS2 may be the same voltage as the first low voltage EVSS1, or may be a different voltage from the first low voltage EVSS1.

That is, because the pull-up transistor Tu is turned off when the pull-down transistor Td is turned on, the second low voltage GVSS2 with a low level passing through the pull-down transistor Td may be output to the gate line GL. The second low voltage GVSS2 supplied to the gate line GL through the pull-down transistor Td may be a gate-off signal. The switching transistor Tsw1 may be turned off by the gate-off signal supplied to the gate of the switching transistor Tsw1. Although it is described that a transistor is turned off by a low voltage and is turned on by a high voltage, embodiments are not limited thereto. As an example, a transistor may be turned off by a high voltage and is turned on by a low voltage, depending on the type of the transistor.

The structure and driving method of the stage ST may be variously changed based on the structure and driving method described with reference to FIG. 5.

For example, the structure of the circuit unit C illustrated in FIG. 5 maybe variously changed, and at least one non-display transistor may be provided in the circuit unit C.

That is, in addition to the four non-display transistors Tst, Trs, Tu, and Td illustrated in FIG. 5, other non-display transistors may be further provided in the stage ST.

Accordingly, a driving method of the stage ST may also be variously changed based on the structure and number of non-display transistors.

A non-display light emitting device NED may be connected to the non-display transistor provided in the stage ST applied to the present disclosure, and the non-display light emitting device NED may be provided to overlap the non-display transistor.

In this case, non-display light emitting devices NED may be provided in all non-display transistors provided in the stage ST.

For example, as illustrated in FIG. 5, each of the four non-display transistors Tst, Trs, Tu, and Td may be provided with a non-display light emitting device NED.

An anode (hereinafter, simply referred to as a non-display anode) of the non-display light emitting device NED may be connected to any one of the non-display transistors, a cathode (hereinafter, simply referred to as a non-display cathode) of the non-display light emitting device NED may be electrically connected to the power supply 500, and a light emitting layer may be provided between the non-display anode and the non-display cathode. The second voltage EVSS may be supplied to the non-display cathode.

For example, the second voltage EVSS may be commonly supplied to the cathode of the light emitting device illustrated in FIG. 2 and the non-display cathode of the non-display light emitting device NED illustrated in FIG. 5. The second voltage EVSS is also referred to as a cathode voltage in the following description.

In this case, one non-display light emitting device NED may be commonly connected to two non-display transistors adjacent and connected to each other, and the commonly connected non-display light emitting device NED may be provided to overlap both the non-display transistors.

For example, the non-display anode of the non-display light emitting device NED connected to the start transistor Tst among the non-display transistors illustrated in FIG. 5 and the non-display anode of the non-display light emitting device NED connected to the reset transistor Trs among the non-display transistors illustrated in FIG. 5 maybe commonly connected to a node between the start transistor Tst and reset transistor Trs. Accordingly, the two non-display light emitting devices NED may be substantially one non-display light emitting device NED. In this case, one non-display light emitting device NED connected to the node between the start transistor Tst and the reset transistor Trs may be provided to overlap both the start transistor Tst and the reset transistor Trs.

Moreover, the non-display anode of the non-display light emitting device NED connected to the pull-up transistor Tu illustrated in FIG. 5 and the non-display anode of the non-display light emitting device NED connected to the pull-down transistor Td may be commonly connected to the node between the pull-up transistor Tu and the pull-down transistor Td. Accordingly, the two non-display light emitting devices NED may be substantially one non-display light emitting device NED. In this case, one non-display light emitting device NED connected to the node between the pull-up transistor Tu and the pull-down transistor Td may be provided to overlap both the pull-up transistor Tu and the pull-down transistor Td. Moreover, because the node between the pull-up transistor Tu and the pull-down transistor Td is connected to a gate line GL, the gate signal GS may be supplied to the gate line GL through the node between the pull-up transistor Tu and pull-down transistor Td.

In addition to the four non-display transistors Tst, Trs, Tu, and Td), all non-display transistors provided in the stage ST may be provided with a non-display light emitting device NED, and each of the non-display light emitting devices NED may be provided to overlap at least one non-display transistor.

FIG. 6 is an example diagram illustrating a stage applied to a light emitting display apparatus according to the present disclosure and pixels adjacent to the stage, FIG. 7 is an example diagram illustrating a cross-sectional surface taken along line A-A′ illustrated in FIG. 6, FIG. 8 is an example diagram illustrating a cross-sectional surface taken along line B-B′ illustrated in FIG. 6, and FIG. 9 is an example diagram illustrating a cross-sectional surface taken along line C-C′ illustrated in FIG. 6. In the following description, details which are the same as or similar to details described above with reference to FIGS. 1 to 5 are omitted or will be simply described.

The light emitting display apparatus according to the present disclosure may include a light emitting display panel 100 divided into a display area DA provided with pixels P including light emitting devices ED and a non-display area NDA outside the display area DA, a power supply unit 500 supplying a power to the light emitting display panel 100, a data driver 300, a gate driver 200, and a control driver 400.

Particularly, a gate driver 200 which supplies gate pulses GP to the gate lines GL provided in the light emitting display panel 100 may be included in the non-display area NDA.

The gate driver 200 may include stages STs connected to the gate lines GL, each of the stages ST may be provided with non-display transistors NTFT, a non-display light emitting device NED may be connected to the non-display transistor NTFT.

In the following description, the non-display area NDA provided with the gate driver 200 may be divided into a line non-display area NDA_L and a transistor non-display area NDA_T.

As illustrated in FIG. 6, the non-display transistors NTFT included in the stage ST may be provided in the transistor non-display area NDA_T and the gate control signal line GCL may be provided in the line non-display area NDA_L.

The non-display transistors NTFT and the gate control signal lines GCL may be provided to overlap the non-display light emitting devices NED.

The non-display transistors NTFT provided in the transistor non-display area NDA_T may include, for example, a start transistor Tst, a reset transistor Trs, a pull-up transistor Tu, and a pull-down transistor Td, which are illustrated in FIG. 5.

As illustrated in FIG. 6, each of the non-display light emitting devices NED may overlap the non-display transistor NTFT. That is, FIG. 6 schematically illustrates positions of the non-display transistors NTFT provided in the stage ST, and schematically illustrates positions of the non-display light emitting devices NED overlapping the non-display transistors NTFT.

In this case, as described above, one non-display light emitting device NED may overlap at least one non-display transistor NTFT.

Moreover, among the non-display transistors NTFT provided in the stage ST, there may be a non-display transistor NTFT which does not overlap a non-display light emitting device NED. However, in order to determine whether all non-display transistors NTFT provided in the stage ST are normally operating, all of the non-display transistors NTFT provided in the stage ST may overlap the non-display light emitting device NED.

The gate control signal lines GCL provided in the line non-display area NDA_L may be lines which supply the gate clocks needed in the stage ST or lines which supply the power needed in the stage ST, as described above with reference to FIG. 4.

A non-display light emitting device NED overlapping the gate control signal lines GCL may be provided in each of the stages ST, as illustrated in FIG. 6.

In this case, the non-display light emitting device NED overlapping the gate control signal lines GCL may be connected to any one of the gate control signal lines GCL.

For example, a kth non-display light emitting device overlapping the gate control signal lines GCL in a kth stage among the stages ST may be connected to a first gate control signal line GCL1 among the gate control signal lines GCL, and a k+1th non-display light emitting device overlapping the gate control signal lines GCL in a k+1th stage among the stages ST may be connected to a second gate control signal line GCL2 among the gate control signal lines GCL. K is a natural number less than g.

To provide an additional description, when the stage ST illustrated in FIG. 6 is the kth stage, the kth stage may be connected to the first gate control signal line GCL1 among the gate control signal lines GCL illustrated in FIG. 6, and the k+1th stage provided at an upper end or a lower end of the stage illustrated in FIG. 6 maybe connected to the second gate signal line GCL among the gate control signal lines GCL illustrated in FIG. 6.

The number of the stages ST may be greater than the number of the gate control signal lines GCL. Therefore, at least two non-display light emitting devices NED may be connected to one gate control signal line GCL, and at least two non-display light emitting devices NED may be provided in different stages ST. In this case, at least two non-display light emitting devices NED connected to one gate control signal line GCL may be provided to be apart from each other.

However, one non-display light emitting device NED connected to one gate control signal line GCL and overlapping all gate control signal lines GCL may be formed continuously in a plurality of stages ST.

For example, when the number of the gate control signal lines GCL is ten, ten non-display light emitting devices NED may be provided in the line non-display area NDA_L. In this case, the ten non-display light emitting devices NED may be arranged in a row along the line non-display area NDA_L, and each of the ten non-display light emitting devices NED may be provided continuously in at least two stages ST.

Moreover, each of the gate control signal lines may overlap a non-display light emitting device.

For example, when the number of gate control signal lines GCL is ten, ten non-display light emitting devices NED may be provided in the line non-display area NDA_L. In this case, each of the ten non-display light emitting devices NED may be provided to overlap one gate control signal line GCL.

Therefore, the ten non-display light emitting devices NED may be arranged in parallel with each other, and each of the ten gate non-display light emitting devices NED may be provided to overlap one gate control signal line GCL.

Therefore, ten gate control signal lines GCL may be arranged in parallel with each other in the line non-display area NDA_L of one stage ST, and each of the ten gate control signal lines GCL may be provided to overlap one gate control signal line GCL.

In this case, one non-display light emitting device NED may be provided continuously in all stages ST, but may be divided into at least two portions. However, the at least two portions may be commonly connected to one gate control signal line GCL.

The pixels P may be provided in the display area DA. The stage ST may be connected to at least one gate line GL, and pixels P may be connected to the gate line GL.

Hereinafter, cross-sectional surfaces of the line non-display area NDA_L, the transistor non-display area NDA_T, and the display area DA illustrated in FIG. 6 will be described with reference to FIGS. 6 to 9.

First, FIG. 7 is an example diagram illustrating a cross-sectional surface taken along line A-A′ illustrated in FIG. 6. That is, a cross sectional surface illustrated in FIG. 7 is an example diagram illustrating a cross sectional surface of a pixel P provided in the display area DA.

As illustrated in FIG. 7, the light emitting display panel 100 applied to the present disclosure may include a substrate 101, a pixel driving circuit layer PDL provided at an upper end of the substrate 101, a planarization layer (also referred to as an overcoating layer OC) 106 provided on at upper end of the pixel driving circuit layer PDL to cover the pixel driving circuit layer PDL, an anode AN provided at an upper end of the planarization layer 106, a light emitting layer EL provided at an upper end of the anode AN, a cathode CA provided at an upper end of the light emitting layer EL, and an encapsulation layer 107 covering the cathode CA. An outer portion of the anode AN may be surrounded by a bank BK.

The substrate 101 may be a glass substrate or a plastic substrate, and moreover, may be formed of various kinds of films. Embodiments are not limited thereto. As an example, the substrate 101 may be also a substrate of another material, such as metal or semiconductors. As an example, the substrate may be single layer or multi-layers structure in which organic material layer and inorganic material layer are stacked alternatively. As an example, the plastic may be polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), etc.

The pixel driving circuit layer PDL including a driving transistor Tdr may be provided on the substrate 101. A pixel driving circuit PDC including the driving transistor Tdr may be provided in the pixel driving circuit layer PDL. The pixel driving circuit PDC, as described above with reference to FIG. 2, may include a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2. That is, the pixel driving circuit layer PDL may include at least two transistors.

Each of the transistors may include an active layer ACT including a semiconductor, a gate insulation layer 103 which is provided on the active layer ACT, and a gate Gate which is provided on the gate insulation layer 103. The gate Gate may be covered by a passivation layer 105, and the passivation layer 105 may be covered by the planarization layer 106.

For example, the driving transistor Tdr illustrated in FIG. 7 may include an active layer ACT which is provided on a buffer 102, a gate insulation layer 103 which is provided on the active layer ACT, a gate Gate which is provided on the gate insulation layer 103, and a passivation layer 105 which covers an upper end of the gate Gate. In this case, the other transistors may be configured as a type similar to the driving transistor Tdr illustrated in FIG. 7.

However, a structure of each of the driving transistor Tdr and the other transistors is not limited to a structure of the driving transistor Tdr illustrated in FIG. 7. That is, a structure of each of the driving transistor Tdr and the other transistors may be changed to various types.

In this case, as illustrated in FIG. 7, a light blocking plate LS may be provided under the driving transistor Tdr, so as to block external light penetrating into the active layer ACT in performing a manufacturing process of a light emitting display apparatus or in using the light emitting display apparatus. Also, the light blocking plate LS may be connected to one of a gate, a first gate electrode, and a second gate electrode of the driving transistor Tdr. Also, the light blocking plate LS may be used as various lines, for example, as a data line. Accordingly, the light blocking plate LS may be provided in a floating state and may also be connected to a signal line through which a voltage is supplied.

The light blocking plate LS may be provided under the other transistors included in the pixel driving circuit layer PDL, or may not be provided under the other transistors included in the pixel driving circuit layer PDL. That is, the light blocking plate LS may be provided at a lower end of the other transistor requiring blocking of light, in addition to a lower end of the driving transistor Tdr, or may be provided in a region requiring blocking of light among regions where a transistor is not provided. As an example, the light blocking plate LS may be omitted.

The light blocking plate LS may be provided on the substrate 101 and may be covered by the buffer 102, and the active layer ACT may be provided on the buffer 102.

Moreover, the pixel driving circuit layer PDL may include a data line DL, a gate line GL, a sensing control line SCL, a sensing line SL, and a voltage supply line PLA, which are connected to the pixel driving circuit PDC.

Each of the buffer 102, the gate insulation layer 103, and the passivation layer 105 may be formed of at least one inorganic layer or at least one organic layer, or may be formed of at least one inorganic layer and at least one organic layer. The buffer 102, the gate insulation layer 103, and the passivation layer 105 may be referred to as an insulation layer.

The gate Gate of the driving transistor Tdr and the light blocking plate LS may be formed of metal.

A color filter CF may be provided at an upper end of the passivation layer 105. For example, when a light generated in the light emitting device ED illustrated in FIG. 7 is output in a direction toward the substrate 101, as illustrated in FIG. 7, the color filter CF may be provided at an upper end of the passivation layer 105. However, the position of the color filter CF may be variously changed. For example, the color filter CF may be provided inside the planarization layer 106 or may be provided at an upper end of the planarization layer 106. A type where light is output in a direction toward the substrate 101 as illustrated in FIG. 7 maybe referred to as a bottom emission type. As an example, the color filter CF may be omitted.

The color filter CF may be provided for each pixel P, and the color of the color filter CF may be variously changed. For example, when a unit pixel includes a red pixel, a green pixel, a blue pixel, and a white pixel, one of a red color filter, a green color filter, and a blue color filter may be provided in a pixel, and a white pixel may not be provided with a color filter. That is, color filters CF of various colors may be provided in the light emitting display panel 100.

The planarization layer 106 may be provided on the pixel driving circuit layer PDL and the color filter CF.

The planarization layer 106 may perform a function of planarizing an upper surface of the pixel driving circuit layer PDL which is not flat. That is, the planarization layer 106 may be formed to have a thickness which is greater than that of the pixel driving circuit layer PDL, and thus, the upper surface of the planarization layer 106 may be a flat surface. The planarization layer 106 may be formed of at least one inorganic layer or at least one organic layer, or may be formed of at least one inorganic layer and at least one organic layer.

The anode AN may be provided on the planarization layer 106. The anode AN may configure the light emitting device ED. The anode AN, as illustrated in FIG. 7, may be electrically connected to the driving transistor Tdr included in the pixel driving circuit layer PDL and may be patterned for each pixel 110.

In a light emitting display panel 100 using the bottom emission type, the anode AN may be formed of a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO), without being limited thereto. As an example, in a light emitting display panel 100 using the top emission type, the anode AN may be formed of a transparent electrode or an opaque material.

That is, light emitted from the light emitting layer EL should pass through the anode AN. Accordingly, the anode AN may be formed as a transparent electrode.

A bank BK may be provided on the planarization layer 106, and an opening portion through which the anode AN is exposed may be formed by the bank BK.

That is, the bank BK may cover outer portions of the anode electrode AE, and thus, the opening portion through which light is output in one pixel 110 may be formed. That is, a region, uncovered by the bank BK, of the anode AN illustrated in FIG. 7 maybe the opening portion.

To provide an additional description, the bank BN may cover outer portions of the anode AN and may be provided in the display area DA of the substrate 101 so that the anode AN is exposed.

The bank BN may prevent a phenomenon where lights overlap between adjacent pixels.

The bank BN may be formed of at least one inorganic layer or at least one organic layer, or may be formed of at least one inorganic layer and at least one organic layer.

The light emitting layer EL may be provided on a whole surface of the substrate 101 to cover the anode AN and the bank BN.

The light emitting layer EL may include one of an organic light emitting layer, an inorganic light emitting layer, and a quantum dot light emitting layer, or may include a stack or combination structure of an organic light emitting layer (or an inorganic light emitting layer) and a quantum dot light emitting layer.

The light emitting layer EL may include a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron injection layer (EIL), an electron transport layer (ETL), an electron blocking layer (EBL), and a charge generating layer (CGL).

In a case where the light emitting layer EL emits white light, the light emitting layer EL may include hole injection layer (HIL)/hole transport layer (HTL), a blue organic layer, electron injection layer (EIL)/charge generating layer (CGL)/electron transport layer (ETL), a red organic layer, a yellow-green organic layer, electron injection layer (EIL)/charge generating layer (CGL)/electron transport layer (ETL), a blue organic layer, electron injection layer (EIL)/electron transport layer (ETL), and an organic buffer, which are sequentially stacked on the anode AN.

The light emitting layer EL may include layers having various stack orders, in addition to layers having a stack order described above.

The cathode CA may be provided on the light emitting layer EL, and particularly, may be provided in a plate shape in the display area DA.

The light emitting display panel 110 applied to the present disclosure may use the bottom emission type as described above. In this case, the cathode CA may perform a function of reflecting light, emitted from the light emitting layer EL, toward the anode AN. To this end, the cathode CA may include metal such as copper or aluminum.

The cathode CA may be covered by the encapsulation layer 107. The encapsulation layer 107 may be formed of at least one organic layer or at least one inorganic layer, or may be formed of at least one inorganic layer and at least one organic layer. Water and oxygen flowing in from the outside may be blocked by the encapsulation layer 107, and thus, may not penetrate into the light emitting layer EL.

Next, FIG. 8 is an example diagram illustrating a cross-sectional surface taken along line B-B′ illustrated in FIG. 6. That is, the cross-sectional surface illustrated in FIG. 8 is an example diagram illustrating the cross-sectional surface of the non-display transistor NTFT and the non-display light emitting device NED which are provided in the transistor non-display area NDA_T.

The transistor non-display area NDA_T may be adjacent to the display area DA, as illustrated in FIG. 6, and may share various layers configuring the display area DA.

For example, the transistor non-display area NDA_T, as illustrated in FIG. 8, may include a substrate 101, a buffer 102 provided on the substrate 101, a non-display active layer ACTa provided on the buffer 102, a gate insulation layer 103 provided on the non-display active layer ACTa, gate layers 104 provided on the gate insulation layer 103, a light blocking layer LSL provided on the gate layers 104, a non-display anode NAN provided on the light blocking layer LSL and connected to any one of the gate layers 104, a non-display bank NBK covering the outer portion of the non-display anode NAN, a non-display light emitting layer NEL provided on the non-display bank NBK, a non-display cathode NCA provided on the non-display light emitting layer NEL, and an encapsulation layer 107 covering the non-display cathode NCA.

Here, the substrate 101, the buffer 102, the insulation layer 103, and the encapsulation layer 107 may correspond to the substrate 101, the buffer 102, the insulation layer 103, and the encapsulation layer 107 described above with reference to FIG. 7. That is, the buffer 102, the insulation layer 103, and the encapsulation layer 107 may be provided on the whole substrate 101. Furthermore, the passivation layer 105 and the planarization layer 106 may be further provided at an upper end of the gate layers 104 illustrated in FIG. 8, and in this case, the non-display anode NAN may be connected to any one of the gate layers 104 through contact holes provided in the passivation layer 105 and the planarization layer 106.

That is, the non-display active layer ACTa, the gate insulation layer 103, and the gate layers 104 illustrated in FIG. 8 may configure the non-display transistor NTFT.

Moreover, the non-display anode NAN, the non-display light emitting layer NEL, and the non-display cathode NCA may configure the non-display light emitting device NED.

In this case, one of the gate layers 104 may be a gate of the non-display transistor NTFT, another may be a first terminal of the non-display transistor NTFT, and another may be a second terminal of the non-display transistor NTFT.

That is, as illustrated in FIG. 8, the non-display transistor NTFT may be connected to the non-display light emitting device NED. Particularly, the non-display transistor NTFT may be connected to the non-display anode NAN of the non-display light emitting device NED, and the non-display light emitting device NED may be provided to overlap the non-display transistor NTFT. That is, the non-display light emitting device NED may be provided at an upper end or a lower end of the non-display transistor NTFT in the cross-sectional surface of the light emitting display panel 100, and FIG. 8 illustrates a light emitting display panel 100 provided with a non-display light emitting device NED at an upper end of the non-display transistor NTFT.

In this case, a first terminal or a second terminal of the non-display transistor NTFT may be connected to the non-display anode NAN.

Therefore, the non-display light emitting device NED may output light by using the current and voltage supplied to the first or second terminal of the non-display transistor NTFT.

When light is output from the non-display light emitting device NED, the temperature of the non-display transistor NTFT connected to the non-display light emitting device NED can increase rapidly. Accordingly, it may be quickly determined whether the non-display transistor NTFT is normally driven at a high temperature.

Therefore, according to the present disclosure, it may be quickly determined whether the gate driver 200 is normally driven at a high temperature.

In this case, if the non-display transistor NTFT is not normally driven, current and voltage may not be normally supplied to the first or second terminal, and thus light may not be output from the non-display light emitting device NED.

The non-display light emitting device NED in which light is not output may be identified through various cameras or magnifiers.

It may be determined that the non-display transistor NTFT connected to the non-display light emitting device NED, which does not output light, does not operate normally.

That is, according to the present disclosure, among the numerous non-display transistors NTFT configuring the gate driver 200, a non-display transistor NTFT which does not operate normally can be quickly and simply identified. Accordingly, whether the gate driver 200 is defective and a specific position of the defect may be quickly and accurately determined.

A light blocking layer LSL which blocks light may be provided at an upper end or a lower end of the non-display light emitting device NED. When the light emitting display panel 100 illustrated in FIGS. 6 to 9 uses a bottom emission type, the light blocking layer LSL may be provided at a lower end of the non-display light emitting device NED, as illustrated in FIG. 8.

That is, the non-display light emitting device NED is not provided to output light to the outside of the light emitting display panel 100, but to increase the temperature of the gate driver 200. Therefore, a light blocking layer LSL which blocks light may be provided between the non-display light emitting device NED and the substrate 101 so that light generated from the non-display light emitting device NED is not output to the outside through the substrate 101.

The light blocking layer LSL may be formed of various materials capable of blocking light, and may be formed by stacking at least two color filters CF. For example, the light blocking layer LSL may consist of a red color filter CF_R, a green color filter CF_G, and a blue color filter CF_B, as illustrated in FIG. 8.

The red color filter CF_R, the green color filter CF_G, and the blue color filter CF_B may be provided in the pixels P to determine the color of the pixels P, as described above with reference to FIG. 7. That is, the light blocking layer LSL may be formed by stacking at least two color filters CFs when color filters CF are provided in the display area DA.

In this case, a planarization layer 106 may be further provided at an upper end of the light blocking layer LSL, and a non-display light emitting device NED may be provided on the planarization layer 106.

Finally, FIG. 9 is an example diagram illustrating a cross-sectional surface taken along line C-C′ illustrated in FIG. 6. That is, the cross-sectional surface illustrated in FIG. 9 is an example diagram illustrating a cross-sectional surface of the gate control signal line GCL and the non-display light emitting device NED provided in the line non-display area NDA_L.

The line non-display area NDA_L may be adjacent to the transistor non-display area NDA_T as illustrated in FIG. 6, and may share various layers configuring the display area DA and the transistor non-display area NDA_T.

For example, the line non-display area NDA_L, as illustrated in FIG. 9, may include a substrate 101, a main gate control signal line GCLa provided on the substrate 101, a buffer 102 provided on the main gate control signal line GCLa, an auxiliary gate control signal line GCLb provided on the buffer 102, a light blocking layer LSL provided on the auxiliary gate control signal line GCLb, a non-display anode NAN provided on the light blocking layer LSL and connected to the auxiliary gate control signal line GCLb, a non-display bank NBK covering the outer portion of the non-display anode NAN, a non-display light emitting layer NEL provided on the non-display bank NBK, a non-display cathode NCA provided on the non-display light emitting layer NEL, and an encapsulation layer 107 covering the non-display cathode NCA.

Here, the substrate 101, the buffer 102, and the encapsulation layer 107 may correspond to the substrate 101, the buffer 102, and the encapsulation layer 107 described above with reference to FIG. 7. That is, the buffer 102 and the encapsulation layer 107 may be provided on the whole substrate 101. Furthermore, the passivation layer 105 and the planarization layer 106 may be further provided at an upper end of the auxiliary gate control signal line GCLb illustrated in FIG. 9, and in this case, the non-display anode NAN may be connected to the auxiliary gate control signal line GCLb through contact holes provided in the passivation layer 105 and the planarization layer 106. Furthermore, a gate insulation layer 103 may be further provided between the main gate control signal line GCLa and the auxiliary gate control signal line GCLb, and in this case, the main gate control signal line GCLa and the auxiliary gate control signal line GCLb may be connected through contact holes provided in the buffer 102 and the gate insulation layer 103.

In this case, the main gate control signal line GCLa and the auxiliary gate control signal line GCLb illustrated in FIG. 9 may configure the gate control signal line GCL. The main gate control signal line GCLa may be formed with the light blocking plate LS, and the auxiliary gate control signal line GCLb may be formed with the gate Gate.

Moreover, the non-display anode NAN, the non-display light emitting layer NEL, and the non-display cathode NCA may configure a non-display light emitting device NED.

In this case, the auxiliary gate control signal line GCLb may be connected to the non-display light emitting device NED. That is, the gate control signal line GCL may be connected to the non-display light emitting device NED. Although FIG. 9 illustrates the gate control signal line GCL including the auxiliary gate control signal line GCLb and the main gate control signal line GCLa, the gate control signal line GCL may include only one of the auxiliary gate control signal line GCLb and the main gate control signal line GCLa.

Particularly, the non-display transistor NTFT may be provided to overlap the gate control signal line GCL. That is, the non-display light emitting device NED may be provided at an upper end or a lower end of the gate control signal line GCL in the cross-sectional surface of the light emitting display panel 100, and FIG. 9 illustrates a light emitting display panel 100 provided with a non-display light emitting device NED at an upper end of the gate control signal line GCL.

Therefore, the non-display light emitting device NED may output light by using current, voltage, and a clock supplied to the gate control signal line GCL.

When light is output from the non-display light emitting device NED, the temperature of the gate control signal line connected to the non-display light emitting device NED or overlapping the non-display light emitting device NED can increase rapidly. Accordingly, it may be quickly determined whether the gate control signal line GCL is normally driven at a high temperature.

Therefore, according to the present disclosure, it may be quickly determined whether the gate driver 200 is normally driven at a high temperature.

In this case, if the gate control signal line GCL is not normally driven, current, voltage, and a clock may not be normally supplied to the gate control signal line connected to the non-display light emitting device NED or overlapping the non-display emitting device NED, and thus light may not be output from the non-display light emitting device NED.

The non-display light emitting device NED in which light is not output may be identified through various cameras or magnifiers.

It may be determined that the gate control signal line connected to the non-display light emitting device NED which does not output light or overlapping the non-display light emitting device NED which does not output light does not operate normally.

That is, according to the present disclosure, among the gate control signal lines GCL included in the gate driver 200, a gate control signal line GCL which does not operate normally can be quickly and simply identified. Accordingly, whether the gate driver 200 is defective and a defective gate control signal line GCL may be quickly and accurately determined.

A light blocking layer LSL which blocks light may be provided at an upper end or a lower end of the non-display light emitting device NED. The light blocking layer LSL provided on the gate control signal line GCL may have the same structure and perform the same function as the light blocking layer LSL described above with reference to FIG. 8. Accordingly, a detailed description of the light blocking layer LSL illustrated in FIG. 9 is omitted.

FIG. 10 is an example diagram illustrating a region in which cathode voltage lines are provided in a light emitting display panel according to the present disclosure, FIG. 11 is an example diagram illustrating a cross-sectional surface taken along line D-D′ illustrated in FIG. 10, FIG. 12 is an example diagram illustrating a cross-sectional surface taken along line E-E′ illustrated in FIG. 10, and FIG. 13 is another example diagram illustrating a cross-sectional surface taken along line D-D′ illustrated in FIG. 10. That is, FIG. 10 is an example diagram illustrating a portion of a light emitting display panel, and particularly, a region provided with a first cathode voltage line 521, a second cathode voltage line 522, a non-display cathode NCA, and a cathode CA. FIG. 10 illustrates a power supply 500 connected to the first cathode voltage line 521 and the second cathode voltage line 522 for convenience of description. In the following descriptions, details which are the same as or similar to the details described above with reference to FIGS. 1 to 9 are omitted or will be briefly described.

First, the power supply 500 may include a cathode voltage generator 510 for supplying a cathode voltage to the cathode CA of the light emitting devices ED, as illustrated in FIGS. 1 and 10. The second voltage EVSS illustrated in FIG. 2 maybe a cathode voltage.

The light emitting devices ED may be commonly connected to the cathode CA provided in the display area DA, and the non-display light emitting devices NED may be commonly connected to the non-display cathode NCA provided in the non-display area NDA.

The non-display cathode NCA of the non-display light emitting device NED may be connected to the first cathode voltage line 521 extending from the cathode voltage generator 510, and the cathode CA of the light emitting devices DE may be connected to the second cathode voltage line 522 extending from the cathode voltage generator 510.

That is, the same cathode voltage may be supplied to the non-display cathode NCA of the non-display light emitting device NED and the cathode CA of the light emitting device DE. However, the light emitting display apparatus according to the present disclosure is not limited thereto. Accordingly, cathode voltages supplied to the non-display cathode NCA and the cathode CA may be different from each other. In this case, the cathode voltage generator 510 may further include a first generator for generating a non-display cathode voltage supplied to the non-display cathode NCA and a second generator for generating a cathode voltage supplied to the cathode CA.

Hereinafter, for convenience of description, the light emitting display apparatus in which a cathode voltage supplied to the non-display cathode NCA is the same as a cathode voltage supplied to the cathode CA will be described as an example of the present disclosure, and in this case, the cathode voltage is generated in the cathode voltage generator 510.

In the light emitting display apparatus according to the present disclosure, the non-display light emitting device NED may be used to determine whether the gate driver 200 is normally driven in the process of manufacturing the light emitting display apparatus.

That is, the non-display light emitting device NED outputs light for testing in the manufacturing process of the light emitting display apparatus, and when the light emitting display apparatus is used by the user after the light emitting display apparatus is manufactured, the non-display light emitting device NED does not output light.

To this end, as an example, the first cathode voltage line 521 may be connected to or separated from the cathode voltage generator 510 by a cathode voltage switch 520 connected to the first cathode voltage line 521, as illustrated in FIG. 10. Although it is illustrated that the cathode voltage switch 520 is included in the power supply 500, the embodiments are not limited thereto. As an example, the cathode voltage switch 520 may be disposed on the display panel.

For example, in the manufacturing process of the light emitting display apparatus, the control driver 400 may transmit a power control signal PCS which can turn on the cathode voltage switch 520 to the cathode voltage switch 520. Accordingly, the cathode voltage can be transmitted to the non-display cathode NCA through the cathode voltage switch 520 and the first cathode voltage line 521, and thus light can be output from the non-display light emitting devices NED.

However, when the light emitting display apparatus is used by the user after the manufacture of the light emitting display apparatus is completed, the control driver 400 may transmit a power control signal PCS which can turn off the cathode voltage switch 520 to the cathode voltage switch 520. Accordingly, the cathode voltage may not be transmitted to the non-display cathode NCA, and thus light is not output from the non-display light emitting devices NED. Although it is described that the cathode voltage switch 520 is controlled by the control driver 400, embodiments are not limited thereto. As an example, the cathode voltage switch 520 may be controlled by a component other than the control driver 400. As an example, the cathode voltage switch 520 may be removed or modified in configuration such that the first cathode voltage line 521 is disconnected from the power supply 500.

Next, the non-display cathode NCA may be connected to the first cathode voltage line 521 in the non-display area NDA, as illustrated in FIG. 10. FIG. 11 is a cross-sectional view of a portion where the non-display cathode NCA and the first cathode voltage line 521 are connected, and particularly, a cross-sectional view taken along the D-D′ line illustrated in FIG. 10.

That is, in a region where the non-display cathode NCA and the first cathode voltage line 521 are connected, the first cathode voltage line 521 may be provided on the substrate 101, the planarization layer 106 and the non-display bank NBK may be provided at an upper portion of the first cathode voltage line 521, and the non-display cathode NCA may be connected to the first cathode voltage line 521 through a contact hole provided in the planarization layer 106 and the non-display bank BK.

The first cathode voltage line 521 may include a first main cathode voltage line 521a and a first auxiliary cathode voltage line 521b, as illustrated in FIG. 11.

The first main cathode voltage line 521a may be formed with the light blocking plate LS, and the first auxiliary cathode voltage line 521b may be formed with the gate Gate.

However, the first cathode voltage line 521 may be formed of only one of the first main cathode voltage line 521a and the first auxiliary cathode voltage line 521b.

Finally, the non-display cathode NCA and the cathode CA may be apart from each other between the display area DA and the non-display area NDA, as illustrated in FIG. 10. That is, as described above, when the light emitting display apparatus is used by the user, the cathode voltage should be supplied to the cathode CA, but the cathode voltage should not be supplied to the non-display cathode NCA. Accordingly, the non-display cathode NCA and the cathode CA are separated.

In this case, the non-display cathode NCA may be connected to the first cathode voltage line 521 in the non-display area NDA, and the cathode CA may be connected to the second cathode voltage line 522 in the non-display area NDA. Embodiments are not limited thereto. As an example, the cathode CA may be connected to the second cathode voltage line 522 in the display area DA and/or the non-display area NDA.

The non-display cathode NCA and the cathode CA may be separated by various methods.

For example, the non-display cathode NCA and the cathode CA may be separated by an undercut structure UC provided between the non-display cathode NCA and the cathode CA as illustrated in FIG. 12, or may be separated on the same plane as illustrated in FIG. 13.

The undercut structure UC may be formed by various layers, but as illustrated in FIG. 12, the undercut structure UC may be formed by a passivation layer 105 and a planarization layer 106. That is, a buffer 102 may be provided on the substrate 101, the passivation layer 105 may be provided on the buffer 102, and the planarization layer 106 and the bank BK may be provided on the passivation layer 105. In this case, the undercut structure UC may be formed between the passivation layer 105 and the planarization layer 106 due to the difference in the degree to which the passivation layer 105 is etched and the planarization layer 106 is etched.

After the undercut structure UC is formed, when the cathode material forming the non-display cathode NCA and the cathode CA is deposited on the substrate 101, the cathode material may be cut off in the undercut structure UC.

When the undercut structure is thin, the cathode material may be connected, and thus, the undercut structure may be formed by etching two or more layers, for example, the buffer 102 and the passivation layer 105. In this case, the undercut structure UC may be formed thick, and thus the cathode material may be completely broken in the undercut structure UC.

Accordingly, the non-display cathode NCA and the cathode CA may be apart from each other with the undercut structure UC therebetween.

Moreover, after the buffer 102, the passivation layer 105, the planarization layer 106, and the bank BK are sequentially stacked on the substrate 101, the cathode material may be provided in the whole upper end of the bank BK.

Subsequently, the cathode material may be separated through the mask process, and as illustrated in FIG. 13, the non-display cathode NCA and the cathode CA may be apart from each other.

FIG. 14 is another example diagram illustrating a cross-sectional surface taken along line B-B′ illustrated in FIG. 6.

In the description referring to FIGS. 6 to 9, a light emitting display panel 100 using a bottom emission type was described as an example of a light emitting display panel applied to the present disclosure.

However, not only the light emitting display panel 100 using the bottom emission type but also a light emitting display panel 100 using a top emission type may be applied to the light emitting display apparatus according to the present disclosure.

That is, in the light emitting display panel 100 using the bottom emission type, light generated from the light emitting device ED may be output to the outside through the substrate 101, as illustrated in FIG. 7. In this case, light generated from the non-display light emitting device NED provided in the non-display area NDA may be also output to the outside through the substrate 101.

Therefore, as illustrated in FIGS. 8 and 9, the light blocking layer LSL for blocking light generated from the non-display light emitting device NED may be provided between the non-display light emitting device NED and the substrate 101.

However, light generated from the light emitting device ED provided in the display area of the light emitting display panel 100 using the top emission type may be output to the outside through the cathode CA and the encapsulation layer 107.

Therefore, light generated from the non-display light emitting device NED provided in the transistor non-display area NDA_T of the light emitting display panel 100 using the top emission type may also be output to the outside through the non-display cathode NCA and encapsulation layer 107, as illustrated in FIG. 14.

However, because the light generated from the non-display cathode NCA should not be output to the outside, a light blocking layer LSL may be provided at an upper end of the non-display cathode NCA and the encapsulation layer 107, as illustrated in FIG. 14.

As described above with reference to FIG. 8, the light blocking layer LSL may be formed of various materials capable of blocking light, for example, at least two color filters CF. In FIGS. 8 and 14, a light blocking layer LSL including a red color filter (F_R, a green color filter CF_G, and a blue color filter CF_B is illustrated.

That is, each of the cross-sectional views illustrated in FIGS. 14 and 8 illustrates a non-display transistor NTFT and a non-display light emitting device NED provided in the transistor non-display area NDA_T. Particularly, the cross-sectional view illustrated in FIG. 14 is a cross-sectional view of the light emitting display panel 100 using the top emission type, and the cross-sectional view illustrated in FIG. 8 is a cross-sectional view of the light emitting display panel 100 using the bottom emission type.

Therefore, the cross-sectional view illustrated in FIG. 14 has a structure similar to the cross-sectional view illustrated in FIG. 8, and the light blocking layer LSL is provided at an upper end of the non-display light emitting device NED in the cross-sectional view illustrated in FIG. 14. However, the light blocking layer LSL is provided at a lower end of the non-display light emitting device NED in the cross-sectional view illustrated in FIG. 8.

To provide an additional description, in the transistor non-display area NDA_T of the light emitting display panel 100 using a top emission type, as illustrated in FIG. 14, the buffer 102 may be provided on the substrate 101, the non-display active layer ACTa may be provided on the buffer 102, the gate insulation layer 103 may be provided on the non-display active layer ACTa, the gate layers 104 may be provided on the gate insulation layer 103, at least one of the passivation layer 105 and the planarization