To apply corresponding voltages to the word lines WL, the bit bines BL, and the source line SL of the memory cell array as described above, the ONOA current measuring circuit 110 may be configured as shown in FIG. 3. The ONOA current measuring circuit 110 may include a memory cell string selector 111, a bit line controller 113, a source line controller 115, a word line controller 117, and an ONOA current measurer 119.

The memory cell string selector 111 may be configured to drive the drain select transistor DST and the source select transistor SST of a memory cell string CS including a selected memory cell to select the memory cell string CS including the selected memory cell, as the selected memory cell string, among the plurality of memory cell strings in the memory cell array.

The bit line controller 113 may be configured to apply the zero (0) voltage to a bit line BL coupled to the selected memory cell string when the selected memory cell string is selected.

The source line controller 115 may be configured to apply the zero (0) voltage to the source line SL of the memory cell array when the selected memory cell string is selected.

FIG. 4 is a graph illustrating an ONOA current measuring voltage (positive (+) bias) applied to the selected word line SEL. WL through a word line controller in the flash memory material reliability measuring apparatus 100 through current measurement according to an embodiment.

Referring to FIG. 4, when the selected memory cell CS including the selected word line SEL. WL is selected through the memory cell string selector 111, the word line controller 117 may be configured to apply the ONOA current measuring voltage to the selected word line SEL. WL coupled to a gate of the selected memory cell MC among the memory cells arranged in series in the selected memory cell string (t0˜t1, t2˜t3) and apply the pass voltage Vpass to unselected word lines WL coupled to gates of unselected memory cells among the memory cells arranged in series in the selected memory cell string (t0˜t1, t2˜t3).

For example, when a corresponding memory cell string CS including the selected memory cell among the plurality of memory cell strings CS1 and CS2 is selected as the selected memory cell through the memory cell string selector 111, the bit line controller 113 and the source line controller 115 may apply the zero (0) voltage to a selected bit line BL and a selected source line SL coupled to the selected memory cell string CS, respectively (t0˜t4). The word line controller 117 may apply the ONOA current measuring voltage to the selected word line SEL. WL, and thus the ONOA current measuring voltage may be applied to the gate of the selected memory cell MC (t0˜t1, t2˜t3). Referring to FIG. 4, through the above-described processing, the word line controller 117 may control the pass voltage Vpass to be applied to the unselected word lines UNSEL. WL while the ONOA current measuring voltage is applied to the selected word line SEL. WL (t0˜t1, t2˜t3), and control the zero (0) voltage to be applied to the unselected word lines UNSEL. WL while the zero (0) voltage is applied to the selected word line SEL. WL (t1˜t2, t3˜t4). The word line controller 117 may apply the ONOA current measuring voltage to the selected word line SEL. WL through a plurality of sweep processes, each of which increases the ONOA current measuring voltage to a FN tunneling threshold voltage for one period (t0˜t1, t2˜t3) and then maintains the ONOA current measuring voltage to the zero (0) voltage for a fixed time (t1˜t2, t3˜t4). The word line controller 117 may apply the ONOA current measuring voltage to the selected word line SEL. WL through a plurality of sweep processes. In each of the plurality of sweep processes, the word line controller 117 may apply the ONOA current measuring voltage, which is increased to a FN tunneling threshold voltage for a fixed time (sweep period, t0˜t1, t2˜t3) during each sweep process (t0˜t2, t2˜t4) and then is maintained to the zero (0) voltage for a remaining time (maintenance period, t1˜t2, t3˜t4) during each sweep process (t0˜t2, t2˜t4), to the selected word line SEL. WL.

FIG. 5 is an energy band diagram of an ONOA path when an ONOA current measuring voltage (positive (+) bias) is applied to a word line WL in a flash memory material reliability measuring apparatus through current measurement according to an embodiment.

As shown in FIG. 5, when the ONOA current measuring voltage is applied to the gate of the selected memory cell MC, a potential barrier, which descends along with an ONOA path via a TOX layer, a floating gate FG, a CTN layer, a BOX layer, and an aluminum oxide (Al₂O₃) layer of the selected memory cell, may be formed from a Si channel of the selected memory cell toward a gate metal of the selected memory cell. Accordingly, the ONOA current may flow along the ONOA path between the Si channel and the gate metal by FN tunneling.

Characteristics of a dielectric layer such as an effective mass or a barrier height may be reflected in the ONOA current.

Referring back to FIG. 4, the word line controller 117 may be configured to apply the ONOA current measuring voltage to the selected word line SEL. WL coupled to the gate of the selected memory cell MC in each of the plurality of sweep processes. Each of the plurality of sweep processes may be divided into a sweep period which increases the ONOA current measuring voltage to the FN tunneling threshold voltage and a maintenance period which maintains the ONOA current measuring voltage to the zero (0) voltage.

In each of the plurality of sweep processes, the ONOA current measuring voltage may be increased to the FN tunneling threshold voltage for a fixed time (sweep period) and then maintained to the zero (0) voltage for a remaining time (maintenance period) after the sweep period. The ONOA current measuring circuit 110 may be configured to measure the ONOA current in the sweep period, in which the ONOA current measuring voltage is applied, in a second sweep process (2^ndSweep). One sweep process includes one sweep period and one maintenance period. The 1st sweep process includes one sweep period (t0˜t1) and one maintenance period (t1˜t2). The 2nd sweep process includes one sweep period (t2˜t3) performed after the maintenance period (t1˜t2) of the 1st sweep process and one maintenance period (t3˜t4).

The ONOA current measurer 119 may be configured to measure the ONOA current flowing in a path (for example, ONOA path) via the tunneling insulating layer of the selected memory cell to which the ONOA current measuring voltage is applied through the word line controller 117. The ONOA current measurer 119 may be configured to measure the ONOA current flowing through the ONOA path of the selected memory cell, to which the ONOA current measuring voltage is applied, in any one sweep process, other than a first sweep process (1^stSweep), among the plurality of the sweep processes. In an example, the ONOA current measurer 119 may be configured to measure the ONOA current flowing through the ONOA path when the ONOA current measuring voltage is applied to the selected word line SEL. WL through the word line controller 117 in the second sweep process among the plurality of sweep processes. In another example, the ONOA current measurer 119 may be configured to measure the ONOA current flowing through the ONOA path when the ONOA current measuring voltage is applied to the selected word line SEL. WL through the word line controller 117 in any one sweep process selected from remaining sweep processes, after the second sweep process, among the plurality of sweep processes.

The flash memory material reliability measuring apparatus 100 according to an embodiment may measure the ONOA current by applying the ONOA current measuring voltage (positive (+) bias) to the selected word line in a first sweep period of the first sweep process 1^stSweep through the word line controller 117, and measure the ONOA current by applying the ONOA current measuring voltage (positive (+) bias) to the selected word line in a second sweep period of the second sweep process 2^ndSweep through the word line controller 117, as shown in FIG. 4.

When the ONOA current measuring voltage is applied to the selected word line SEL. WL through the first sweep process 1^stSweep, the CTN layer, which is the charge trap site in the ONOA structure, or a floating gate FG may be filled with electrons or holes. Then, when the ONOA current measuring voltage is applied to the selected word line SEL. WL through the second sweep process 2^ndSweep, the current flowing through the ONOA path in the second sweep process may be reduced than the current flowing through the ONOA path in the first sweep process even when the same bias voltage as the bias voltage in the first sweep process is applied to the selected word line SEL. WL in the second sweep process.

Specifically, when the ONOA current measuring voltage, which is increased to the FN tunneling threshold voltage, is applied to the selected word line SEL. WL through the word line controller 117 in the first sweep period of the first sweep process 1^stSweep, the CTN layer, which is a trap site in the ONOA structure, may be filled with charges (electrons or holes). Therefore, the ONOA current measured through the ONOA current measurer 119 might not match the FN current. On the other hand, when the ONOA current measuring voltage, which is increased to the FN tunneling threshold voltage, is applied to the selected word line SEL. WL through the word line controller 117 in the second sweep period of the second sweep process 2^ndSweep, the CTN layer, which is a trap site in the ONOA structure, may have been filled with charges (electrons or holes), and thus ONOA current measured through the ONOA current measurer 119 may be reduced and may substantially match the FN current. The FN current may be calculated using the following General Equations 1 to 3.

ln
⁡
(

J
FN

E
ox
2

)

=

ln
⁡
(
A
)

-

B

E
ox

[

General
⁢

equation
⁢

1

]

A
=

q
3

8
⁢
π
⁢
h
⁢

Φ
B

⁢

m
ox
★

[

General
⁢

equation
⁢

2

]

B
=

8
⁢
π
⁢

2
⁢

m
ox
★

⁢

Φ
B
3

3
⁢
qh

[

General
⁢

equation
⁢

3

]

In General Equations 1 to 3, ‘J_FN’ may refer to a FN current density, ‘E_OX’ may refer to an electric field applied to a tunnel oxide (TOX) layer, ‘m*_ox’ may refer to an effective mass in a dielectric, ‘Φ_B’ may refer to a barrier height, that is a work function, ‘H’ may refer to a Flank constant, and ‘q’ may refer to charge quantity.

Accordingly, it can be seen that when the ONOA current is measured by applying the ONOA current measuring voltage to the selected word line SEL. WL through the second sweep process 2^ndSweep and the FN current is calculated through General Equations 1 to 3, the actually measured ONOA current matches the FN current. Therefore, the flash memory material reliability measuring apparatus 100 according to an embodiment may measure the ONOA current in the second sweep process after the first sweep process is performed and then apply the measured ONOA current to generate the reliability indicator for a material of the flash memory.

Further, the flash memory material reliability measuring apparatus 100 according to an embodiment may measure the ONOA currents and the FN current through first to fourth sweep processes in which the ONOA current measuring voltage (positive (+) bias) is applied to the selected word line SEL. WL through the word line controller 117.

Specifically, when the ONOA current measuring voltage is first applied to the selected word line SEL. WL through the first sweep process 1^stSweep, the CTN layer, which is a charge trap site in the ONOA structure, may be filled with charges. Accordingly, it may be illustrated that all the ONOA currents measured in the second sweep process 2^ndSweep to the last sweep process (for example, fourth sweep process) may be almost the same as each other. At this time, the ONOA currents measured in the second sweep process 2^ndSweep to the last sweep process (for example, fourth sweep process) may substantially match the FN current.

Therefore, according to an embodiment, the ONOA currents, which are measured by applying the ONOA current measuring voltage to the selected word line SEL. WL from the second sweep process to the last sweep process after the ONOA current measuring voltage is applied to the selected word line SEL. WL in the first sweep, may be applied to generate the flash memory material reliability indicator. Specifically, the ONOA current may be measured by applying the ONOA current measuring voltage to the selected memory cell in any one sweep process, other than the first sweep process, among the plurality of sweep processes and the measured ONOA current may be applied to generate the flash memory material reliability indicator. In an example, the ONOA current may be measured in the second sweep process among the plurality of sweep processes and the measured ONOA current may be applied to generate the flash memory material reliability indicator, as described above. In another example, the ONOA current may be measured in any one sweep process selected from remaining sweep processes, after the second sweep process, among the plurality of sweep processes and the measured ONOA current may be applied to generate the flash memory material reliability indicator.

Referring back to FIG. 2, the reliability indicator generator 120 may be configured to generate the reliability indicator (i.e., reliability indicator signal) using the ONOA current measured in the ONOA current measuring circuit 110. The reliability indicator may include at least one of an endurance indicator, a retention indicator, a disturbance indicator, an interference indicator, and a tunnel oxide (TOX) nitrogen gradient indicator of the flash memory.

The endurance may refer to a maximum number of cycles to measure how many times the material of the flash memory can endure program and erase cycles.

The retention may refer to a time that the charges charged in the floating gate (in the CTN layer) can be retained. When a thickness of the TOX layer is thick, it is difficult to perform a program operation and it is easy to perform an erase operation compared to when the TOX layer is thin. When the thickness of the TOX layer is thin, it is difficult to perform an erase operation and it is easy to perform a program operation compared to when the TOX layer is thick. Accordingly, the retention may be used to calculate an item such as the thickness of the TOX layer. Specifically, values of the retention for each thickness of the TOX layer are calculated to generate standard information, and the thickness of the TOX layer can be calculated by comparing the unknown values of retention using the generated standard information.

The disturbance may refer to a phenomenon that charges (electrons or holes) are physically charged or discharged in an adjacent victim cell during programming, and thus a threshold voltage Vth of a memory cell is increased or reduced. That is, the charges may be charged or discharged into an adjacent floating gate, and thus the charge quantity of the adjacent floating gate may be physically changed.

The reason for the disturbance may be dielectric breakdown due to damage of a TOX layer, electrons trapped between a substrate and the TOX layer, charges such as electrons or holes trapped in the TOX layer, and the like.

The disturbance may include program disturbance in a word line direction, pass voltage disturbance in a bit line direction, pass voltage disturbance due to incremental step pulse program (ISPP), pass voltage disturbance due to increase in the number of memory cells of a memory cell string CS, read disturbance, disturbance due to a boosting method, and the like.

The program disturbance in the word line direction may occur due to accumulation of charges charged in the floating gates of the unselected memory cells in programming.

The pass voltage disturbance in the bit line direction may occur in all memory cells surrounding a floating gate to be programming in program driving.

The pass voltage disturbance due to the ISPP may occur due to a potential difference affecting the floating gate between a control gate of a pass transistor pass Tr and a substrate.

The pass voltage disturbance according to the increase in the number of memory cells of the memory cell string CS may occur due to increase in the threshold voltage Vth of the pass transistor pass Tr up to the level sufficient to affect the channel of the pass transistor pass Tr by repetitive application of the pass voltage according to increase in the number of memory cells coupled to the memory cell string CS in programming.

The read disturbance may occur due to charges unintentionally charged in an adjacent victim floating gate Victim VG in a data read process.

The disturbance due to the boosting method may occur due to charges such as electrons or holes charged in the adjacent floating gate FG charged by the voltage level applied to the substrate in boosting.

The interference may be a phenomenon in which the threshold voltage Vth of a target memory cell is shifted temporarily or for a fixed time as if the floating gate FG of the target memory cell is charged or discharged despite no substantial change in the number of charges in the floating gate FG. The reason of the interference may include parasitic capacitance generated between the target memory cell and surrounding memory cells, change in charge quantity of the surrounding floating gates, charges trapped around the floating gate FG, and the like.

The interference may include cell to cell interference (CCI), interference due to a program order, bit line to bit line interference (BBI), interference due to crack of the floating gate, vertical interference, horizontal interference, and the like.

The cell to cell interference (CCI) may occur due to increase of capacitance between floating gates FGs by reduction in a width between memory cells according to increase in density of memory cells.

The interference by the program order may occur due to a physical effect between bit lines according to the program order of sites three-dimensionally existing around one floating gate FG or between the floating gates FGs by the program order according to a program method.

The interference by the crack of the floating gate FG may refer to an effect on adjacent memory cells due to spreading of wave energy to the outside of the crack of the floating gate FG even though charges do not escape from the floating gate FG when the crack occurs in the floating gate FG.

The vertical interference may refer to change of the threshold voltages Vth in verification and read of a target memory cell by the memory cells in a cell string direction.

The horizontal interference may refer to change of the threshold voltages Vth in verification and read by the memory cells in a page direction.

The flash memory material reliability measuring apparatus 100 according to an embodiment may generate the reliability indicator for the flash memory material using the measured ONOA current.

Specifically, flash memory material reliability measuring apparatus 100 may derive the TOX electric field from the ONOA current and confirm reliability distribution according to the TOX electric field to generate an endurance reliability indicator (reliability indicator 1). In this way, the endurance according to the TOX electric field may be predicted by measuring the ONOA current and deriving the TOX electric field from the measured ONOA current. The TOX electric field may be a value calculated by an equation. The equation for calculating the TOX electric field may be ((ONOA BV) (Knee BV))/(ONOA BV)) in the second sweep process 2