103 is disposed on the adhesive layer 303 with its corresponding plurality of solder bumps 105 facing toward the carrier wafer 301 and with its corresponding substrate 104 facing away from the carrier wafer 301. In some embodiments, the adhesive layer 303 is configured to substantially surround the plurality of solder bumps 105 on each of the electro-optical chips 103, with the plurality of solder bumps 105 in contact with the top surface of the carrier wafer 301. In some embodiments, the adhesive layer 303 is configured to substantially surround the plurality of solder bumps 105 on each of the electro-optical chips 103, with the plurality of solder bumps 105 separated from the top surface of the carrier wafer 301 by a portion of the adhesive layer 303. It should be understood that the electro-optical chips 103 are disposed on the adhesive layer 303 across the carrier wafer 301 such that the bottom surfaces of the electro-optical chips 103 (the silicon substrate 104 surfaces of the electro-optical chips 103) are substantially coplanar with each other across the carrier wafer 301. Also, it should be appreciated that each electro-optical chip 103 is positioned on the carrier wafer 301 such that an open region is present next to the optical fiber attachment region 109 of the electro-optical chip 103, where the open region corresponds to an area in which the silicon baseplate 101 corresponding to the electro-optical chip 103 is to be formed to create the electro-optical chip assembly 100.

In some embodiments, such as shown in the example of FIG. 3B, the region above the adhesive layer 303 and between/around the electro-optical chips 103 is left vacant, e.g., filled by ambient atmosphere. However, in some embodiments, as an option, the region above the adhesive layer 303 and between/around the electro-optical chips 103 is filled with a mold compound material 305. FIG. 3C shows the vertical cross-section view through the carrier wafer 301 as shown in FIG. 3B, with the mold compound 305 disposed above the adhesive layer 303 and between/around the electro-optical chips 103, in accordance with some embodiments. In some embodiments, the mold compound 305 is a polymer material. In some embodiments, the mold compound 305 is disposed as a coating of a liquid polymer material, with the liquid polymer material thereafter being allowed to cure to form a solid polymer material. In some embodiments, the liquid polymer material is a liquid polymer composite material. For example, in some embodiments, the liquid polymer composite material includes an epoxy matrix with fill (particulate) material dispersed within the epoxy matrix. It should be understood that in various embodiments, the mold compound 305 can be essentially any type of mold compound material used in semiconductor chip manufacturing, so long as the mold compound 305 is thermally, chemically, and mechanically compatible with the silicon fusion bonding process used to fuse the silicon substrate 104 of the electro-optical chip 103 to a silicon base wafer 331.

In some embodiments, after the electro-optical chips 103 are secured to the carrier wafer 301, a planarization process is performed on the bottom surfaces of the electro-optical chips 103 (the silicon substrate 104 surfaces of the electro-optical chips 103) to ensure that the bottom surfaces of the electro-optical chips 103 are substantially coplanar with each other across the carrier wafer 301. In some embodiments, the planarization process is a chemical mechanical polishing (CMP) process. In some embodiments, the planarization process is a plasma etching process. It should be understood that in various embodiments, the planarization process can implement essentially any type of silicon wafer planarization technology. Once the bottom surfaces of the substrates 104 of the electro-optical chips 103 are sufficiently coplanar with each other across the carrier wafer 301, the carrier wafer 301 with the electro-optical chips 103 attached thereto is positioned over the silicon base wafer 331, such that the bottom surface of the silicon substrate 104 of each of the electro-optical chips 103 is in physical contact with the silicon base wafer 331.

FIG. 3D shows a vertical cross-section view through the carrier wafer 301 and the electro-optical chips 103 attached thereto, with the bottom surfaces of the silicon substrates 104 of the electro-optical chips 103 in physical contact with the silicon base wafer 331, in accordance with some embodiments. In some embodiments, the silicon base wafer 331 has a circumferential size and shape that is substantially the same as the carrier wafer 301. Also, FIG. 3D shows an example embodiment in which the mold compound 305 is present between/around the electro-optical chips 103. However, it should be understood that in some embodiments, the mold compound 305 is not present between/around the electro-optical chips 103, such that the region between/around the electro-optical chips 103 is vacant, e.g., filled by ambient atmosphere.

With the silicon substrates 104 of the electro-optical chips 103 in physical contact with the silicon base wafer 331, such as shown in FIG. 3D, a fusion bonding process is performed to fuse the silicon substrates 104 of the electro-optical chips 103 with the silicon base wafer 331. FIG. 3E shows a vertical cross-section view through the silicon base wafer 331 with the silicon substrates 104 of the electro-optical chips 103 fusion bonded to the silicon base wafer 331, and with the carrier wafer 301 and adhesive layer 303 released from the electro-optical chips 103, in accordance with some embodiments. FIG. 3F shows a top view of the silicon base wafer 331 with the silicon substrates 104 of the electro-optical chips 103 fusion bonded to the silicon base wafer 331, in accordance with some embodiments. In various embodiments, the fusion bonding process is performed to form a Si—Si bond at the interface between the silicon substrate 104 of the electro-optical chip 103 and the silicon base wafer 331. In some embodiments, the silicon substrate 104 of the electro-optical chip 103 and the silicon base wafer 331 are sufficiently flat, clean, and polished that the Si—Si bond forms spontaneously upon contact of the silicon substrate 104 of the electro-optical chip 103 with the silicon base wafer 331. In some embodiments, high temperature and high pressure is applied to form the Si—Si bond between the silicon substrate 104 of the electro-optical chip 103 and the silicon base wafer 331. In some embodiments, a high temperature, e.g., >700° C., annealing process is performed to remove water and/or hydrogen gas from the interface region between the silicon substrate 104 of the electro-optical chip 103 and the silicon base wafer 331 in order to strengthen the Si—Si bond. It should be understood that, in various embodiments, essentially any fusion bonding (or direct bonding) process used in the semiconductor fabrication industry for forming Si—Si bonds can be implemented to fusion bond the silicon substrates 104 of the electro-optical chips 103 to the silicon base wafer 331.

As shown in FIG. 3F, a plurality of scribe lines 333 is defined across the silicon base wafer 331, such that a plurality of silicon baseplates 101 for the respective plurality of electro-optical chips 103 is delineated by the plurality of scribe lines 333, where each of the plurality of silicon baseplates 101 corresponds to a different portion of the silicon base wafer 331. In some embodiments, the plurality of scribe lines 333 are defined such that each of the plurality of silicon baseplates 101 has a substantially same shape and a substantially same size. In some embodiments, the plurality of scribe lines 333 are defined such that each of the plurality of silicon baseplates 101 has a substantially rectangular shape that extends outward away from the optical fiber attachment region 109 of its corresponding electro-optical chip 103 by a distance 334 that provides for subsequent attachment of the plurality of optical fibers 107 to the silicon baseplate 101 by way of the adhesive 113.

FIG. 3G shows the electro-optical chips 103 and their corresponding silicon baseplates 101 singulated from the silicon base wafer 331, in accordance with some embodiments. An outline 335 of the silicon base wafer 331 is shown for reference. In various embodiments, the silicon base wafer 331 is cut or divided in some manner along the plurality of scribe lines 333, such as shown in FIG. 3F, to obtain the electro-optical chips 103 and their corresponding silicon baseplates 101. Again, it should be understood that each electro-optical chip 103 is fusion bonded to its corresponding silicon baseplate 101. It should also be understood that each electro-optical chip 103 is manufactured on a semiconductor wafer that is separate from the silicon base wafer 331 from which the silicon baseplates 101 are formed. FIG. 2A shows the side view of the electro-optical chip 103 fusion bonded to its silicon baseplate 101 after singulation from the silicon base wafer 331, which is referenced as View A-A in FIG. 3G.

After the electro-optical chip 103 and its corresponding silicon baseplate 101 is singulated from the silicon base wafer 331, the plurality of optical fibers 107 is attached to the electro-optical chip 103. FIG. 3H shows a top view of the plurality of optical fibers 107 attached to the electro-optical chip 103, such as previously described with regard to FIG. 1C, in accordance with some embodiments. FIG. 3I shows a side view of the plurality of optical fibers 107 attached to the electro-optical chip 103, referenced as View A-A in FIG. 3H, in accordance with some embodiments. FIG. 3J shows a vertical cross-section view of the plurality of optical fibers 107 attached to the electro-optical chip 103, looking toward the electro-optical chip 103, referenced as View B-B in FIG. 3H, in accordance with some embodiments. FIG. 1D shows the vertical cross-section view of the plurality of optical fibers 107 attached to the electro-optical chip 103, looking toward the support block 115, which is referenced as View C-C in FIG. 3H.

It should be understood that with the plurality of optical fibers 107 attached to the electro-optical chip 103 in the electro-optical chip assembly 100, the electro-optical chip 103 is configured for photonic and electronic testing before the electro-optical chip 103 is solder bonded to an electronic package, e.g., multi-chip package (MCP) and/or to another computer chip and/or to another electronic component. FIG. 4 shows the electro-optical chip assembly 100 connected both photonically and electrically to a test system 401, in accordance with some embodiments. In some embodiments, the test system 401 includes a plurality of electrically conductive contact pads 403 that can be positioned in physical contact with the plurality of solder bumps 105 of the electro-optical chip 103. Also, the plurality of optical fibers 107 can be temporarily optically connected to corresponding optical input/output devices of the test system 403. The test system 403 is configured to use the plurality of optical fibers 107 and the plurality of solder bumps 105 to test the photonic and electronic performance of the electro-optical chip 103. In various embodiments, the test system 403 includes one or more computer systems that can be programmed and operated as needed to test the photonic and electronic performance of the electro-optical chip 103. It should be appreciated that the photonic and electronic testing of the electro-optical chip 103 can be performed with the electro-optical chip assembly 100 in the pre-solder-reflow state, which enables verification of proper functionality of the electro-optical chip 103 before physical bonding of the electro-optical chip 103 to another device. This serves to reduce the loss of MCPs and/or other electronic devices due to their physical connection with a later discovered inoperable electro-optical chip 103. Once the electro-optical chip 103 is tested and verified to function properly, the electro-optical chip 103 is bonded to another electronic package or computer chip or electronic component through a solder reflow process that bonds the plurality of solder bumps 105 to a corresponding plurality of conductive pads on the other electronic package or computer chip or electronic component. FIG. 5 shows an example of an MCP 500 in which the electro-optical chip 103 of the electro-optical chip assembly 100 is solder bonded to an electronic package 501, in accordance with some embodiments. More specifically, the plurality of solder bumps 105 of the electro-optical chip 103 is solder bonded to a corresponding plurality of electrically conductive pads 503 of the electronic package 501.

In some embodiments, the process for manufacturing the electro-optical chip assembly 100 is performed without disposal of the adhesive layer 303 on the carrier wafer 301. For example, FIG. 6A shows a top view of a carrier wafer 601 that includes a number of sockets 603, in accordance with some embodiments. FIG. 6B shows a vertical cross-section view through the carrier wafer 601, referenced as View A-A in FIG. 6A, in accordance with some embodiments. Each of the sockets 603 is formed as a recessed region that extends a prescribed depth 604 into the carrier wafer 601 from the top surface of the carrier wafer 601. In some embodiments, each of the sockets 603 is formed to have an outer peripheral shape that substantially matches an outer peripheral shape of the electro-optical chip 103. Also, in some embodiments, each of the sockets 603 is formed to have a horizontal cross-section size that substantially matches a horizontal cross-section size of the electro-optical chip 103, such that when the electro-optical chip 103 is disposed within the socket 603, the electro-optical chip 103 is held by friction force within the socket 603, without use of an adhesive material to hold the electro-optical chip 103 on the carrier wafer 601. However, in other embodiments, a temporary adhesive is used to secure each electro-optical chip 103 within its respective socket 603.

FIG. 6C shows a top view of the carrier wafer 601 with the electro-optical chips 103 respectively disposed within the sockets 603, in accordance with some embodiments. Each socket 603 is positioned on the carrier wafer 601 so that when the electro-optical chip 103 is disposed within the socket 603 an open region is present next to the optical fiber attachment region 109 of the electro-optical chip 103, where the open region corresponds to an area in which the silicon baseplate 101 corresponding to the electro-optical chip 103 is to be formed to create the electro-optical chip assembly 100.

FIG. 6D shows a vertical cross-section view through the carrier wafer 601 with the electro-optical chips 103 disposed within the sockets 603, referenced as View A-A in FIG. 6C, in accordance with some embodiments. In some embodiments, the electro-optical chips 103 are fully seated within the sockets 603, such that the plurality of solder bumps 105 of the electro-optical chips 103 contact the carrier wafer 601 at the bottom of the sockets 603.

In some embodiments, after the electro-optical chips 103 are secured within the sockets 603 of the carrier wafer 601, a planarization process is performed on the bottom surfaces of the silicon substrates 104 of the electro-optical chips 103 to ensure that bottom surfaces of the silicon substrates 104 of the electro-optical chips 103 are substantially coplanar with each other across the carrier wafer 601. In some embodiments, the planarization process includes one or more of a CMP process, a plasma etching process, and/or another type of planarization process used in semiconductor wafer manufacturing. Once the bottom surfaces of the silicon substrates 104 of the electro-optical chips 103 are sufficiently coplanar with each other across the carrier wafer 601, the carrier wafer 601 with the electro-optical chips 103 secured in their respective sockets 603 is positioned over the silicon base wafer 331, such that the bottom surfaces of the silicon substrates 104 of the electro-optical chips 103 are in physical contact with the silicon base wafer 331. FIG. 6E shows a vertical cross-section view through the carrier wafer 601 and the electro-optical chips 103 attached thereto, with the bottom surfaces of the silicon substrates 104 of the electro-optical chips 103 in physical contact with the silicon base wafer 331, in accordance with some embodiments. In some embodiments, the silicon base wafer 331 has a circumferential size and shape that is substantially the same as the carrier wafer 601.

With the silicon substrates of the electro-optical chips 103 in physical contact with the silicon base wafer 331, such as shown in FIG. 6E, the fusion bonding process is performed to fuse the silicon substrates of the electro-optical chips 103 with the silicon base wafer 331. FIG. 3E shows a vertical cross-section view through the silicon base wafer 331 with the electro-optical chips 103 fusion bonded to the silicon base wafer 331 and with the carrier wafer 601 released from the electro-optical chips 103, in accordance with some embodiments. From the configuration of FIG. 3E, the process for manufacturing the electro-optical chip assembly 100 proceeds with the singulation of the silicon base wafer 331, as previously discussed with regard to FIGS. 3F and 3G, and with the attachment of the plurality of optical fibers 107 to the electro-optical chip 103, as previously discussed with regard to FIGS. 3H, 3I, and 3J.

In some embodiments, the electro-optical chips 103 are fusion bonded to the silicon base wafer 331 before the plurality of solder bumps 105 are disposed on the electro-optical chips 103. FIG. 7A shows a top view of the carrier wafer 601 with electro-optical chips 103A disposed within the sockets 603, in accordance with some embodiments. The plurality of solder bumps 105 is not yet disposed on each of the electro-optical chips 103A in the configuration of FIG. 7A. The electro-optical chips 103A are oriented such that the surface of each electro-optical chip 103A on which the plurality of solder bumps 105 is to be disposed faces toward the carrier wafer 601.

FIG. 7B shows a vertical cross-section view through the carrier wafer 601 with the electro-optical chips 103A disposed within the sockets 603, referenced as View A-A in FIG. 7A, in accordance with some embodiments. Each of the sockets 603 is formed as a recessed region that extends a prescribed depth 606 into the carrier wafer 601 from the top surface of the carrier wafer 601. In some embodiments, the electro-optical chips 103A are fully seated within the sockets 603, such that the top surface of the electro-optical chips 103A on which the plurality of solder bumps 105 are to be disposed contact the carrier wafer 601 at the bottom of the sockets 603.

In some embodiments, after the electro-optical chips 103A are secured within the sockets 603 of the carrier wafer 601, a planarization process is performed on the bottom surfaces of the silicon substrates 104 of the electro-optical chips 103A to ensure that bottom surfaces of the silicon substrates 104 of the electro-optical chips 103A are substantially coplanar with each other across the carrier wafer 601. In some embodiments, the planarization process includes one or more of a CMP process, a plasma etching process, and/or another type of planarization process used in semiconductor wafer manufacturing. Once the bottom surfaces of the silicon substrates 104 of the electro-optical chips 103A are sufficiently coplanar with each other across the carrier wafer 601, the carrier wafer 601 with the electro-optical chips 103A secured in their respective sockets 603 is positioned over the silicon base wafer 331, such that the bottom surfaces of the silicon substrates 104 of the electro-optical chips 103A are in physical contact with the silicon base wafer 331. FIG. 7C shows a vertical cross-section view through the carrier wafer 601 and the electro-optical chips 103A attached thereto, with the bottom surfaces of the silicon substrates 104 of the electro-optical chips 103A in physical contact with the silicon base wafer 331, in accordance with some embodiments.