1140 may perform an error correction operation on data to be stored in the allocated memory dies.

FIG. 3 is a diagram illustrating a memory die in which defects occur according to an embodiment of the present disclosure.

Referring to FIG. 3, a memory die (Die K) may include defective memory cells that have failed in a voltage test and defective memory cells that have failed in a temperature test.

The memory die (Die K) may include a memory cell array including a plurality of memory cells.

In an embodiment, among memory cells included in the memory die (Die K), defective memory cells may be identified through a wafer test. Among the memory cells included in the memory die (Die K), the defective memory cells that have failed in the voltage test may be memory cells in which no defects have occurred due to a change in another condition (e.g., temperature). Similarly, among the memory cells included in the memory die (Die K), defective memory cells that have failed in the temperature test may be memory cells in which no defects have occurred due to a change in another condition (e.g., voltage).

In other words, the defective memory cells, having failed in the voltage test, may be operated as normal memory cells unless they are operating at the voltage level at which defects occurred. Other defective memory cells, having failed in the temperature test, may be operated as normal memory cells unless they are operating at the temperature level at which defects occurred.

Furthermore, among the memory cells included in the memory die (Die K), memory cells that have passed the voltage test and the temperature test may be operated as normal memory cells.

Therefore, even though defective memory cells are present among the memory cells included in the memory die (Die K), the memory controller 1130 illustrated in FIG. 2 may allocate the memory die (Die K) for use unless the memory die (Die K) is used in the specific environment or condition in which defects have occurred in the memory cells.

In an embodiment, the memory cells included in the memory die (Die K) may be identified as defective memory cells during an operating process. Even though the memory cells included in the memory die (Die K) are not identified as defective memory cells in the wafer test process, defects may occur during an operating process.

FIG. 4 is a diagram illustrating a defect information table according to an embodiment of the present disclosure.

Referring to FIG. 4, a defect information table 1121 may include defect information depending on different voltage environments.

The defect information table 1121 may include information about the level of the voltage at which the defect has occurred in the defective memory die. Although not illustrated in FIG. 4, the defect information table 1121 may also include information about the address of a defective memory die in which a defect has occurred during a process of performing a wafer test while changing the operating voltage; the address of a memory block in which the defect has occurred among a plurality of memory blocks included in the defective memory die; the address of a page in which the defect has occurred among a plurality of pages included in the defective memory die; and the address of memory cells in which the defect has occurred among a plurality of memory cells included in the defective memory die.

Among the pieces of defect information stored in the defect information table 1121, pieces of defect information depending on voltage may include information about whether defects have occurred in respective memory dies in low voltage, normal voltage, and high voltage environments. Low voltage, normal voltage, and high voltage may be relative levels for distinguishing the operating voltages based on a preset reference value.

In an embodiment, as a result of performing a cell test on memory cells in a low-voltage operating environment, memory dies in which defects have occurred may be a second memory die (Die 2) and an N-th memory die (Die N). As a result, for memory cells included in the second memory die (Die 2), the defect information table 1121 may include the address of the second memory die (Die 2) and the address ADDR2 of memory cells in which defects have occurred in the low-voltage operating environment. Similarly, for memory cells included in the N-th memory die (Die N), the defect information table 1121 may include the address of the N-th memory die (Die N) and the address ADDR4 of memory cells in which defects have occurred in the low-voltage operating environment among memory cells included in the N-th memory die (Die N).

In an embodiment, as a result of performing a cell test on memory cells in a normal-voltage operating environment, memory dies in which defects have occurred may be a second memory die (Die 2) and an N-th memory die (Die N). As a result, for memory cells included in the second memory die (Die 2), the defect information table 1121 may include the address of the second memory die (Die 2) and the address ADDR3 of memory cells in which defects have occurred in the normal-voltage operating environment. Similarly, for memory cells included in the N-th memory die (Die N), the defect information table 1121 may include the address of the N-th memory die (Die N) and the address ADDR5 of memory cells in which defects have occurred in the normal-voltage operating environment.

In an embodiment, as a result of performing a cell test on memory cells in a high-voltage operating environment, memory dies in which defects have occurred may be a first memory die (Die 1) and an N-th memory die (Die N). Consequently, for memory cells included in the first memory die (Die 1), the defect information table 1121 may include the address of the first memory die (Die 1) and the address ADDR1 of memory cells in which defects have occurred in the high-voltage operating environment. Similarly, for memory cells included in the N-th memory die (Die N), the defect information table 1121 may include the address of the N-th memory die (Die N) and the address ADDR6 of memory cells in which defects have occurred in the high-voltage operating environment.

Further, referring to FIG. 4, a third memory die (Die 3) and an N−1-th memory die (Die N−1) may be normal memory dies in which no defects have occurred even though the operating voltage changes.

FIG. 5 is a diagram illustrating a defect information table according to an embodiment of the present disclosure.

Referring to FIG. 5, a defect information table 1121 may include defect information depending on temperature.

The defect information table 1121 may include information about the level of the temperature at which the defect has occurred in the defective memory die. Although not illustrated in FIG. 5, the defect information table 1121 may include information about the address of a defective memory die in which a defect has occurred during a process of performing a wafer test while changing operating temperature; the address of a memory block in which the defect has occurred among a plurality of memory blocks included in the defective memory die; the address of a page in which the defect has occurred among a plurality of pages included in the defective memory die; and the address of memory cells in which the defect has occurred among a plurality of memory cells included in the defective memory die.

Among the pieces of defect information stored in the defect information table 1121, pieces of defect information depending on temperature may include information about whether defects have occurred in respective memory dies in low temperature, normal temperature, and high temperature environments. The low temperature, normal temperature, and high temperature may be relative levels for distinguishing the operating temperatures based on a preset reference value.

In an embodiment, as a result of performing a cell test on memory cells in a low-temperature operating environment, memory dies in which defects have occurred may be a third memory die (Die 3) and an N-th memory die (Die N). As a result, for memory cells included in the third memory die (Die 3), the defect information table 1121 may include the address of the third memory die (Die 3) and the address ADDR2′ of memory cells in which defects have occurred in the low-temperature operating environment. Similarly, for memory cells included in the N-th memory die (Die N), the defect information table 1121 may include the address of the N-th memory die (Die N) and the address ADDR5′ of memory cells in which defects have occurred in the low-temperature operating environment.

In an embodiment, as a result of performing a cell test on memory cells in the normal temperature operating environment, dies in which defects have occurred may be an N−1-th memory die (Die N−1) and the N-th memory die (Die N). Consequently, for memory cells included in the N−1-th memory die (Die N−1), the defect information table 1121 may include the address of the N−1-th memory die (Die N−1) and the address ADDR4′ of memory cells in which defects have occurred in a normal temperature operating environment. Similarly, for memory cells included in the N-th memory die (Die N), the defect information table 1121 may include the address of the N-th memory die (Die N) and the address ADDR6′ of memory cells in which defects have occurred in the normal-temperature operating environment.

In an embodiment, as a result of performing a cell test on memory cells in a high-temperature operating environment, memory dies in which defects have occurred may be a second memory die (Die 2), a third memory die (Die 3), and an N-th memory die (Die N). As a result, for memory cells included in the second memory die (Die 2), the defect information table 1121 may include the address of the second memory die (Die 2) and the address ADDR1′ of memory cells in which defects have occurred in the high-temperature operating environment. Similarly, for memory cells included in the third memory die (Die 3), the defect information table 1121 may include the address of the third memory die (Die 3) and the address ADDR3′ of memory cells in which defects have occurred in the high-temperature operating environment. Similarly, for memory cells included in the N-th memory die (Die N), the defect information table 1121 may include the address of the N-th memory die (Die N) and the address ADDR7′ of memory cells in which defects have occurred in the high-temperature operating environment.

Further, referring to FIG. 5, a first memory die (Die 1) may be a normal memory die in which no defects have occurred even though the operating temperature changes.

FIG. 6 is a diagram illustrating a defect information table according to an embodiment of the present disclosure.

Referring to FIG. 6, a defect information table 1121 may include process information indicating whether memory cells are in a fast-operating state or a slow-operating state depending on process parameters. Also, the defect information table 1121 may include process information about respective memory dies.

In an embodiment, a first memory die (Die 1) and an N-th memory die (Die N) may be manufactured on different wafers. Therefore, in respective operating environments, depending on the process parameters, the operating states of the first memory die (Die 1) and the N-th memory die (Die N) may be different from each other.

In an embodiment, the first memory die (Die 1) may be in a state in which memory cells are operating fast in low-voltage and low-temperature states. Further, the first memory die (Die 1) may be in a state in which memory cells are operating in a normal mode in low-voltage and normal-temperature states. Furthermore, the first memory die (Die 1) may be in a state in which memory cells are operating in the normal mode in low-voltage and high-temperature states.

In an embodiment, the first memory die (Die 1) may be in a state in which memory cells are operating fast in normal-voltage and low-temperature states. Further, the first memory die (Die 1) may be in a state in which memory cells are operating fast in normal-voltage and normal-temperature states. Furthermore, the first memory die (Die 1) may be in a state in which memory cells are operating in the normal mode in normal-voltage and high-temperature states.

In an embodiment, the first memory die (Die 1) may be in a state in which memory cells are operating slowly in high-voltage and low-temperature states. Further, the first memory die (Die 1) may be in a state in which memory cells are operating fast in high-voltage and normal-temperature states. Furthermore, the first memory die (Die 1) may be in a state in which memory cells are operating fast in high-voltage and high-temperature states.

In an embodiment, an N-th memory die (Die N) may be in a state in which memory cells are operating slowly in low-voltage and low-temperature states. Furthermore, the N-th memory die (Die N) may be in a state in which memory cells are operating fast in low-voltage and normal-temperature states. Furthermore, the N-th memory die (Die N) may be in a state in which memory cells are operating in the normal mode in low-voltage and high-temperature states.

In an embodiment, the N-th memory die (Die N) may be in a state in which memory cells are operating fast in normal-voltage and low-temperature states. Furthermore, the N-th memory die (Die N) may be in a state in which memory cells are operating fast in normal-voltage and normal-temperature states. Furthermore, the N-th memory die (Die N) may be in a state in which memory cells are operating fast in normal-voltage and high-temperature states.

In an embodiment, the N-th memory die (Die N) may be in a state in which memory cells are operating fast in high-voltage and low-temperature states. Further, the N-th memory die (Die N) may be in a state in which memory cells are operating fast in high-voltage and normal-temperature states. Furthermore, the N-th memory die (Die N) may be in a state in which memory cells are operating fast in high-voltage and high-temperature states.

A memory controller 1130 illustrated in FIG. 2 may allocate memory dies based only on the defect information related to voltage illustrated in FIG. 4. In an embodiment, the memory controller 1130 illustrated in FIG. 2 may allocate memory dies based only on the defect information related to temperature illustrated in FIG. 5. In an embodiment, the memory controller 1130 illustrated in FIG. 2 may allocate memory dies in consideration of all of the voltage, temperature, and process information illustrated in FIG. 6.

For example, assuming that memory dies are allocated in a normal voltage environment only based on defect information related to voltage, as illustrated in FIG. 4, no defects have occurred in the N−1-th memory die (Die N−1) in the normal voltage environment. Thus, the memory controller 1130 may allocate the N−1-th memory die (Die N−1). Further, when the memory controller 1130 allocates memory dies only based on the defect information related to voltage, the memory controller 1130 may allocate the N−1-th memory die (Die N−1) even though defects have occurred in the N−1-th memory die (Die N−1) in a normal temperature environment, as illustrated in FIG. 5.

For example, it is assumed that memory dies are allocated in a normal temperature environment only based on defect information related to temperature. As illustrated in FIG. 5, no defects have occurred in the second memory die (Die 2) in the normal temperature environment, and thus the memory controller 1130 may allocate the second memory die (Die 2). Because the memory controller 1130 allocates memory dies only based on defect information related to temperature, the memory controller 1130 may allocate the second memory die (Die 2) even though defects have occurred in the second memory die (Die 2) in the normal voltage environment, as illustrated in FIG. 4.

For example, it is assumed that memory dies are allocated in consideration of all of the defect information related to voltage, the defect information related to temperature, and the process information. The memory controller 1130 may first allocate a memory die in a fast operating state from among memory dies in which no defects have occurred in a memory condition at the time at which memory dies are allocated.

FIG. 7 is a diagram illustrating a process of dynamically allocating memory dies based on temperature according to an embodiment of the present disclosure.

A memory controller 1130 illustrated in FIG. 2 may allocate memory dies required for operation, from among a plurality of memory dies included in a volatile storage area 1200, based on defect information related to temperature.

Among 12 memory dies included in the volatile storage area 1200, first, second, sixth, and tenth memory dies (Die 1, 2, 6, and 10) may include memory cells in which defects have occurred in a high-temperature operating environment. Similarly, fifth and ninth memory dies (Die 5 and 9) may include memory cells in which defects have occurred in a normal-temperature operating environment. Similarly, eighth and twelfth memory dies (Die 8 and 12) may include memory cells in which defects have occurred in a low-temperature operating environment. In addition, third, fourth, seventh, and eleventh memory dies (Die 3, 4, 7, and 11) may be normal memory dies in which no defects have occurred.

A state detector 1110 illustrated in FIG. 2 may monitor a memory condition, and may provide the result of monitoring to the memory controller 1130. The memory controller 1130 may check memory dies in which defects have occurred based on memory conditions with reference to a defect information table 1121.

In an embodiment, a temperature detector 1112 included in the state detector 1110 may detect the temperature of the storage device, and may generate temperature information based on the detected temperature. For example, the temperature detector 1112 may detect the temperature of the storage device, and may generate temperature information including information indicating whether the detected temperature corresponds to a low-temperature environment, a normal-temperature environment, or a high-temperature environment.

The memory controller 1130 illustrated in FIG. 2 may check the memory dies in which defects have occurred in the memory condition based on the temperature information.

In an embodiment, when the memory condition corresponds to a high temperature operating environment, such as for example detected by the temperature detector 1112, the memory controller 1130 may allocate the memory dies (e.g., Die 3, 4, 5, 7, 8, 9, 11, and 12) other than the memory dies (e.g., Die 1, 2, 6, and 10) in which defects have occurred in the high-temperature operating environment.

In an embodiment, when the memory condition corresponds to a normal-temperature operating environment, the memory controller 1130 may allocate the memory dies (e.g., Die 1, 2, 3, 4, 6, 7, 8, 10, 11, and 12) other than the memory dies (e.g., Die 5 and 9) in which defects have occurred in the normal-temperature operating environment.

In an embodiment, when the memory condition corresponds to a low-temperature operating environment, the memory controller 1130 may allocate the memory dies (e.g., Die 1, 2, 3, 4, 5, 6, 7, 9, 10, and 11) other than the memory dies (e.g., Die 8 and 12) in which defects have occurred in the low-temperature operating environment.

FIG. 8 is a diagram illustrating a process of dynamically allocating memory dies based on voltage according to an embodiment of the present disclosure.

A memory controller 1130 illustrated in FIG. 2 may allocate memory dies required for operation from among a plurality of memory dies included in a volatile storage area 1200, based on defect information related to voltage.

Among 12 memory dies included in the volatile storage area 1200, second, seventh, ninth, and tenth memory dies (e.g., Die 2, 7, 9, and 10) may include memory cells in which defects have occurred in a high-voltage operating environment. Similarly, fourth and eighth memory dies (e.g., Die 4 and 8) may include memory cells in which defects have occurred in a normal-voltage operating environment. Similarly, fifth and twelfth memory dies (e.g., Die 5 and 12) may include memory cells in which defects have occurred in a low-voltage operating environment. The remaining memory dies, that is, first, third, sixth and eleventh memory dies (e.g., Die 1, 3, 6, and 11) may be normal memory dies in which no defects have occurred.

A state detector 1110 illustrated in FIG. 2 may monitor a memory condition, and may provide the result of monitoring to the memory controller 1130. The memory controller 1130 may check memory dies in which defects have occurred based on the memory condition with reference to a defect information table 1121.

In an embodiment, a voltage detector 1111 included in the state detector 1110 may detect an applied operating voltage, and may generate voltage information based on the detected voltage. For example, the voltage detector 1111 may detect the operating voltage applied to the memory dies, and may generate voltage information, including information indicating whether the detected voltage corresponds to a low-voltage environment, a normal-voltage environment, or a high-voltage environment.

The memory controller 1130 illustrated in FIG. 2 may check the memory dies in which defects have occurred in the memory condition, based on the voltage information.