FIG. 2 is a flow diagram of a process integration method for improving the leakage in MV devices according to the embodiments of the application;

FIGS. 3A-3J are the schematic diagrams of the cross-sectional structures obtained at the respective steps of the process integration method for improving leakage in MV devices according to the embodiments of the application; and

FIG. 4 is a simulated curve of a GIDL leakage current of an MV device formed when the thickness of the gate spacer of the medium voltage region is changed according to the process integration method for improving leakage in MV devices of the embodiments of the application.

DETAILED DESCRIPTION OF THE DISCLOSURE

Referring to FIG. 2, it is a flow diagram of a process integration method for improving leakage in MV devices of the embodiments of the application; and referring to FIG. 3A to FIG. 3J, they are the schematic diagrams of the cross-sectional structures obtained in the respective steps of the process integration method for improving leakage in MV devices according to the embodiments of the application. The process integration method for improving leakage in MV devices of the embodiments of the application includes the following steps:

step I., referring to FIG. 3A, providing a semiconductor substrate 203 to form a first gate structure of an MV device and a second gate structure of an LV device on the semiconductor substrate 203, wherein the first gate structure is located in an MV device formation region 201, the second gate structure is located in the LV device formation region 202, the MV device has a first operating voltage, the LV device has a second operating voltage, and the first operating voltage is greater than the second operating voltage. In FIG. 3A, the first gate structure is shown in a dashed box 204a and the second gate structure is shown in a dashed box 204b. In FIG. 3A, both the MV device formation region 201 and the LV device formation region 202 are shown, the MV device formation region 201 is located at the left of the dashed line AA and the LV device formation region 202 is located at the right of a dashed line AA.

In the LV device formation region 202, each of the LV devices is repeatedly arranged at a second pitch, and the integration level is improved by reducing the second pitch; and in FIG. 3A, two of the second gate structures are shown, and the second pitch is the sum of the width of the second gate structure and the spacing between the second gate structures. As can be seen, the integration level of the device can be improved by reducing the second pitch.

In the MV device formation region 201, each of the MV devices is repeatedly arranged at the first pitch, the first pitch being larger than the second pitch. In FIG. 3A, only one of the first gate structures is shown, other first gate structures are repeatedly arranged but they are not shown in the figure. The first pitch is the sum of the width of the first gate structure and the spacing between the first gate structures.

The MV device includes an input-output (IO) device, and the LV device includes a core device and an SRAM device.

The first gate structure includes a first gate dielectric layer 205a and a first gate conducting material layer 206a stacked in sequence.

The second gate structure includes a second gate dielectric layer 205b and a second gate conducting material layer 206b stacked in sequence.

Hard mask layers 207 are also formed at the tops of the first gate conducting material layer 206a and the second gate conducting material layer 206b.

The thickness of the first gate dielectric layer 205a is greater than that of the second gate dielectric layer 205b, and the first gate dielectric layer 205a also extends along the surface of the semiconductor substrate 203 in the MV device formation region 201 outside the first gate conducting material layer 206a.

In the embodiment of the application, the semiconductor substrate 203 includes a silicon substrate.

The material of the first gate dielectric layer 205a includes an oxide layer or a high dielectric constant layer.

The material of the second gate dielectric layer 205b includes an oxide layer or a high dielectric constant layer.

The material of the first gate conducting material layer 206a includes polycrystalline silicon.

The material of the second gate conducting material layer 206b includes polycrystalline silicon.

The method includes step II., referring to FIG. 3B, depositing a first spacer material layer 208 which on the top surfaces and sides of the first gate conducting material layer 206a and the second gate conducting material layer 206b, and the surface of the substrate outside the first gate conducting material layer 206a and the second gate conducting material layer 206b.

In the embodiments of the application, the material of the first spacer material layer 208 is carbon-doped silicon nitride. In other embodiments, the material of the first spacer material layer 208 is silicon nitride.

The method includes step III., referring to FIG. 3C, forming an additional spacer material layer 209a on the surface of the first spacer material layer 208, wherein the additional spacer material layer 209a is of a different material than the first spacer material layer 208.

In the embodiments of the application, the material of the additional spacer material layer 209a includes an oxide layer. In some preferred embodiments, the oxide layer used in the additional spacer material layer 209a is formed by deposition a TEOS layer with a CVD process. The TEOS CVD process indicates a chemical vapor deposition process in which TEOS is used as a silicon source. The oxide layer formed by the TEOS CVD process is also referred to as a TEOS oxide layer.

Compared with nitrogen-doped silicon nitride, the TEOS oxide layer has a very high etching selection ratio under hydrofluoric acid. The etch rate of TEOS oxide layer to etch rate of carbon-doped silicon nitride under hydrofluoric acid is higher than 30:1.

The method includes step IV, referring to FIG. 3D, forming a first mask layer (can be the photomask 301) to cover the MV device formation region 201 and open the LV device formation region 202.

In FIG. 3D, the graphical structure of the first mask layer is can be a photomask