182 such as copper and landing pads 186. Landing pads 186 can by metal-metal bonded with landing pads 117 and through vias 118 of the mid-layer interposer 112. The metal wiring layers 182 of the silicon interconnect 122 may form die-to-die wiring 192 for interconnection between multiple dies. The complete die-to-die routing path may pass through a portion of the set of through vias 118 extending through the mid-layer interposer, and be connected with die-to-die wiring 192. Wiring within the BEOL build up structures may be fabricated using suitable damascene processing for example. One or more of the components in the first package level 120 may include through vias 190 extending at least from a back side to the BEOL build-up structure thereof. In the illustrated embodiment, the SOC die and silicon interconnect 122 each include through vias, which can be used for power delivery, for example, to the overlying dies.

The mid-layer interposer 112 in accordance with embodiments can include a silicon bulk layer 111 and an interposer BEOL build-up structure 115 formed similarly as those described for the components in the first and second package levels, including one or more dielectric layers 116 and metal wiring layers 114. It is to be appreciated that while embodiments are described with regard a silicon bulk layer 111, this bulk layer may be formed of other non-silicon materials including glass, silicon carbide, other compound semiconductors, and may be active or passive. A topmost dielectric layer 116 may be an oxide layer and include metal traces and landing pads 117. A planarized surface 119 may extend across the topmost dielectric layer 116 and landing pads 117 to facilitate hybrid bonding. Similarly, a back-side oxide layer 101 with planarized surface may be formed on the underside of the silicon bulk layer 111 for dielectric-dielectric bonding with components in the first package level 120. A plurality of through silicon vias 118 can extend through the silicon bulk layer 111 (and back-side oxide layer 101) to the BEOL build-up structure. The mid-layer interposer 112 may additionally include a plurality of devices 113, including passive devices such as MIM capacitors (planar or 3D) or trench capacitors, magnetic elements (inductors, coupled inductors, etc.), or even active devices such as transistors. In an embodiment, the mid-layer interposer includes an array of trench capacitors. Alternative materials may also be used in place of the silicon bulk layer 111, such as glass or other non-silicon materials. Other embodiments may include landing pads including through vias incorporated within back-side oxide layer 101 that can be planarized, similar to incorporation of top landing pads 117 and planarization, to facilitate hybrid bonding with components in the first package level 120.

The components within the second package level 140 may be embedded/encapsulated within an encapsulation layer 148, such as an inorganic encapsulation/fill layer material (e.g. dielectric/oxide or silicon) or organic molding compound layer material (e.g. molding compound material). A silicon encapsulation layer material, or gap fill material, can be used where no vertical interconnections are to be made therethrough. Likewise, the components within the first package level 120 can be embedded/encapsulated within an encapsulation layer 130, such as an inorganic encapsulation layer material (e.g. oxide, oxynitride, silicon) or organic molding compound layer material. A plurality of through vias 132 (e.g. through dielectric vias) may extend completely through a thickness of the encapsulation layer 130, and laterally adjacent the components, to make electrical connection within the mid-layer interposer 112, such as with the through vias 118 (through silicon vias, through glass vias, etc.). A back-side redistribution layer (RDL) 125 may optionally be formed underneath the encapsulation layer 130. The back-side RDL 125 may include contact pads 197 formed on the through vias 132 and through vias 190. The back-side RDL 125 may include one or more dielectric layers 195 and metal routing layers 196, and landing pads 198 which can receive solder bumps 105. The metal routing layers 196 may be formed using thin film techniques, or alternatively with damascene processing.

Referring now to FIG. 4B a 3D system 110 is illustrated similar to that of FIG. 4A with two variations. Firstly, any of the first level components may be bonded back-side up to the mid-layer interposer 112 (such as with a back side oxide bonding layer on a back side of a silicon bulk layer 147 of the component). This configuration is illustrated with cache die 128. A second variation is the memory die stack 153, which shows a second level component formed of a die stack rather than a monolithic die. While a memory die stack 153 is illustrated it is understood this is exemplary and components with stacked dies are not limited to memory.

FIGS. 5A-5F are schematic cross-sectional side view illustrations for a die-first reconstitution sequence of forming a 3D system with mid-layer interposer and component with pre-formed through vias in accordance with an embodiment. Such a sequence may begin with mid-layer interposer 112 as shown in FIG. 5A. At this stage, the silicon bulk layer 111 may be a silicon wafer. As shown in FIG. 5A, through vias 118 (e.g. through silicon vias, etc.) may already be formed into the silicon bulk layer 111 for future reveal.

Referring to FIG. 5B one or more components can be hybrid bonded to the planarized surface of the BEOL build-up structure 115 of the mid-layer interposer 112 to form dielectric-dielectric and metal-metal bonds. In the particular embodiment illustrated the components are the high power dies 142, 144, though this is merely exemplary. The components can then be encapsulated with an encapsulation layer 148 (also referred to as gap fill) such as a molding compound material or inorganic material (e.g. oxide, silicon) as shown in FIG. 5C, followed by bonding of optional thermal/structure cap 200, such as another silicon wafer. For thicker dies a molding compound may be used. Encapsulation layer 148 may optionally cover the high power dies 142, 144. This may be followed by grinding operation as shown in FIG. 5D to remove a thickness of the silicon bulk layer 111 and reveal the through vias 118. A second hybrid bonding operation may then be performed to add the first package level components. Referring to FIG. 5E the silicon interconnect 122 is illustrated, though this is merely exemplary. As shown, the silicon interconnect 122 can be placed face down with landing pads 186 aligned with the through vias 118 (or thin intervening routing layer). This can be followed as shown in FIG. 5F by the formation of a second encapsulation layer 130 (or gap fill layer), and another grinding operation to reduce a thickness of the silicon bulk layer 147 of the silicon interconnect 122 and reveal the through vias 190. Through vias 132 may then be formed by etching and plating, for example. Through vias 132 can be through mold vias (TMVs) or through oxide vias (TOVs) depending upon material of the encapsulation layer 130. This may be followed by building of RDL 125 (FIGS. 4A-4B), solder bump 105 drop, and singulation of the reconstituted structure to form a plurality of 3D systems 110.

FIGS. 6A-6F are schematic cross-sectional side view illustrations for a component-first reconstitution sequence of forming a 3D system with mid-layer interposer and component with pre-formed through vias in accordance with an embodiment. The process flow of FIGS. 6A-6FG is similar to that of FIGS. 5A-5F with a difference being in hybrid bonding of the components in the first package level are hybrid bonded first. As shown in FIG. 6A the process flow begins with a mid-layer interposer 112. One or more components can be hybrid bonded to the planarized surface of the BEOL build-up structure 115 of the mid-layer interposer 112 as shown in FIG. 6B to form dielectric-dielectric and metal-metal bonds. In the particular embodiment illustrated, a silicon interconnect 122 is bonded, followed by formation of encapsulation layer 130 and through vias 132. This may be followed by an etching operation to reveal through vias 190, and formation of RDL 125 as shown in FIG. 6C. A second carrier substrate 210 may then be optionally bonded to the RDL 125 as shown in FIG. 6D. The mid-layer interposer 112 may be ground and etched to reveal through vias 118 and planarized for hybrid bonding. Referring to FIG. 6E one or more components can then be hybrid bonded to the mid-layer interposer 112. In the exemplary embodiment illustrated high power dies 142, 144 are bonded face down. A second encapsulation layer 148 may then be formed around the high power dies 142, 144 followed by optional attachment of a thermal/structure cap 200. Optionally, second encapsulation layer 148 can cover the high power dies 142, 144 rather than the thermal/structure cap 200. The second carrier substrate 210 may then be removed followed by solder bump 105 drop, and singulation of the reconstituted structure to form a plurality of 3D systems 110.

It is to be appreciated that while both reconstitution sequences FIGS. 5A-5F and FIGS. 6A-6F illustrate via first approaches where pre-formed through vias (e.g. through silicon vias, etc.) are formed in a silicon interconnect 122 that this may be provided for any of the components in the first package level 120.

Referring now to FIGS. 7A-7D schematic cross-sectional side view illustrations are provided for a component-first sequence of forming a 3D system with mid-layer interposer 112 and component through via-last formation in accordance with an embodiment. As shown in FIG. 7A the sequence can begin with bonding the front side of a silicon interconnect 122 or other first package level component to the back side of the mid-layer interposer 112, or specifically to the back-side oxide layer 101 formed on the silicon bulk layer 111. In this manner, bonding is made with dielectric-dielectric bonds, and no metal-metal bonds. Notably, the front side of silicon interconnect 122 can optionally not include landing pads 186 previously illustrated in such a via-last process sequence. This can be followed by formation of encapsulation layer around the silicon interconnect 122 and any other components as shown in FIG. 7B. A planarization or etching operation may then be optionally performed to expose landing pads 186. The reconstituted stack-up can then be flipped, followed by hybrid bonding of multiple components onto the BEOL build-up structure 115 of the mid-layer interposer 112. In the exemplary embodiment illustrated in FIG. 7C high power dies 142, 144 are bonded face down. A second encapsulation layer 148 may then be formed around the high power dies 142, 144 followed by optional attachment of a thermal/structure cap 200 as previously described. Referring now to FIG. 7D the reconstituted stack-up is flipped again and through vias 220B are formed completely through the silicon interconnect 122 and into the BEOL build-up structure 115. Through vias 220A are also formed through the encapsulation layer 130 and into the BEOL build-up structure 115. Thus, the through vias 220A are also through silicon vias where they extend through the silicon bulk layer 111. This may be followed by building of RDL 125, solder bump 105 drop, and singulation of the reconstituted structure to form a plurality of 3D systems 110 as previously described.

Still referring to FIG. 7D, through vias 220C can also extend all the way through the mid-layer interposer 112 to contact the landing pads 186 of either or both high power dies 142, 144. In this manner the through vias 220C are bonded to the landing pads 186 with metal-metal bonds. Additionally, through vias 220D can be formed that stop within the silicon interconnect 122. This may be followed by formation of RDL 125.

FIGS. 8A-8E are schematic cross-sectional side view illustrations for a die-first sequence of forming a 3D system with mid-layer interposer 112 and component through via-last formation in accordance with an embodiment. The process flow of FIGS. 8A-8E is similar to that of FIGS. 7A-7D with a difference being in hybrid bonding of the components in the second package level are hybrid bonded first. As shown in FIG. 8A the process flow begins with a mid-layer interposer 112. One or more components can be hybrid bonded to the planarized surface of the BEOL build-up structure 115 of the mid-layer interposer 112 as shown in FIG. 8B to form dielectric-dielectric and metal-metal bonds. In the particular embodiment illustrated, high power dies 142, 144 are hybrid bonded, followed by formation of encapsulation layer 148. A thermal/structure cap 200 can then optionally be attached as previously described. The reconstituted structure can then be flipped, followed by bonding the front side of a silicon interconnect 122 or other first package level component to the back side of the mid-layer interposer 112, or specifically to the back-side oxide layer 101 formed on the silicon bulk layer 111 as shown in FIG. 8C. In this manner, bonding is made with dielectric-dielectric bonds, and no metal-metal bonds. This can be followed by formation of encapsulation layer 130 around the silicon interconnect 122 and any other components as shown in FIG. 8D. Referring now to 8E, similar to the description of FIG. 7D, through vias 220B are now formed completely through the silicon interconnect 122 and into the BEOL build-up structure 115. Through vias 220A are also formed through the encapsulation layer 130 and into the BEOL build-up structure 115. Thus, the through vias 220A are also through silicon vias where they extend through the silicon bulk layer 111. Additionally, through vias 220D can be formed that stop within the silicon interconnect 122. This may be followed by building of RDL 125, solder bump 105 drop, and singulation of the reconstituted structure to form a plurality of 3D systems 110 as previously described.

The mid-layer interposers 112 in accordance with embodiments can include electrical routing, as well as passive device and/or active devices. In some embodiments the mid-layer interposers 112 can include banks of passive devices such as trench capacitors or MIM capacitors. However, it may not be suitable to connect all capacitors and capacitor banks for all applications, or in the case of defective devices. In accordance with embodiments, the mid-layer interposers can include customized routing and connectivity to the devices.

FIGS. 9A-9B are schematic cross-sectional side view illustrations of a sequence for testing and connecting a bank of deep trench capacitors within a mid-layer interposer in accordance with an embodiment. As shown in FIG. 9A the BEOL build-up structure 115 is partially fabricated including devices 113 (deep trench capacitors) as well as dielectric layers 116 and metal wiring layers 114. At this stage the devices can be tested in-line. Good devices 113 can be electrically connected with vias 199, while vias 199 may optionally not be formed to connect defective devices 113X (including passive devices such as MIM capacitors (planar or 3D) or trench capacitors, magnetic elements, or even active devices such as transistors) as shown in FIG. 9B. Thus, the mid-layer interposer may include a dielectric layer 116 within the BEOL build-up structure 115 where vias 199 are connected to only some of the devices 113. As such, the defective devices 113X may be left as floating, or electrically isolated.

As similar embodiment is shown in FIG. 10, where the devices 113 are MIM capacitors include a lower terminal 242 (plate), upper terminal 244 (plate) and high dielectric constant dielectric material 246 therebetween. The lower terminal 242 and upper terminal 244 may be formed of the metal wiring layers 114. The dielectric material 246 may have a higher dielectric constant than the dielectric layers 116 forming the BEOL build-up structure 115.

Still referring to FIG. 10, a via 199 is optionally connected to one of the terminals for a defective device 113X. This may also be the case with the trench capacitors of FIG. 9B. For example, this may be a low power (Vss) connection. However, high power Vdd may not be connected to the defective device 113X with a via 199.

The programmable writing may be used to connect appropriate vias 199 or provide open wiring. While FIGS. 9A-9B and FIG. 10 are shown at the device scale, the programmable writing may be used to connect, or alternatively mask, entire banks of devices. FIG. 11A is a schematic top view illustration of a via 199 connections to devices 113 within a mid-layer interposer in accordance with an embodiment. As shown individual devices 113 can be arranged into groups of banks 240. Where a defective device 113X is determined, an entire masked bank 240X can be designated. For example, where a single defective device 113X is measured then the via 199 connections can be skipped for an entire associated masked bank 240X. Alternatively, measurements may not be so precise, and instead testing is performed at the bank level, and as such a defective bank may be measured which indicates one or more defective device 113X in the masked bank 240X. In an embodiment, the mid-layer interposer 112 may include a plurality of banks 240, including one or more masked banks 240X including an array of capacitors that are either not electrically connected, or incompletely connected, such as with only Vss via 199 connections.

FIG. 11B is a schematic top view illustration of landing pad connections to capacitor banks in accordance with an embodiment. Thus, FIG. 11B illustrates the mid-layer interposer 112 further along in the fabrication sequence. As shown, landing pads 117 may still be formed for each bank 240 and masked bank 240X. This can facilitate further metal-metal bonding. For example, the two illustrated landing pads 117 can be for low power (Vss) and high power (Vdd) connection. Masked banks may include one or more dummy landing pads 117D that are not connected to the capacitors. For example, the dummy landing pads can be for both Vss and Vdd connections, or just for the Vdd connection in the exemplary embodiments. Embodiments are not limited to two landing pads 117, and this is merely exemplary. In accordance with embodiments the dummy landing pads 117D for a masked bank 240X may overlay an array of capacitors that are not electrically connected or incompletely connected to the corresponding landing pads 117 of the masked bank.

Up until this point embodiments have been described specifically with regard to a mid-layer interposer that can facilitate WoW or CoW bonding techniques, provide additional routing area, etc. More specifically the mid-layer interposer has been described as including a bulk layer 111 such as silicon bulk layer 111 or alternative material. For example, the bulk layer 111 could be a rigid layer such as silicon, glass or other non-silicon materials. In particular, the bulk layer 111 may be compatible with fabrication plant substrate sizes, such as 300 mm wafers, 200 mm wafers, etc. In other embodiments, the mid-layer interposer can be an intermediate dielectric layer deposited during the reconstitution sequence. The intermediate dielectric layer may include a managed surface for hybrid bonding and electrical connections in an embodiment. In an embodiment, stitched vias (TVs) may be formed through the intermediate dielectric layer for electrical connections in a via-last approach.

FIGS. 12A-12C are schematic cross-sectional side view illustrations for a reconstitution sequence of forming a 3D system with an intermediate dielectric layer and managed surface for hybrid bonding in accordance with an embodiment. Referring to FIG. 12A a stage of the process sequence is illustrated in which high power dies 142, 144 are placed face up on a carrier substrate 202 and encapsulated in an encapsulation layer 148. It is to be appreciated that high power dies 142, 144 are exemplary and any die set can be used. An intermediate dielectric layer 230, such as an oxide, oxynitride, polymer or even silicon, is then formed over the encapsulation layer and high power dies 142, 144. Referring to FIG. 12B a plurality of through dielectric vias 232 (e.g. copper) are formed completely through the intermediate dielectric layer 230 to connect directly to landing pads 186 with metal-metal bonds. The intermediate dielectric layer 230 can then be planarized to form a planar managed surface of the dielectric layer 230 material and metal bond pads 234. In this manner, the managed surface 236 can be prepared for hybrid bonding. A silicon interconnect 122, for example, can then be hybrid bonded to the managed surface 236 using CoW hybrid bonding for example with dielectric-dielectric bonds any metal-metal bonds between the landing pads 186 and metal bond pads 234. In the particular embodiment illustrated in FIG. 12C dummy landing pads 186D and dummy metal bond pads 234D may be formed to facilitate metal-metal bond area. It is to be appreciated that silicon interconnect 122 is exemplary and any die or component can be used.

While not separately illustrated, the reconstituted structure can then be further processed similarly as other embodiments including formation of another encapsulation layer around the silicon interconnect 122, formation of through vias, various RDL layers, thermal/structure cap, solder bumps, etc. and singulated into 3D systems 110.

FIGS. 13A-13C are schematic cross-sectional side view illustrations for a reconstitution sequence of forming a 3D system with an intermediate dielectric layer and via stitching in accordance with an embodiment. Referring to FIG. 13A the process sequence begins similarly as FIG. 12A. The surface of the intermediate dielectric layer 230 can then be planarized to form managed surface 236. A die or other component, illustrated as exemplary silicon interconnect 122, can then be bonded to the intermediate dielectric layer 230 as shown in FIG. 12B. For example, this may be achieved with surface activation and dielectric-dielectric bonds between the dielectric layer 184 and intermediate dielectric layer 230. A plurality of through vias 220C can then be formed through the silicon interconnect to the landing pads 186 to form metal-metal bonds. This is similar to the via-last approach described and illustrated in FIG. 7D.

In an embodiment, a 3D system includes a mid-layer interposer, a first package level on a first side of the mid-layer interposer, the first package level including a component (e.g. silicon interconnect 122) bonded to the mid-layer interposer with dielectric-dielectric bonds, and a second package level on a second side of the mid-layer interposer, the second package level including a first die (e.g. high power die 142, 144) bonded to the mid-layer interposer with dielectric-dielectric bonds. A plurality of through vias can extend completely through the component and at least partially through the mid-layer interposer. For example, in the embodiment illustrated in FIG. 7D the through vias 220B formed completely through the silicon interconnect 122 and into the BEOL build-up structure 115. In the embodiments illustrated in FIG. 7D and FIG. 13C through vias 220C extend all the way through the mid-layer interposer 112 to contact the landing pads 186 of either or both high power dies 142, 144. In the embodiment illustrated in FGI. 13C the mid-layer interposer is an intermediate dielectric layer 230.

Up until this point various 3D systems and assembly techniques have been described in which CoW and WoW hybrid bonding techniques can be used to achieve fine bump pitch in multiple package levels. The various 3D systems and assembly techniques are also compatible with electromagnetic field communication structures such as capacitive, magnetic, or photonic coupling to communicate across dielectric layers, or even thin metal layers. Photonic coupling may include photonic waveguides or photonic wires, for example, as well as electrical-to-optical (EO) converters and optical-to-electrical (OE) converters. Such electromagnetic field communication structures can also be integrated with fusion bonding and thermal compression bonding in addition to hybrid bonding. An EO converter may include conversion electronics and any suitable optical transmitter such as laser, light emitting diode, or other light source, modulator, etc. An OE converter may include an optical receiver such as a photodetector (avalanche photodiode, p-i-n photodiode, etc.) and conversion electronics. One or more optical repeater structures may additionally be included in the optical paths to receive, amplify, and then re-transmit the optical signals. One example is an optical amplifier (e.g. semiconductor optical amplifier). Other repeaters may be electrical/optical that can be integrated into active silicon connected to the optical paths with a variety of features such as logic, flops, cache, memory compressors and decompressors, controllers, local processing elements, etc. The OE/EO converters can also include optical mutliplexers, demultiplexers.

The dies described herein may additionally include an assembly of different components, can be heterogenous, and be hierarchically arranged. For example, a die may include a separately formed layer(s) of an optical converter, or multiple attached components.

The optical paths produced by the waveguides or photonic wires may be rigid or flexible. In an exemplary embodiment, waveguides are formed of a suitable material, such as oxide or nitride, that is readily integrated into semiconductor device fabrication and packaging. For example, the waveguides may be integrated into the BEOL build-up structure 115 of a mid-layer interposer 112. Vertical photonic communication, such as across CoW or WoW bonded surfaces, can be further negotiated using optical vias, grating couplers, mirrors, prisms, or additional waveguides or photonic wire bonds.

Referring now to FIGS. 14-19 schematic cross-sectional side view illustrations are provided of exemplary 3D systems within optical interconnects in accordance with embodiments. The 3D system structures may correspond to the 3D system structures previously described herein, and as such, the illustrational detail is focused on the optical interconnect structures rather than common shared features previously described herein.

The particular embodiment illustrated in FIG. 14 may be similar to those illustrated and described with regard to FIGS. 4A-4B for example, including a first package level 120 with one or more first-level dies 212 (e.g. any of silicon interconnect 122, moderate power die 124, LSIO die 126, cache die 128 or combination thereof) and a second package level 140 with one or more second-level dies 222 (e.g. any of high power die 142