114. Thus, the voltage at the control terminal 108c of transistor 108 is HIGH. In response, transistor 108 is ON so the first voltage input 102 is coupled to the voltage output 106. Thus, the voltage at the voltage output 106 is HIGH. Further, the second control signal 204 is LOW. Thus, the first protection circuitry 120 is OFF. Furthermore, because the voltage at the voltage output 106 is non-negative, the second protection circuitry 130 is OFF.

During normal OFF mode (e.g., when the power supply (not shown) is coupled to the circuit 100, transistor 108 is to be OFF, and there are no power supply current restrictions), the first control signal 202 is LOW. In response, the first transistor control circuitry 112 couples the voltage output 106 to the control terminal 108c (e.g., pulls down the control terminal 108c to the voltage output 106) via the second control path 116. Thus, the voltage at the control terminal 108c of transistor 108 is LOW. In response, transistor 108 is OFF so the first voltage input 102 is not coupled to the voltage output 106. Thus, the voltage at the voltage output 106 is LOW. Further, the second control signal 204 is HIGH. Because the second control signal 204 is HIGH and the voltage at the control terminal 108c of transistor 108 is non-negative, the first protection circuitry 120 is ON. Furthermore, because the voltage at the voltage output 106 is non-negative, the second protection circuitry 130 is OFF.

During low power mode (e.g., when the power supply (not shown) is coupled to the circuit 100, transistor 108 is to be ON, and the amount of current consumed by the power supply must be less than about 10 microamps, less than about 8 microamps, less than about 6 microamps, or some other suitable value), the first control signal 202 is HIGH. In response, the first transistor control circuitry 112 couples the second voltage input 104 to the control terminal 108c (e.g., pulls up the control terminal 108c to the second voltage input 104) via the first control path 114. Thus, the voltage at the control terminal 108c of transistor 108 is HIGH. In response, transistor 108 is ON so that the first voltage input 102 is coupled to the voltage output 106. Thus, the voltage at the voltage output 106 is HIGH. Further, the second control signal 204 is LOW. Thus, the first protection circuitry 120 is OFF. Furthermore, because the voltage output is non-negative, the second protection circuitry 130 is OFF.

In some cases, a negative voltage may be applied at the voltage output 106 (e.g., during circuit testing such as direct power injection (DPI) testing or some other circuit testing). During this negative output voltage mode (e.g., when the voltage at the voltage output 106 is negative, the power supply is coupled to the circuit 100, and transistor 108 is to be OFF), transistor 108 may be briefly turned ON. Because the voltage at the voltage output 106 is negative, the second protection circuitry 130 turns ON. In response, the control terminal 108c of transistor is coupled to the voltage output 106 via the fourth current path 132. Thus, the difference between the voltage at the control terminal 108c of transistor 108 and the voltage at the voltage output (e.g., the gate-to-source voltage Vgs) drops to approximately zero. In response, transistor 108 turns OFF.

During sleep mode (e.g., when the power supply is coupled to the circuit 100, transistor 108 is to be OFF and the amount of current consumed by the power supply connected to the circuit must be less than 2 microamps, less than 1 microamp, or some other suitable value), the first control signal 202 is unavailable and thus transistor control circuitry 112 does not couple the control terminal 108c to the second voltage input 104 nor the voltage output 106. The second control signal 204 remains available and is HIGH. Because the second control signal 204 is HIGH and the voltage at the control terminal 108c of transistor 108 is non-negative, the first protection circuitry 120 is ON. In response, the control terminal 108c of transistor 108 is coupled to ground 122 via the second current path 124 and the third current path 126. Thus, the voltage at the control terminal 108c of transistor 108 is LOW. In response, the first transistor 108 is OFF so that the first voltage input 102 is not coupled to the voltage output 106. Thus, the voltage at the voltage output 106 is LOW. Furthermore, because the voltage at the voltage output 106 is non-negative, the second protection circuitry 130 is OFF.

During no power supply mode (e.g., when the power supply is not coupled to the circuit 100 and transistor 108 is to be OFF), the first control signal 202 is unavailable and thus transistor control circuitry 112 does not couple the control terminal 108c to the second voltage input 104 nor the voltage output 106. The second control signal 204 remains available and is HIGH. Because the second control signal 204 is HIGH and the voltage at the control terminal 108c of transistor 108 is non-negative, the first protection circuitry 120 is ON. In response, the control terminal 108c of transistor 108 is coupled to ground 122 via the second current path 124 and the third current path 126. Thus, the voltage at the control terminal 108c of transistor 108 is LOW. In response, the first transistor 108 is OFF so that the first voltage input 102 is not coupled to the voltage output 106. Thus, the voltage at the voltage output 106 is LOW. Furthermore, because the voltage at the voltage output 106 is non-negative, the second protection circuitry 130 is OFF.

In some examples, the second control signal 204 is available during sleep mode and no power supply mode because the second control signal 204 is generated using a power-on reset (POR) signal which is available regardless of operation mode.

FIG. 3 is a circuit diagram of some examples of a system 300 including the circuit 100 of FIG. 1. The system 300 further includes a controller 302, a voltage source 304, a voltage converter 306, and load circuitry 308.

The controller 302 (e.g., a microcontroller or some other suitable controller circuitry) includes a first output 302a and a second output 302b. The first output 302a of the controller 302 is coupled to the first control signal input 134 of circuit 100. The second output 302b of the controller 302 is coupled to second control signal input 128 of circuit 100.

The voltage source 304 (e.g., a battery or some other suitable direct current (DC) voltage source) includes a first terminal 304a (e.g., a positive terminal) and a second terminal 304b (e.g., a negative terminal). The first terminal 304a is coupled to the first voltage input 102 of circuit 100 and the voltage converter 306. In some examples, the second terminal 304b is coupled to ground 122.

The voltage converter 306 (e.g., a charge pump, a boost DC-to-DC converter, or some other suitable voltage conversion circuitry) includes an input 306a and an output 306b. The input 306a of the voltage converter 306 is coupled to the first terminal 304a of the voltage source 304. The output 306b of the voltage converter 306 is coupled to the second voltage input 104 of circuit 100. In some examples, the voltage source 304 and the voltage converter 306 are part of the power supply.

The load circuitry 308 includes a first terminal 308a and a second terminal 308b. The first terminal 308a of the load circuitry 308 is coupled to the voltage output 106 of circuit 100. In some examples, the second terminal 308b of the load circuitry 308 is coupled to ground 122. The load circuitry 308 may for example, include resistor(s), inductor(s), and capacitor(s).

The controller 302 is configured to generate the first control signal (e.g., first control signal 202 of FIG. 2) and the second control signal (e.g., second control signal 204 of FIG. 2). The controller 302 is configured to provide the first control signal to the control terminal 112d of the first transistor control circuitry 112 via the first control signal input 134 to control the first transistor control circuitry 112. The controller 302 is configured to provide the second control signal to the control terminal 120d of the first protection circuitry 120 via the second control signal input 128 to control the first protection circuitry 120.

The voltage source 304 is configured to generate a first voltage (e.g., a DC voltage) at the first terminal 304a. The voltage converter 306 is configured to receive the first voltage (at input 306a) from the voltage source 304 and generate a second voltage (at output 306b) greater than the first voltage. In some examples, the first voltage is in a range from about 3 volts to about 40 volts or some other suitable range. Further, the second voltage is about 8 volts higher than the first voltage, 10 volts higher than the first voltage, 12 volts higher than the first voltage, or some other suitable voltage.

Circuit 100 is configured to provide current to the load circuitry 308 by selectively coupling the voltage source 304 to the load circuitry 308 using transistor 108.

FIG. 4 is a circuit diagram of some examples of a circuit 400 similar to the circuit 100 of FIG. 1 in which the first transistor control circuitry 112, the first protection circuitry 120, and the second protection circuitry 130 include a plurality of transistors.

For example, the first transistor control circuitry 112 includes a second transistor 402 (e.g., a pull-up transistor) and a third transistor 404 (e.g., a pull-down transistor). Transistor 402 is coupled between the second voltage input 104 and the control terminal 108c of transistor 108 in the first control path 114. The first control path includes the second voltage input 104, a first terminal 402a of transistor 402, a second terminal 402b of transistor 402, and the control terminal 108c of transistor 108.

Transistor 404 is coupled between the voltage output 106 and the control terminal 108c of transistor 108 in the second control path 116. The second control path 116 includes the voltage output 106, a first terminal 404a of transistor 404, a second terminal 404b of transistor 404, and the control terminal 108c of transistor 108.

In some examples, the first transistor control circuitry 112 further includes an inverter 426. An input (not labeled) of inverter 426 is coupled to the first control signal input 134. A control terminal 402c of transistor 402 is coupled to an output (not labeled) of inverter 426. Further, a control terminal 404c of transistor 404 is coupled to the output (not labeled) of inverter 426.

Inverter 426 is configured to receive the first control signal (e.g., first control signal 202 of FIG. 7) from the first control signal input 134. Inverter 426 inverts the first control signal and outputs an inverted first control signal. Transistor 402 and transistor 404 are configured to receive the inverted first control signal at control terminal 402c and control terminal 404c, respectively, from inverter 426. Transistor 402 is configured to selectively couple the control terminal 108c of transistor 108 to the second voltage input 104 (via the first control path 114) based on the (inverted) first control signal. Transistor 404 is configured to selectively couple the control terminal 108c of transistor 108 to the voltage output 106 (via the second control path 116) based on the (inverted) first control signal.

For example, when the first control signal is HIGH (when the inverted first control signal is LOW), transistor 402 is ON and transistor 404 is OFF, as shown, for example, in FIG. 7. In response, the second voltage input 104 is coupled to the control terminal 108c of transistor 108 via the first control path 114. Thus, the voltage at the control terminal 108c of transistor is HIGH. In response, transistor 108 turns ON so that the first voltage input 102 is coupled to the voltage output 106. Thus, the voltage at the voltage output 106 is HIGH. Conversely, when the first control signal is LOW (when the inverted first control signal is HIGH), transistor 402 turns OFF and transistor 404 turns ON, as shown, for example, in FIG. 7. In response, the voltage output 106 is coupled to the control terminal 108c of transistor 108 via the second control path 116. Thus, the voltage at the control terminal 108c is LOW. In response, transistor 108 turns OFF and hence the first voltage input 102 is not coupled to the voltage output 106. Thus, the voltage at the voltage output 106 is LOW.

The first protection circuitry 120 includes a fourth transistor 406, a fifth transistor 408, a sixth transistor 410, and a first resistor 412. Transistor 406 is coupled between the control terminal 108c of the first transistor 108 and ground 122 in both the second current path 124 and the third current path 126. A control terminal 406c of transistor 406 is coupled to the second control signal input 128.

Transistor 408 is coupled between the control terminal 108c of transistor 108 and a first terminal 406a of transistor 406 in the second current path 124. A control terminal 408c of transistor 408 is coupled to a first terminal 408a of transistor 408 so that transistor 408 is a “diode-connected” transistor that allows unidirectional current flow from the control terminal 108c of transistor 108 to ground 122.

Transistor 410 is coupled between the control terminal 108c of transistor 108 and the first terminal 406a of transistor 406 in the third current path 126. Resistor 412 is coupled between the control terminal 108c of transistor 108 and a first terminal 410a of transistor 410 in the third current path 126. A control terminal 410c of transistor 410 is coupled to the first terminal 410a of transistor 410 (through resistor 412) so that transistor 410 is a “diode-connected” transistor that allows unidirectional current flow from the control terminal 108c of transistor 108 to ground 122.

The second current path 124 includes the control terminal 108c of transistor 108, the first terminal 408a of transistor 408, a second terminal 408b of transistor 408, the first terminal 406a of transistor 406, a second terminal 406b of transistor 406, and ground 122. The third current path 126 includes the control terminal 108c of the first transistor 108, a first terminal 412a of resistor 412, a second terminal 412b of resistor 412, the first terminal 410a of transistor 410, a second terminal 410b of transistor 410, the first terminal 406a of transistor 406, the second terminal 406b of transistor 406, and ground 122.

Transistor 406 is configured to receive a second control signal (e.g., second control signal 204 of FIG. 7) at the control terminal 406c of transistor 406 from second control signal input 128. Transistor 406, transistor 408, and transistor 410 are configured to selectively couple the control terminal 108c of transistor 108 to ground 122 (via the second current path 124 and the third current path 126) based on the second control signal and the voltage at the control terminal 108c of transistor 108.

For example, when the second control signal (e.g., second control signal 204 of FIG. 7) is HIGH, transistor 406 is ON, as shown, for example, in FIG. 7. When transistor 406 is ON and the voltage at the control terminal 108c is non-negative, transistor 408 and transistor 410 are ON (e.g., transistor 408 and transistor 410 are forward biased). When transistor 408 is ON, the control terminal 108c of transistor 108 is coupled to ground 122 via the second current path 124. However, the voltage drop across transistor 408 is greater than zero. Thus, the voltage at the control terminal 108c of transistor 108 is greater than zero. To bring the voltage at the control terminal 108c of transistor 108 closer to zero, transistor 410 is included in the first protection circuitry 120. Transistor 410 has a reduced voltage drop. For example, transistor 410 is a “natural” device having a voltage drop approximately equal to zero. When transistor 410 is ON, the control terminal 108c of transistor 108 is coupled to ground 122 via the third current path 126 and thus the voltage at the control terminal 108c of transistor 108 is pulled down to approximately zero. Resistor 412 is included in the third current path 126 to limit the current in the third current path 126 to protect transistor 410. Thus, transistor 408 flows a majority of the current from the control terminal 108c of transistor 108 to ground 122 (via the second current path 124) while transistor 410 flows a minority of the current from the control terminal 108c of transistor 108 to ground 122 (via the third current path 126). When the control terminal 108c of transistor 108 is coupled to ground 122, the voltage at the control terminal 108c of transistor 108 is LOW. In response, transistor 108 is OFF so that the first voltage input 102 is not coupled to the voltage output. Thus, the voltage at the voltage output 106 is LOW.

When the second control signal is LOW, transistor 406 is OFF and hence transistor 408 and transistor 410 are OFF, as shown, for example, in FIG. 7. Thus, the control terminal 108c of transistor 108 is not coupled to ground 122.

Further, when the voltage at the voltage output 106 is negative, transistor 408 and transistor 410 are OFF (e.g., reverse biased), as shown, for example, in FIG. 7. Thus, the control terminal 108c of transistor 108 is not coupled to ground 122.

The second protection circuitry 130 includes a seventh transistor 414, an eighth transistor 416, a second resistor 418, and a ninth transistor 420. Transistor 414 is coupled between the control terminal 108c of transistor 108 and the voltage output 106 in the fourth current path 132. The fourth current path includes the control terminal 108c of transistor 108, a first terminal 414a of transistor 414, a second terminal 414b of transistor 414, and the voltage output 106.

Transistor 416 is coupled between the voltage output 106 and ground 122 in a fifth current path 424. A control terminal 416c of transistor 416 is coupled to a first terminal 416a of transistor 416 so that transistor 416 is a “diode-connected” transistor that allows unidirectional current flow from ground 122 to the voltage output 106. A control terminal 414c of transistor 414 is coupled to the control terminal 416c of transistor 416.

Resistor 418 is coupled between the first terminal 416a of transistor 416 and ground 122 in the fifth current path 424. Transistor 420 is coupled between a second terminal 418b of resistor 418 and ground 122 in the fifth current path 424. A control terminal 420c of transistor 420 is coupled to a second terminal 420b of transistor 420 so that transistor 420 is a “diode-connected” transistor that allows unidirectional current flow from ground 122 to the voltage output 106. In some examples, transistor 420 forms a body diode 422 that is coupled between the second terminal 420b and a first terminal 420a of transistor 420.

The fifth current path 424 includes ground 122, the second terminal 420b of transistor 420, the first terminal 420a of transistor 420, the second terminal 418b of resistor 418, a first terminal 418a of resistor 418, the first terminal 416a of transistor 416, a second terminal 416b of transistor 416, and the voltage output 106.

Transistor 414 is configured to selectively couple the control terminal 108c of transistor 108 to the voltage output 106 (via the fourth current path 132) based on the voltage at the voltage output 106. For example, when the voltage at the voltage output 106 is negative, transistor 416 and transistor 420 are ON (e.g., transistor 416 and transistor 420 are forward biased). Thus, current can flow from ground 122 to the voltage output 106 via the fifth current path 424. In response to transistor 416 and transistor 420 turning ON, transistor 414 turns ON. Because transistor 414 is ON, the control terminal 108c of transistor 108 is coupled to the voltage output 106. Thus, the voltage at the control terminal 108c of transistor 108 is approximately equal to the voltage at the voltage output 106. In response, transistor 108 is OFF so that the first voltage input 102 is not coupled to the voltage output 106.

Further, when the voltage at the voltage output 106 is non-negative, transistor 416 and transistor 420 are OFF (e.g., reverse biased) and hence transistor 414 is OFF, as shown, for example, in FIG. 7. Thus, control terminal 108c is not coupled to the voltage output 106.

During low power mode, the second control signal is LOW and the voltage at the voltage output 106 is non-negative. In response, transistor 406, transistor 408, transistor 410, transistor 416, transistor 420, and transistor 414 are OFF so that control terminal 108c is not coupled to ground 122 nor the voltage output 106. Thus, current leakage from control terminal 108c to ground 122 or to the voltage output 106 may be eliminated. As a result, the power supply current consumption requirement for low power mode can be met.

Although transistor 408, transistor 410, transistor 416, and transistor 420 are referred to as “diode-connected transistors”, it will be appreciated that in some examples, these transistors could alternatively be referred to as unidirectional current devices and/or could alternatively be diodes or the like.

FIG. 5A and FIG. 5B are a circuit diagram of some examples of a circuit 500 similar to the circuit 400 of FIG. 4 in which a tenth transistor 506 is coupled between the first voltage input 102 and the voltage output 106 in a sixth current path 507 that is parallel to the first current path 110.

The circuit 500 includes a first portion 501a and a second portion 501b. The first portion 501a includes the first voltage input 102, the second voltage input 104, the first control signal input 134, the second control signal input 128, the voltage output 106, transistor 108, the first transistor control circuitry 112 (including transistor 402, transistor 404, and inverter 426), the first protection circuitry 120 (including transistor 406, transistor 408, transistor 410, and resistor 412), and the second protection circuitry 130 (including transistor 414, transistor 416, resistor 418, and transistor 420), which are coupled together as discussed with reference to FIG. 4. Further, the first portion 501a includes the first current path 110, the first control path 114, the second control path 116, the second current path 124, the third current path 126, the fourth current path 132, and the fifth current path 424, as discussed with reference to FIG. 4.

In brief, the second portion 501b is a copy of the first portion 501a. More specifically, the second portion 501b includes the first voltage input 102, a third voltage input 502, a third control signal input 505, the second control signal input 128, the voltage output 106, a tenth transistor 506, second transistor control circuitry 504, third protection circuitry 510, and fourth protection circuitry 512.

Transistor 506 is coupled between the first voltage input 102 and the voltage output 106 in a sixth current path 507. The sixth current path 507 includes the first voltage input 102, a first terminal 506a of transistor 506, a second terminal 506b of transistor 506, and the voltage output 106. The sixth current path 507 is parallel to the first current path 110.

The second transistor control circuitry 504 includes an eleventh transistor 514 and a twelfth transistor 518. Transistor 514 is coupled between the third voltage input 502 and a control terminal 506c of transistor 506 in a third control path 516 (e.g., a second pull-up path). The third control path 516 includes the third voltage input 502, a first terminal 514a of transistor 514, a second terminal 514b of transistor 514, and the control terminal 506c of transistor 506. Transistor 518 is coupled between the voltage output 106 and the control terminal 506c of transistor 506 in a fourth control path 520 (e.g., a second pull-down path). The fourth control path 520 includes the voltage output 106, a second terminal 518b of transistor 518, a first terminal 518a of transistor 518, and the control terminal 506c of transistor 506.

In some examples, the second transistor control circuitry 504 further includes an inverter 548. An input (not labeled) of inverter 548 is coupled to the third control signal input 505. A control terminal 514c of transistor 514 is coupled to an output (not labeled) of inverter 548. A control terminal 518c of transistor 518 is coupled to the output (not labeled) of inverter 548.

The third protection circuitry 510 includes a thirteenth transistor 522, a fourteenth transistor 528, a fifteenth transistor 530, and a third resistor 532. Transistor 528 and transistor 522 are coupled between the control terminal 506c of transistor 506 and ground 122 in a seventh current path 524. The seventh current path 524 includes the control terminal 506c of transistor 506, a first terminal 528a of transistor 528, a second terminal 528b of transistor 528, a first terminal 522a of transistor 522, a second terminal 522b of transistor 522, and ground 122.

Resistor 532, transistor 530, and transistor 522 are coupled between the control terminal 506c of transistor 506 and ground 122 in an eighth current path 526. The eighth current path 526 includes the control terminal 506c of transistor 506, a first terminal 532a of resistor 532, a second terminal 532b of resistor 532, a first terminal 530a of transistor 530, a second terminal 530b of transistor 530, the first terminal 522a of transistor 522, the second terminal 522b of transistor 522, and ground 122.

A control terminal 522c of transistor 522 is coupled to the second control signal input 128. A control terminal 528c of transistor 528 is coupled to the first terminal 528a of transistor 528 so that transistor 528 is a “diode-connected” transistor that allows unidirectional current flow from the control terminal 108c of transistor 108 to ground 122 (via the seventh current path 524). A control terminal 530c of transistor 530 is coupled to the first terminal 530a of transistor 530 (through resistor 532) so that transistor 530 is a “diode-connected” transistor that allows unidirectional current flow from the control terminal 108c of transistor 108 to ground 122 (via the eighth current path 526).

The fourth protection circuitry 512 includes a sixteenth transistor 534, a seventeenth transistor 538, a fourth resistor 542, and an eighteenth transistor 544. Transistor 534 is coupled between the control terminal 506c of transistor 506 and the voltage output 106 in a ninth current path 536. The ninth current path 536 includes the control terminal 506c of transistor 506, a first terminal 534a of transistor 534, a second terminal 534b of transistor 534, and the voltage output 106.

Transistor 538, resistor 542, and transistor 544 are coupled between the voltage output 106 and ground 122 in a tenth current path 540. The tenth current path 540 includes ground 122, a second terminal 544b of transistor 544, a first terminal 544a of transistor 544, a second terminal 542b of resistor 542, a first terminal 542a of resistor 542, a first terminal 538a of transistor 538, a second terminal 538b of transistor 538, and the voltage output 106. In some examples, transistor 544 forms a body diode 546 that is coupled between the second terminal 544b and the first terminal 544a of transistor 544.

A control terminal 534c of transistor 534 is coupled to a control terminal 538c of transistor 538. The control terminal 538c of transistor 538 is coupled to the first terminal 538a of transistor 538 so that transistor 538 is a “diode-connected” transistor that allows unidirectional current flow from ground 122 to the voltage output 106 (via the tenth current path 540). A control terminal 544c of transistor 544 is coupled to the second terminal 544b of transistor 544 so that transistor 544 is a “diode-connected” transistor allows unidirectional current flow from ground 122 to the voltage output 106 (via the tenth current path 540).

In some example systems, the first voltage input 102 is coupled to a voltage source (e.g., voltage source 304 of FIG. 3), the second voltage input 104 is coupled to an output of a first voltage converter (e.g., output 306b of voltage converter 306 of FIG. 3), and the third voltage input 502 is coupled to an output of a second voltage converter (not shown), different than the first voltage converter. Further, the third control signal input 505 is coupled to an output of a controller (e.g., a third output (not shown) of controller 302 of FIG. 3).

In some examples, transistors 108, 404, 406, 408, 410, 414, 416, 420, 506, 518, 522, 528, 530, 534, 538, 544 are n-channel metal oxide semiconductor field effect transistors (MOSFETs), and transistors 402, 514 are p-channel MOSFETs. Although the transistors shown in FIG. 4, FIG. 5A, and FIG. 5B are illustrated and described as being MOSFETs, in some other examples the transistors can alternatively be corresponding bipolar junction transistors (BJTs), junction field-effect transistors (JFETs), or some other suitable transistors.

Transistor 108 includes a first number of channels and transistor 506 includes a second number of channels, greater than the first number of channels. For example, transistor 108 includes one channel and transistor 506 includes two or more channels (e.g., two channels, three channels, four channels, five channels, etc.). Other numbers of channels are also possible.

FIG. 6 is a top view of one example of an integrated chip including transistor 108 and transistor 506. Transistor 108 includes a channel 602 extending between a first source/drain region 604a and a second source/drain region 604b. A first gate electrode 606 extends over channel 602. The first source/drain region 604a is coupled to the first voltage input 102 and forms the first terminal 108a of transistor 108. The second source/drain region 604b is coupled to the voltage output 106 and forms the second terminal 108b of transistor 108. The first gate electrode 606 forms the control terminal 108c of transistor 108.

Further, transistor 506 includes a first channel 608a extending between the first source/drain region 604a and a third source/drain region 604c, a second channel 608b extending between the third source/drain region 604c and a fourth source/drain region 604d, a third channel 608c extending between the fourth source/drain region 604d and a fifth source/drain region 604e, and a fourth channel 608d extending between the fifth source/drain region 604e and a sixth source/drain region 604f. A first finger of a second gate electrode 610 extends over the first channel 608a, a second finger of the second gate electrode 610 extends over the second channel 608b, a third finger of the second gate electrode 610 extends over the third channel 608c, and a fourth finger of the second gate electrode 610 extends over the fourth channel 608d. The first source/drain region 604a, the fourth source/drain region 604d, and the sixth source/drain region 604f are coupled to the first voltage input 102 and form the first terminal 506a of transistor 506. The third source/drain region 604c and the fifth source/drain region 604e are coupled to the voltage output 106 and form the second terminal 506b of transistor 506. The second gate electrode 610 forms the control terminal 506c of transistor 506.

Although transistor 108 and transistor 506 are illustrated as planar transistors in FIG. 6, in some other examples, transistor 108 and transistor 506 may alternatively be three-dimensional transistors (e.g., fin field effect transistors, gate-all-around field effect transistors, or the like).

FIG. 7 is an example timing diagram corresponding to the circuit 500 of FIG. 5A and FIG. 5B.

During normal ON mode (e.g., when the power supply (voltage source 304 and voltage converter 306) is coupled to the circuit 500, the first voltage input 102 is to be coupled to the voltage output 106 via both the first current path 110 and the sixth current path 507, and there are no supply current restrictions), the first control signal 202 is HIGH (when the inverted first control signal is LOW) and the third control signal 702 is HIGH (when the inverted third control signal is LOW). In response, transistor 402 and transistor 514 are ON while transistor 404 and transistor 518 are OFF so that the second voltage input 104 is coupled to control terminal 108c (via the first control path 114) and the third voltage input 502 is coupled to control terminal 506c (via the third control path 516). Thus, the voltage at control terminal 108c is HIGH and the voltage at control terminal 506c is HIGH. In response, transistor 108 and transistor 506 are ON so that the first voltage input 102 is coupled to the voltage output 106 through transistor 108 (via the first current path 110) and through transistor 506 (via the sixth current path 507). Thus, the voltage at the voltage output 106 is HIGH. Further, the second control signal 204 is LOW. Thus, transistor 406 and transistor 522 are OFF and hence transistor 408, transistor 410, transistor 528, and transistor 530 are OFF. Furthermore, because the voltage output is non-negative, transistor 416, transistor 420, transistor 538, and transistor 544 are OFF and hence transistor 414 and transistor 534 are OFF.

During normal OFF mode (e.g., when the power supply is coupled to the circuit 500, the first voltage input 102 is not to be coupled to the voltage output 106, and there are no power supply current restrictions), the first control signal 202 is LOW and the third control signal 702 is LOW. In response, transistor 404 and transistor 518 are ON while transistor 402 and transistor 514 are OFF so that the voltage output 106 is coupled to the control terminal 108c of transistor 108 (via the second control path 116) and the control terminal 506c of transistor 506 (via the fourth control path 520). Thus, the voltage at control terminal 108c is LOW and the voltage at control terminal 506c is LOW. In response, transistor 108 is OFF and transistor 506 is OFF so that the first voltage input 102 is not coupled to the voltage output 106. Thus, the voltage output 106 is LOW. Further, the second control signal 204 is HIGH. Because the second control signal 204 is HIGH, transistor 406, transistor 408, and transistor 410 are ON and transistor 522, transistor 528, and transistor 530 are ON. Furthermore, because the voltage at control terminal 108c is non-negative and the voltage at control terminal 506c is non-negative, transistor 416, transistor 420, transistor 538, and transistor 544 are OFF and hence transistor 414 and transistor 534 are OFF.

During low power mode (e.g., when the power supply is coupled to the circuit 500, transistor 108 is to be ON, transistor 506 is to be OFF, and the amount of current consumed by the power supply must be less than about 10 microamps, less than about 8 microamps, less than about 6 microamps, or some other suitable value), the first control signal 202 is HIGH and the third control signal 702 is LOW. In response, transistor 402 is ON, transistor 514 is OFF, transistor 404 is OFF, and transistor 518 is ON so that the second voltage input 104 is coupled to control terminal 108c and the voltage output 106 is coupled to control terminal 506c. Thus, the voltage at control terminal 108c is HIGH and the voltage at control terminal 506c is LOW. In response, transistor 108 is ON and transistor 506 is OFF so that the first voltage input 102 is coupled to the voltage output 106 through transistor 108 (via the first current path) but not through transistor 506. Because the first voltage input 102 is coupled to the voltage output 106 through transistor 108 (via the first current path) but not through transistor 506, the voltage at the voltage output 106 may be slightly lower than during normal ON mode, but the voltage at the voltage output 106 is still HIGH. Further, the second control signal 204 is LOW. Thus, transistor 406 and transistor 522 are OFF and hence transistor 408, transistor 410, transistor 528, and transistor 530 are OFF. Furthermore, because the voltage at the voltage output 106 is non-negative, transistor 416, transistor 420, transistor 538, and transistor 544 are OFF and hence transistor 414 and transistor 534 are OFF.

In some examples, the second voltage input 104 is coupled to a first voltage converter (e.g., voltage converter 306 of FIG. 3) and the third voltage input 502 is coupled to a second voltage converter (not shown). The first voltage converter (not shown) is smaller (e.g., includes less stages) than the second voltage converter and more efficient than the second voltage converter. During low power mode, the second voltage input 104 is coupled to control terminal 108c but the third voltage input 502 is not coupled to control terminal 506c so that the more efficient voltage converter (the first voltage converter) is used and the less efficient voltage converter (the second voltage converter) is decoupled from the circuit. By using the more efficient voltage converter and decoupling the less efficient voltage converter during low power mode, the current consumed by power supply (e.g., the voltage source 304 of FIG. 3, the first voltage converter 306 of