2. A flyback capacitor CFLY may be connected across Q2 and Q3. An input or bus capacitor CBUS may be connected across Q1 and Q4. An output inductor LOUT may be connected from a midpoint between Q2 and Q3 to an output of application circuit 400. An output capacitor COUT may be connected between the output and ground.

The operation of outputting voltage from application circuit 400 may be made by charging and discharging flying capacitor CFLY.

FIG. 5 is an illustration of operation of example application circuit 400, according to examples of the present disclosure. In particular, FIG. 5 illustrates timing of signals generated by application using PWM signals from apparatus 100 that are not yet overridden, but may be overridden. During different phases of operation, different ones of Q1-Q4 may be activated.

In a first phase, Q1 and Q3 may be activated while Q2 and Q4 are deactivated. In this first phase, flying capacitor CFLY may be charged up to VIN.

In a second phase, Q4 and Q3 may be activated while Q1 and Q2 are deactivated.

In a third phase, Q4 and Q2 may be activated while Q1 and Q3 are deactivated. This may be the converse of the first phase.

In a fourth phase, Q4 and Q3 may be activated while Q1 and Q2 are deactivated. This may be a same operation as in the second phase.

FIG. 6 is an illustration of an example application circuit 600 to which apparatus 100 may provide PWM signals, according to examples of the present disclosure. In particular, multiple instances of apparatus 100 may include multiple instances of APWMH and APWML signal to control switches within the example application circuit 600. In particular, multiple instances of apparatus 100 may provide multiple instances of APWMH and APWML signals to control switches within the example application circuit 400. Application circuit 600 may be a four-level totem-pole power factor correction circuit.

In application circuit 600, a series of six switches Q1, Q2, Q3, Q4, Q5, Q6 may be connected in series from top to bottom, and may form a bridge. In parallel, two switches Q7 and Q8 may be connected in series with each other. A voltage source VIN may be connected between a midpoint of Q7 and Q8 at a first end of voltage source VIN and a first end of input inductor LIN on a second end of voltage source VIN. A second end of input inductor LIN may be connected to a midpoint of Q3 and Q4. These switches Q7, Q8, VIN, and LOUT may together form a rectifier. A flyback capacitor CF1 may be connected between a midpoint of Q1 and Q2 on a first end and a midpoint of Q5 and Q6 on a second end. A flyback capacitor CF2 may be connected between a midpoint of Q2 and Q3 on a first end and a midpoint of Q4 and Q5 on a second end. An output capacitor, CDC, may be connected between output and ground.

Q1 may be controlled by the PWM signal APWMH1, and Q6 may be controlled by the counterpart PWM signal APWML1. Q2 may be controlled by the PWM signal APWMH2, and Q5 may be controlled by the counterpart PWM signal APWML2. Q3 may be controlled by the PWM signal APWMH3, and Q4 may be controlled by the counterpart PWM signal APWML3.

FIG. 7 is an illustration of operation of example application circuit 600, according to examples of the present disclosure. Illustrated are VAC produced by VIN, VDC output from application circuit 600, the current through LIN, and switching voltage (VSW).

In application circuit 600, it may be important to properly balance the voltage of flying capacitors CF1, CF2 in order to achieve low total harmonic distortion (THD) of the input of the power supply. During level transitions of switching voltage VSW, wherein distinctly different voltage levels may be produced as VOUT, VFCAP representing voltage across flying capacitors CF1 and CF2 in FIG. 6 may become distorted through parasitic resistance. Distortions may lead to oscillations in voltage balancing, which might otherwise need to be actively compensated.

FIG. 8 is an illustration of operation of apparatus 100 to provide override signals to example application circuit 600 to which apparatus 100 may provide PWM signals, according to examples of the present disclosure. FIG. 8 may illustrate how both switches of a given complementary pair might be active at a same time through action of override circuit 104. Shown in FIG. 8 is the control of switches Q2 and Q5. PWMH2 signal is shown as control of Q2 as a baseline, without override. APWML2 signal is shown as control of Q5, though PWML2 would be the same signal. Override circuit 104 may augment PWMH2 to include the shaded portion shown in FIG. 8 to yield APWMH2 signal, wherein overlap may occur with APWML2 signal such that both switches Q2 and Q5 may be activated at a same time. There may be no risk of shoot-through current when both Q2 and Q5 are activated at a same time, because capacitors may be charged rather than a short being caused. The overlapping switch times may shorten flying capacitor centering startup voltage. The capacitors are to produce positive and negative sine waves, so the capacitors need to be completely discharged, or, discharged to a known half charge, or at a deterministic beginning point. The overlapping switch time may make the time to reach such a deterministic beginning point do this shorter.

FIG. 9 is an illustration of an example system 900 for override of PWM operating to generate generally complementary PWM signals, according to examples of the present disclosure. System 900 may include a PWM generator circuit 902, an override circuit 904, and an output circuit 908. PWM generator circuit 902 and override circuit 902 may implement or be implemented by, fully or in part, PWM generator circuit 102 and override circuit 104. PWM generator circuit 902, an override circuit 904, and an output circuit 908 may be implemented in any suitable manner, such as by analog circuitry, digital circuitry, instructions for execution by a processor (not shown), application specific integrated circuit, field programmable gate array, programmable logic, programmable hardware, programmable logic device, or any suitable combination thereof.

PWM generator circuit 902 may generate a first PWM signal, such as PWMH, and a second PWM signal, such as PWML. Signals PWHM and PWML may be generally complementary to each other in respect to their active portions.

Override circuit 904 may receive signals PWMH and PWML and output adjusted PWM signals such as APWMH and APWML based on PWMH and PWML to output circuit 908.

Output circuit 908