30. Each of the contact layers 32 is in ohmic contact with the source electrode 22. Each of the contact layers 32 extends in the y direction.

The body layer 34 is a p-type layer having a lower p-type impurity concentration than the contact layers 32. The body layer 34 is disposed at a position below the source layers 30 and the contact layers 32. The body layer 34 is in contact with the source layers 30 and the contact layers 32 from below. The body layer 34 is in contact with the gate insulating films 16 on the side surfaces of the trenches 14 located below the source layers 30. The body layer 34 faces the gate electrode 18 with the gate insulating film 16 interposed therebetween.

Each of the trench lower layers 35 is a p-type layer disposed at a position directly below a corresponding one of the trenches 14. In this example, each of the trench lower layers 35 is disposed at a position in contact with the bottom surface of the corresponding trench 14. That is, each of the trench lower layers 35 is in contact with the gate insulating film 16 at the bottom surface of the corresponding one of the trenches 14. As shown in FIG. 5, when the semiconductor substrate 12 is viewed from above, each of the trench lower layers 35 extends long along the y direction. That is, each of the trench lower layers 35 extends long in the y direction along the bottom surface of the corresponding one of the trenches 14. A p-type impurity concentration of each of the trench lower layers 35 is higher than a p-type impurity concentration of the body layer 34 and lower than a p-type impurity concentration of the contact layers 32. The p-type impurity concentration of each of the trench lower layers 35 is higher than a p-type impurity concentration of each of the p-type deep layers 36.

As shown in FIGS. 1 to 3, each of the p-type deep layers 36 is a p-type layer protruding downward from a lower surface of the body layer 34. The p-type deep layers 36 are arranged at intervals in the y direction. Each of the p-type deep layers 36 has a shape elongated in the z direction in the yz cross section. That is, a dimension of each of the p-type deep layers 36 in the z direction is larger than a dimension of each of the p-type deep layers 36 in the y direction. Each of the p-type deep layers 36 extends from the lower surface of the body layer 34 to a depth below a lower end of each of the trench lower layers 35. As shown in FIGS. 4 to 6, when the semiconductor substrate 12 is viewed from above, each of the p-type deep layers 36 extends long in the x direction. As shown in FIG. 4, when the semiconductor substrate 12 is viewed from above, the p-type deep layers 36 intersect the trenches 14. Each of the p-type deep layers 36 is in contact with the gate insulating film 16 on the side surface of each of the trenches 14 located below the body layer 34. As shown in FIG. 5, when the semiconductor substrate 12 is viewed from above, the p-type deep layers 36 intersect the trench lower layers 35. Each of the p-type deep layers 36 is connected to the trench lower layers 35 at intersections with the trench lower layers 35. The p-type impurity concentration of each of the p-type deep layers 36 is higher than the p-type impurity concentration of the body layer 34 and lower than the p-type impurity concentration of the contact layer 32. In the present embodiment, the x direction corresponds to a first direction, and the y direction corresponds to a second direction.

Each of the p-type deep layers 36 is in contact with the body layer 34 from below. Therefore, each of the p-type deep layers 36 is electrically connected to the source electrode 22 via the body layer 34 and the contact layers 32. As described above, the trench lower layers 35 are connected to the p-type deep layers 36 at the intersections between the trench lower layers 35 and the p-type deep layers 36. Therefore, each of the trench lower layers 35 is electrically connected to the source electrode 22 via the p-type deep layers 36, the body layer 34, and the contact layers 32.

FIG. 4 shows a cross section along the xy plane in a depth range R1 in which both the trenches 14 and the p-type deep layers 36 are present. FIG. 5 shows a cross section along the xy plane in a depth range R2 in which both the trench lower layers 35 and the p-type deep layers 36 are present. FIG. 6 shows a cross section along the xy plane in a depth range R3 below the lower ends of the trench lower layers 35 and above the lower ends of the p-type deep layers 36. As shown in FIGS. 4 to 6, in the depth ranges R1, R2, and R3, the p-type deep layers 36 are arranged at intervals in the y direction. Hereinafter, a portion between the p-type deep layers 36 is referred to as a spacing portion 39a. As shown in FIG. 4, in the depth range R1, the trenches 14 and the p-type deep layers 36 extend in a lattice shape. Therefore, a plurality of rectangular regions 39s defined by the trenches 14 and the p-type deep layers 36 are formed in each of the spacing portions 39a. As shown in FIG. 5, in the depth range R2, the trench lower layers 35 and the p-type deep layers 36 extend in a lattice shape. Therefore, a plurality of rectangular regions 39t partitioned by the trench lower layers 35 and the p-type deep layers 36 are formed in each of the spacing portions 39a.

As shown in FIG. 1 and FIG. 2, the drain-side n-type layer 42 is an n-type layer in contact with the drain electrode 24. The drain-side n-type layer 42 is distributed from a position in contact with the lower surface of the body layer 34 to the lower surface 12b of the semiconductor substrate 12 through the spacing portions 39a. The drain-side n-type layer 42 is in contact with the gate insulating film 16 on the side surface of each of the trenches 14 at positions below the body layer 34. The drain-side n-type layer 42 includes a high concentration layer 37, an intermediate concentration layer 38, a drift layer 39, and a drain layer 40. An n-type impurity concentration of the intermediate concentration layer 38 is higher than an n-type impurity concentration of the drift layer 39. An n-type impurity concentration of the high concentration layer 37 is higher than the n-type impurity concentration of the intermediate concentration layer 38. An n-type impurity concentration of the drain layer 40 is higher than the n-type impurity concentration of the high concentration layer 37.

The high concentration layer 37 is disposed at a position directly below the body layer 34. The high concentration layer 37 is distributed in a depth range from the lower end of the body layer 34 to a position below the lower end of each of the trench lower layers 35. Thus, as shown in FIG. 4 and FIG. 5, the high concentration layer 37 is distributed in the depth range R1 and the depth range R2. As shown in FIGS. 1 to 3, the high concentration layer 37 is disposed in each of the spacing portions 39a. The high concentration layer 37 is in contact with the lower surface of the body layer 34. As shown in FIG. 4, in the depth range R1, the high concentration layer 37 is disposed in the rectangular regions 39s. The high concentration layer 37 is in contact with the gate insulating film 16 on the side surface of each of the trenches 14. As shown in FIG. 5, in the depth range R2, the high concentration layer 37 is disposed in the rectangular regions 39t. The high concentration layer 37 is in contact with the side surface of each of the trench lower layers 35. As shown in FIG. 4 and FIG. 5, in the depth ranges R1 and R2, the high concentration layer 37 is in contact with the side surface of each of the p-type deep layers 36. As shown in FIG. 1, the high concentration layer 37 is in contact with the lower surface of each of the trench lower layers 35.

As shown in FIGS. 1 to 3, the intermediate concentration layer 38 is disposed at a position directly below the high concentration layer 37. The intermediate concentration layer 38 is distributed in a depth range from the lower end of the high concentration layer 37 to a position below the lower end of each of the p-type deep layers 36. Therefore, as shown in FIG. 6, the intermediate concentration layer 38 is distributed within the depth range R3. As shown in FIG. 1 and FIG. 6, the intermediate concentration layer 38 is disposed in each of the spacing portions 39a. The intermediate concentration layer 38 is in contact with the lower surface of the high concentration layer 37. The intermediate concentration layer 38 is in contact with the side surface and the lower surface of each of the p-type deep layers 36.

The drift layer 39 is disposed at a position directly below the intermediate concentration layer 38. The drift layer 39 is distributed over a range directly below the plurality of p-type deep layers 36 and the plurality of spacing portions 39a. The drift layer 39 is in contact with a lower surface of the intermediate concentration layer 38.

The drain layer 40 is disposed at a position directly below the drift layer 39. The drain layer 40 is distributed in a depth range from the lower end of the drift layer 39 to the lower surface 12b of the semiconductor substrate 12. The drain layer 40 is in contact with a lower surface of the drift layer 39. The drain layer 40 is in ohmic contact with the drain electrode 24.

Next, the operation of the MOSFET of the first embodiment will be described. Normally, the MOSFET is used in a state where a potential higher than a potential of the source electrode 22 is applied to the drain electrode 24. When a potential equal to or higher than a gate threshold value is applied to each of the gate electrodes 18, a channel is formed in the body layer 34 in the vicinity of the gate insulating film 16. The source layers 30 and the high concentration layer 37 are connected by the channel. Therefore, electrons flow from the source layers 30 to the drain layer 40 through the channel, the high concentration layer 37, the intermediate concentration layer 38, and the drift layer 39. That is, the MOSFET is turned on. When the potential of each of the gate electrodes 18 is reduced from a value equal to or higher than the gate threshold value to a value less than the gate threshold value, the channel disappears and the flow of electrons stops. In other words, the MOSFET is turned off.

Next, the operation when the MOSFET is turned on will be described in more detail. As described above, when the MOSFET is turned on, electrons flow from the source layers 30 to the drain layer 40 through the channel, the high concentration layer 37, the intermediate concentration layer 38, and the drift layer 39. Therefore, the high concentration layer 37 and the intermediate concentration layer 38 constitute a part of the current path. In the on-state of the MOSFET, a depletion layer having a predetermined width extends from the p-type deep layers 36 and the trench lower layers 35 to the high concentration layer 37 and the intermediate concentration layer 38 due to a built-in potential. The depletion layer narrows the current path inside the high concentration layer 37 and the intermediate concentration layer 38.

As shown in FIG. 4 and FIG. 5, in the depth ranges R1 and R2, each of the spacing portions 39a is divided into the plurality of rectangular regions 39s and 39t by the trenches 14 and the trench lower layers 35. Therefore, the area of the high concentration layer 37 is small in the xy cross section shown in FIG. 4 and FIG. 5. When the depletion layer widely extends from the p-type deep layers 36 and the trench lower layers 35 to the high concentration layer 37, the current path in the high concentration layer 37 becomes extremely narrow. However, since the n-type impurity concentration of the high concentration layer 37 is high, the extension of the depletion layer from the p-type deep layers 36 and the trench lower layers 35 to the high concentration layer 37 is restricted. Therefore, a wide current path can be secured in the high concentration layer 37. In addition, since the n-type impurity concentration of the high concentration layer 37 is high, the resistivity of the current path in the depth ranges R1 and R2 is reduced. Therefore, the resistance of the current path in the depth ranges R1 and R2 is reduced.

On the other hand, since the intermediate concentration layer 38 has the n-type impurity concentration lower than the n-type impurity concentration of the high concentration layer 37, the depletion layer extends relatively widely from the p-type deep layers 36 and the trench lower layers 35 to the intermediate concentration layer 38. The depletion layer narrows the current path in the intermediate concentration layer 38. However, as shown in FIG. 6, the trenches 14 and the trench lower layers 35 are not present in the depth range R3. Therefore, the intermediate concentration layer 38 in the depth range R3 has a larger area in the xy cross section than the high concentration layer 37 in the depth ranges R1 and R2. Therefore, even if the current path in the intermediate concentration layer 38 is narrowed by the depletion layer, a wide current path can be secured in the intermediate concentration layer 38. In addition, since the intermediate concentration layer 38 having the n-type impurity concentration higher than the n-type impurity concentration of the drift layer 39 is disposed in the depth range R3, the resistivity of the current path in the depth range R3 is reduced. Therefore, the resistance of the current path in the depth range R3 is reduced.

As described above, according to the first embodiment, the resistance of the current path in the spacing portions 39a can be reduced. Therefore, the on-resistance of the MOSFET of the first embodiment is low.

Next, the operation when the MOSFET is turned off will be described in more detail. When the channel disappears, a reverse voltage is applied to a pn junction at an interface between the body layer 34 and the drain-side n-type layer 42. Therefore, a depletion layer spreads from the body layer 34 to the drain-side n-type layer 42. Each of the p-type deep layers 36 is electrically connected to the source electrode 22 and has substantially the same potential as the body layer 34. Therefore, when the channel disappears, a reverse voltage is also applied to a pn junction at an interface between each of the p-type deep layers 36 and the drain-side n-type layer 42. Therefore, a depletion layer also spreads from each of the p-type deep layers 36 to the drain-side n-type layer 42. Furthermore, each of the trench lower layers 35 is electrically connected to the source electrode 22 and has substantially the same potential as the body layer 34. Therefore, when the channel disappears, a reverse voltage is also applied to a pn junction at an interface between each of the trench lower layers 35 and the drain-side n-type layer 42. Therefore, a depletion layer also spreads from each of the trench lower layers 35 to the drain-side n-type layer 42. Thus, the depletion layers extend from the body layer 34, the p-type deep layers 36, and the trench lower layers 35 to the drain-side n-type layer 42. Substantially all of the high concentration layer 37, the intermediate concentration layer 38, and the drift layer 39 are depleted. The drain layer 40 is hardly depleted. The high voltage applied between the drain electrode 24 and the source electrode 22 is held by the high concentration layer 37, the intermediate concentration layer 38, and the drift layer 39 that are depleted. The p-type impurity concentrations of the trench lower layers 35 and the p-type deep layers 36 are set such that a non-depleted region remains in the trench lower layers 35 and the p-type deep layers 36 when the MOSFET is in the off-state. Thereby, the extension of the depletion layers to the high concentration layer 37, the intermediate concentration layer 38, and the drift layer 39 is promoted.

Since each of the p-type deep layers 36 protrudes downward (that is, toward the drift layer 39) below the trench lower layer 35, an electric field is likely to concentrate around the lower end of each of the p-type deep layers 36. However, since the n-type impurity concentration of the intermediate concentration layer 38 adjacent to the p-type deep layers 36 is not so high, the periphery of the lower end of each of the p-type deep layers 36 is depleted relatively quickly when the MOSFET is turned off. Accordingly, an electric field concentration around the lower end of each of the p-type deep layers 36 can be restricted.

Since each of the trench lower layers 35 is in contact with the high concentration layer 37, the depletion layer is less likely to extend around each of the trench lower layers 35 when the MOSFET is turned off. That is, when the MOSFET is turned off, the speed at which the depletion layer extends around each of the trench lower layers 35 is slow. If the extension of the depletion layer is insufficient in the periphery of each of the trench lower layers 35, a high electric field is applied to the gate insulating film 16 covering the lower end portion of each of the trenches 14, and the insulating property of the gate insulating film 16 deteriorates. However, in the present embodiment, since the p-type deep layers 36 protrude downward below the trench lower layers 35, a high electric field is unlikely to be generated in a region above the lower end of each of the p-type deep layers 36. Therefore, even if the extension of the depletion layer is slow around each of the trench lower layers 35, the electric field applied to the gate insulating film 16 can be sufficiently restricted.

As described above, according to the first embodiment, it is possible to restrict the generation of a high electric field at the lower end of each of the p-type deep layers 36 and the lower end of each of the trenches 14. Therefore, the MOSFET of the first embodiment has a high breakdown voltage.

FIG. 7 shows the state of the trench lower layers 35 when the MOSFET is off. As described above, the p-type impurity concentration of the trench lower layers 35 is higher than the p-type impurity concentration of the p-type deep layers 36. Therefore, as shown in FIG. 7, in a state where the MOSFET is off, a relatively large non-depleted region 60 remains in a range in contact with the bottom surface of the corresponding trench 14 in each of the trench lower layers 35. Since the non-depleted region 60 remains at the position directly below each of the trenches 14, the feedback capacitance (that is, the electrostatic capacitance between the gate electrode 18 and the drain electrode 24) is reduced. Therefore, the MOSFET of the present embodiment can be switched at high speed. In addition, since the non-depleted region 60 remains at the position directly below each of the trenches 14, the electric field applied to the gate insulating film 16 can be reduced by the shielding effect.

Next, the operation when a load connected to the MOSFET is short-circuited in the on-state of the MOSFET of the first embodiment will be described. When the load is short-circuited, the potential of the drain electrode 24 becomes extremely higher than the potential of the source electrode 22, and a large current flows through the MOSFET. In addition, when the load is short-circuited, a high reverse voltage is applied to a pn junction at an interface between the drain-side n-type layer 42 and each p-type layer including the body layer 34, the p-type deep layers 36, and the trench lower layers 35. Therefore, a depletion layer extends from the p-type layers to the drain-side n-type layer 42. FIG. 8 shows a state of the p-type deep layers 36 and the trench lower layers 35 when the load is short-circuited. As shown in FIG. 8, when the load is short-circuited, the non-depleted region 60 remains in the central portions of the p-type deep layers 36 and the trench lower layers 35. This promotes the extension of the depletion layers from the p-type deep layers 36 and the trench lower layers 35 to the high concentration layer 37 and the intermediate concentration layer 38. Therefore, the high concentration layer 37 and the intermediate concentration layer 38 are instantaneously depleted when the load is short-circuited. Therefore, the current flowing through the MOSFET when the load is short-circuited (so-called saturation current) is reduced. In this way, since the p-type impurity concentrations of the p-type deep layers 36 and the trench lower layers 35 are set to high concentrations to the extent that the non-depleted regions 60 remain in the p-type deep layers 36 and the trench lower layers 35 when the load is short-circuited, the saturation current can be restricted.

The following describes a method of manufacturing the MOSFET according to the first embodiment. First, as shown in FIG. 9, the intermediate concentration layer 38, the high concentration layer 37, the p-type deep layers 36, the body layer 34, the source layers 30, and the contact layers 32 are formed by ion implantation into the drift layer 39. The p-type deep layers 36 are formed by implanting p-type impurities deeply into the upper surface 12a. Next, as shown in FIG. 10, the trenches 14 are formed by etching the upper surface 12a of the semiconductor substrate 12. Next, as shown in FIG. 11, p-type impurity ions are implanted into the bottom surfaces of the trenches 14 to form the trench lower layers 35. Next, as shown in FIG. 1, the gate insulating films 16, the gate electrodes 18, the interlayer insulating films 20, the source electrode 22, and the drain electrode 24 are formed. Accordingly, the MOSFET of the first embodiment is completed.

When the trenches 14 are formed, the depths of the trenches 14 vary. When the trench lower layers 35 are formed, the ion implantation depths vary. Therefore, the positions of the lower ends of the trench lower layers 35 are affected by both the variation in the depth of the trenches 14 and the variation in the depth of the ion implantation. Therefore, the variation in the positions of the lower ends of the trench lower layers 35 in the z direction is large. In the MOSFET of the first embodiment, since the p-type deep layers 36 protrude downward below the trench lower layers 35, the positions of the lower ends of the trench lower layers 35 do not significantly affect the breakdown voltage of the MOSFET. Therefore, even if the variation in the positions of the lower ends of the trench lower layers 35 is large, the variation in the breakdown voltage of the MOSFET hardly occurs. Furthermore, the positions of the lower ends of the p-type deep layers 36 in the z direction greatly affect the breakdown voltage of the MOSFET. As described above, the p-type deep layers 36 are formed by implanting p-type impurities into the upper surface 12a of the semiconductor substrate 12. Therefore, the variation in the depths of the trenches 14 does not affect the positions of the lower ends of the p-type deep layers 36. Therefore, the variation in the positions of the lower ends of the p-type deep layers 36 is small. Therefore, the variation in the breakdown voltage of the MOSFET is small.

Next, modifications of the first embodiment will be described.

In the first embodiment, the upper ends of the p-type deep layers 36 are in contact with the body layer 34. However, as shown in FIG. 12 and FIG. 13, the upper ends of the p-type deep layers 36 may be separated downward from the lower surface of the body layer 34. In FIG. 12, the upper ends of the p-type deep layers 36 are disposed within a depth range below the lower surface of the body layer 34 and above the lower ends of the trenches 14. In FIG. 13, the upper ends of the p-type deep layers 36 are disposed within a depth range below the lower ends of the trenches 14 and above the lower ends of the trench lower layers 35. In FIG. 12 and FIG. 13, the n-type layer (for example, the high concentration layer 37) is disposed between the p-type deep layers 36 and the body layer 34. Between the p-type deep layers 36 and the body layer 34, connection layers 50 of p-type are partially disposed. The connection layers 50 connect the p-type deep layers 36 and the body layer 34. The p-type deep layers 36 are electrically connected to the source electrode 22 via the connection layers 50, the body layer 34, and the contact layers 32. As described above, the upper ends of the p-type deep layers 36 may be disposed at positions separated from the body layer 34 as long as the upper ends are located above the lower ends of the trench lower layers 35.

In the first embodiment, the high concentration layer 37 is in contact with the body layer 34. However, as shown in FIG. 14 and FIG. 15, the upper end of the high concentration layer 37 may be separated downward from the lower surface of the body layer 34. In FIG. 14, the upper end of the high concentration layer 37 is disposed within a depth range below the lower surface of the body layer 34 and above the lower ends of the trenches 14. In FIG. 15, the upper end of the high concentration layer 37 is disposed within a depth range below the lower ends of the trenches 14 and above the lower ends of the trench lower layers 35. In FIG. 14 and FIG. 15, an n-type layer 52 having an n-type impurity concentration lower than the n-type impurity concentration of the high concentration layer 37 is disposed between the high concentration layer 37 and the body layer 34. As described above, as long as the high concentration layer 37 is present in at least a part of the depth range in which both the trench lower layers 35 and the p-type deep layers 36 are present, the upper end of the high concentration layer 37 may be disposed at a position separated from the body layer 34.

In the first embodiment, the lower end of the high concentration layer 37 (that is, the upper end of the intermediate concentration layer 38) is disposed below the lower ends of the trench lower layers 35. However, as shown in FIG. 16, the lower end of the high concentration layer 37 may be disposed within a depth range below the upper ends of the trench lower layers 35 and above the lower ends of the trench lower layers 35. Alternatively, the lower end of the high concentration layer 37 may be disposed at the same depth as the lower ends of the trench lower layers 35. As described above, as long as the high concentration layer 37 is present in at least a part of the depth range in which both the trench lower layers 35 and the p-type deep layers 36 are present, the lower end of the high concentration layer