210 to the memory 110. In addition, the controller 120 may transmit a plurality of control signals through the second conductive line 220 to the memory 110. Further, the controller 120 may transmit the data to write through the third conductive line 230 to the memory 110, or receive data read from the memory 110. Each of the conductive lines 210 to 230 may include one or a plurality of conductive lines. In addition, each conductive line may be connected to a terminal performing connection to the outside of the controller 120. Accordingly, a signal transmitted by the controller 120 may be transmitted through the terminal and the conductive line to the memory 110, and a signal transmitted by the memory 110 may reach the controller 120 through the terminal and the conductive line.

If a plurality of memories are connected to the controller 120, the chip select signal CS# may be used to select a control signal to be transmitted through the second conductive line 220 and the third conductive line 230 and a memory that receives data. The symbol # indicates that a corresponding signal is a low active signal which is ON (i.e., in a state of chip selection) when the signal is at a logic low level, and OFF (i.e., in a state of no chip selection) when a state of the signal is at a logic high level. According to an embodiment, the memory 110 may recognize the selection thereof when the memory 110 receives the chip select signal CS# having a logic low level.

The control signal may vary depending on a data transmission method of the protocol set between the controller 120 and the memory 110.

According to an embodiment, if the data transmission method is a multiplexed data transmission method which transmits or receives command, address and data in a multiplexed manner at the third conductive line 230, the control signal that is transmitted and received by the controller 120 through the second conductive line 220 may include a command latch enable (CLE) signal, an address latch enable (ALE) signal, a read enable (RE) signal, and a data strobe (DQS) signal.

The CLE signal may be a signal that allows information to be transmitted through the third conductive line 230 and be recognized as a command.

The ALE signal may be a signal that allows information to be transmitted through the third conductive line 230 and be recognized as an address.

The RE signal indicates a state where the controller 120 is able to receive data, and may be used only at the read operation.

The DQS signal may be a signal that allows the memory 110 to recognize timings of strobing data transmitted through the third conductive line 230. During the read operation, the memory 110 may generate the DQS signal and transmit it to the controller 120, and when the controller 120 transmits data to the memory 110 for writing, the controller 120 may generate the DQS signal and transmit it to the memory 110.

In another embodiment, in a data transmission method where a conductive line for address transmission and a conductive line for data transmission are provided separately, the control signals that the controller 120 transmits and receives through the second conductive line 230 may include a signal RD/WR# indicating whether a command is for a read or a write operation, an address signal for writing or reading data, a read enable (RE) signal, and a data strobe (DQS) signal. At this instance, through the third conductive line 230, only data may be transmitted.

FIG. 5 is a timing diagram when transmitting data to the memory for writing data according to a multiplexed data transmission method, and FIG. 6 is a timing diagram when reading data from the memory according to a multiplexed data transmission method.

The controller 120 may transmit a chip select signal CS# whose state is logic low through the first conductive line connected to the memory to which a command will be transmitted to indicate that the corresponding memory is selected. In addition, the controller 120 may transmit a command through the third conductive line 230 while activating a state of the CLE signal to be a logic high.

After that, in case of the data writing illustrated in FIG. 5, while toggling the DQS signal, the controller 120 may transmit a signal D1 to Dn such that data to be written into the memory can be transmitted from the third conductive line 230 at time points where a state of the DQS signal changes from logic low to logic high, and that changes from logic high to logic low.

In the case of the data read illustrated in FIG. 6, the controller 120 may indicate, to the memory 110, that the controller 120 can receive data while toggling the RE signal. The memory 110 may transmit the signal D1 to Dn such that the data read from the memory 110 can be transmitted from the third conductive line 230 at time points where a state of the DQS signal changes from logic low to logic high, and that changes from logic high to logic low, while toggling the DQS signal based on the received RE signal.

When the memory recognizes that the chip select signal CS# is activated to a state of logic low through the first conductive line 210 connected to the memory 110, the memory 110 may recognize that the subsequent control signal and data that the memory 110 receives through the second conductive line 220 and the third conductive line 230 are for the memory 110. The memory 110 may recognize a signal received through the third conductive line 230 as a command, in a state where the CLE signal is activated to a state of logic high. The command may include a memory write command or a memory read command. In addition, the memory 110 may recognize a signal received through the third conductive line 230 as an address signal, in the case where a state of the ALE signal is activated to logic high. In addition, in an example of FIG. 5, the memory 110 may recognize that the signal received through the third conductive line 230 as data D1 to Dn to write into the memory at a time point where the DQS signal changes from a state of logic low to logic high or from a state of logic high to logic low. In an example of FIG. 6, the memory 110 may recognize, from the received RE signal, that the controller 120 is ready to receive data, and may transmit a signal such that data read at a time point where the DQS signal changes from a state of logic low to logic high or from a state of logic high to logic low can be loaded at the third conductive line 230.

Referring to timing diagrams illustrated in FIG. 5 and FIG. 6, the RE signal should be toggled each time to indicate readiness to receive data, and the DQS signal should be toggled each time to indicate that there is a signal in the third conductive line 230. Change of the RE signal and/or the DQS signal by toggling each time as mentioned above may consume a significant amount of power

Therefore, embodiments of the present disclosure propose a measure to reduce power consumption by suppressing toggle of the RE signal and/or the DQS signal.

FIG. 7 is a timing diagram when transmitting data to the memory for writing data in the multiplexed data transmission method according to an embodiment of the present disclosure, and FIG. 8 is a timing diagram when reading data in the multiplexed data transmission method from the memory according to another embodiment of the present disclosure.

In the embodiments of FIG. 7 and FIG. 8, the multiplexed data transmission method has been taken as an example, however, the measure which will be described hereinafter may be used as it is in a method where an address connection and data connection are separately provided.

Referring to FIG. 7, the controller 120 may transmit the chip select signal CS# in a logical low state through the first conductive line 210 connected to the memory to which the controller 120 intends to transmit a command to indicate that the corresponding memory is selected. In addition, the controller 120 may transmit a command through the third conductive line 230 while activating the CLE signal, which is transmitted through the third conductive line 230, to a state of logic high. The corresponding command may include a data read or data write command. Next, the controller 120 may transmit an address through the third conductive line 230 while activating the ALE signal, which has been transmitted through the second conductive line 220, to a state of logic high.

After that, in the case of data writing illustrated in FIG. 7, the controller 120 may complete data transmission through two step toggling 510 in which the DQS signal toggles once at a time point of transmitting the initial data and toggles once more at a time point of transmitting the final data, instead of toggling the DQS signal continuously.

In addition, referring to FIG. 8, in case of data read, the controller 120 may complete the data read by only toggling the RE signal once when the controller 120 is ready to receive data, and toggling the RE signal once more when the controller 120 only needs to receive the last data. In response to the above, the memory 110 may complete the data transmission only by two step toggling 610 in which the DQS signal toggles once at a time point of transmitting the data read in response to the toggling of the first RE signal to the controller 120 and the DQS signal toggles once more at a time point of transmitting the final read data to the controller 120.

Accordingly, the power consumption may be reduced since toggling of the RE signal and the DQS signal can be significantly reduced.

In the embodiments of FIG. 7 and FIG. 8, for more precise operation, the same clock frequency which is synchronized between the controller 120 and the memory 110, or the same clock frequency which is not synchronized therebetween may be used. Accordingly, a data transmission rate may be shared between the controller 120 and the memory 110.

In addition, the controller 120 may indicate a size of data to read from the memory 110 or to write into the memory 110 before start of transmission. According to an embodiment, size information of data may be included with a command, which is transmitted in advance in FIG. 7 and FIG. 8, and delivered to the memory 110.

FIG. 9 is a sequence diagram illustrating operations between the controller 120 and the memory 110 for reading data from the memory according to an embodiment of the present disclosure.

Referring to FIG. 9, the controller 120 may set an interface rate between the controller 120 and the memory 110 in operation S710. According to an embodiment, setting the interface rate may be setting a frequency of a clock to be used by the interface. According to an embodiment, the controller 120 may set the interface rate only once for the first time after power is applied thereto. In another embodiment, changing the set value based on a performance or a state of the memory may be possible.

The controller 120 may transmit a size of data to read from the memory 110 in operation S720. According to an embodiment, the controller 120 may include a size of data intended to read with a read command that will be transmitted to the memory 110. However, the controller 120 may perform the operation S720 adjunctively. Even if the operation S720 is not performed, the memory 110 and the controller 120 may recognize a size of data intended to read based on the RE signal or DQS signal that will be transmitted later.

The controller 120 may transmit the first RE signal to indicate that it is ready to receive data to the memory 110 in operation S730. According to an embodiment, the controller 120 may transmit the first RE signal when the controller can receive all of the size of data intended to read which has been set in the operation S720.

In operation S740, the memory 110 may transmit the first DQS signal and the first data based on the reception of the first RE signal. The first DQS signal may be used as a signal indicating start of the data transmission.

In operation S750, the memory 110 may transmit data only to the controller 120 without toggling the DQS signal.

In operation S760, the controller 120 may transmit the second RE signal. The second RE signal may be the one indicating that the controller is not ready to receive data, and in another embodiment, the second RE signal may be the one indicating that the controller has received a size of data intended to read, which has been set in the operation S720.

The controller 120 may omit operation S760 which transmits the second RE signal if the controller 120 has transmitted the size of the data intended to read in advance in the operation S720. In another embodiment, if the controller has not received the preset size of the data even if the size of the data to be read in advance is transmitted in the operation S720, in order to indicate the it is ready to receive the data, the controller 120 may perform the operation S760 which transmits the second RE signal to stop the data transmission by the memory 110.

In operation S770, the memory 110 may transmit the second DQS signal and the last data, if the memory 110 receives the second RE signal from the controller 120, or transmits the last data having the size received in the operation S720.

In the operations S740 to S770, the controller 120 may receive the data transmitted by the memory 110 using an internal clock. At this instance, an error may occur due to a mismatch between a reception clock and a transmission clock if the reception clock used for receiving data by the memory 110 and the transmission clock used for transmitting data by the controller 120 are not synchronized, but the possibility of an error occurrence may be eliminated by adjusting a volume of data being transmitted, or by synchronizing the reception clock and the transmission clock.

When the controller 120 receives all data transmitted by the memory 110, the read operation may be completed.

FIG. 10 is a sequence diagram illustrating operations between the controller and the memory for writing data into the memory according to another embodiment of the present disclosure.

Referring to FIG. 10, the controller 120 may set an interface rate between the controller 120 and the memory 110 in operation S810. According to an embodiment, the setting may be setting a frequency of the clock to use in the interface. The controller 120 may set the interface rate only once for the first time after power is applied thereto, and may apply the set rate to all subsequent data reading or data writing. In another embodiment, changing the set value based on a performance or a state of the memory may be possible.

According to an embodiment, the controller 120 may set the interface rate at the data reading according to FIG. 9 and the interface rate at the data writing according to FIG. 10 differently.

In operation S820, the controller 120 may transmit the data size to write into the memory 110 to the memory 110. According to an embodiment, the controller 120 may include a size of the data to a write command that will be transmitted to the memory 110. However, the controller 120 may perform operation S820 adjunctively. Even if the operation S820 is not performed, the memory 110 may recognize a size of data intended to be written based on the DQS signal that will be transmitted later.

The controller 120 may transmit the first DQS signal and the first data in operation S830. The first DQS signal may be used as a signal indicating start of the data transmission.

In operation S840, the controller 120 may transmit data only to the memory 110 without toggling the DQS signal.

In operation S850, the controller 120 may complete the data transmission after transmitting the second DQS signal and the last data.

In operations S830 to S850, the memory 110 may receive data transmitted by the controller 120 using an internal clock. At this instance, an error may occur due to a mismatch between a reception clock and a transmission clock if the reception clock used for receiving data by the memory 110 and the transmission clock used for transmitting data by the controller 120 are not synchronized, but the possibility of the error occurrence may be eliminated by adjusting a volume of data being transmitted, or by synchronizing the reception clock and the transmission clock.

The controller 120 may complete the data writing after transmitting all data to write thereinto to the memory 110.

As described above, the method for transmitting data between the controller 120 and the memory 110 included in the storage device 110 proposed by the present disclosures may minimize power consumed by the storage device 100 by suppressing toggling that is performed at every data transmission of the DQS signal indicating presence of data in the third conductive line 230 and the RE signal indicating whether reception is available by the controller 120. The method described above may be summarized as below.

According to embodiments of the present disclosure, an electronic apparatus (e.g. controller (120) or host (150)) may comprises a first terminal connected to a first conductive line and configured to transmit, to an external device (e.g. memory (110) or storage device (100)), a read enable signal indicating whether data reception is available, a second terminal connected to a second conductive line and configured to transmit or receive, to or from the external device, a data strobe signal indicating start and end of data transmission, a third terminal connected to a third conductive line and configured to transmit or receive data to or from the external device; and an interface configured to control transmitting or receiving data to or from the external device, wherein the interface is configured to transmit, to the external device, a first read enable signal indicating whether the first terminal is ready to receive data, receive, from the external device, a first data strobe signal indicating start of data transmission through the second terminal and a first data through the third terminal at a same time, receive, from the external device, subsequent data after the first data through the third terminal, and receive, from the external device, a second data strobe signal indicating end of data transmission through the second terminal and a last data through the third terminal.

According to embodiments of the present disclosure, the interface may be configured to transmit, to the external device, a second read enable signal requesting to stop data transmission through the first terminal.

According to embodiments of the present disclosure, the interface may be configured to transmit, to the external device, a size of data to read through the third terminal before transmitting the first read enable signal.

According to embodiments of the present disclosure, a frequency of a clock used by the interface may be set to be equal to a frequency of a clock used by the external device.

According to embodiments of the present disclosure, the clock used by the interface may be synchronized with the clock used by the external device.

According to embodiments of the present disclosure, the interface may be configured to transmit, to the external device, a third data strobe signal indicating start of data to write and a first write data through the second terminal and the third terminal, transmit, to the external device, subsequent write data after the first write data through the third terminal, and transmit, to the external device, a fourth data strobe signal indicating end of write data transmission and a last write data through the second terminal and the third terminal.

According to embodiments of the present disclosure, the interface may be configured to transmit, to the external device, a size of the data to write before transmitting the third data strobe signal and the first data.

According to embodiments of the present disclosure, an electronic apparatus (e.g. controller (120) or host (150)) may comprises a first terminal connected to a first conductive line and configured to receive, from an external device (e.g. memory (110) or storage device (100)), a read enable signal indicating whether data reception is available, a second terminal connected to a second conductive line configured to transmit or receive, to or from the external device, a data strobe signal indicating start and end of data transmission, a third terminal connected to a third conductive line and configured to transmit or receive data to or from the external device and an interface configured to control transmitting or receiving data to or from the external device, wherein the interface is configured to receive, from the external device, a first read enable signal indicating whether the first terminal is ready to receive data, transmit, to the external device, a first data strobe signal indicating start of data transmission through the second terminal and a first data through the third terminal at a same time, transmit, to the external device, subsequent data after the first data through the third terminal, and transmit, to the external device, a second data strobe signal indicating end of data transmission through the second terminal and a last data through the third terminal.