314 may generate the mode switching signal MS of the next cycle according to the comparison result CMP and the mode switching signal MS of the current cycle. The logic circuit 314 may provide the mode switching signal MS of the next cycle to the slope compensation circuit 122 and the selection circuit 311, so that the circuits 122 and 311 operate according to the latest mode switching signal MS in the next cycle.

In this embodiment, the logic circuit 314 includes a memory unit RAM and a logic control unit LCU. The memory unit RAM is configured to store the comparison result CMP in the buck mode (referred to as a first value in the following embodiment), the comparison result CMP in the boost mode (referred to as a second value in the following embodiment), and the mode switching signal of the current cycle. The memory unit RAM may be, for example, any type of fixed or removable random access memory (RAM), read-only memory (ROM), flash memory, or similar components or a combination of the above components.

In this embodiment, the logic control unit LCU is coupled to the memory unit RAM. The logic control unit LCU may include multiple logic gates or digital logic circuits to perform operations as shown in FIG. 4 based on, for example, an excitation table in FIG. 5.

FIG. 4 is a schematic diagram of an operation of the mode switching circuit according to the embodiment of FIG. 3. In FIG. 4, an horizontal axis is operation time of the mode switching circuit 123, and a vertical axis is a voltage value or an operation value of the logic control unit LCU. Referring to FIGS. 3 and 4, operation details of the mode switching circuit 123 are described by taking the buck mode as an initial operation mode as an example. In this embodiment, the memory unit RAM further stores the mode switching signal MS of a previous cycle, so that the logic control unit LCU may further consider the mode switching signal MS of the previous cycle to generate the mode switching signal MS of the next cycle according to the comparison result CMP, the mode switching signal MS of the current cycle, and the mode switching signal MS of the previous cycle.

Referring to FIG. 5 together, FIG. 5 is the excitation table according to this embodiment. The excitation table includes multiple fields 510 to 530 and multiple other fields corresponding to the fields 510 to 530. “INPUT” shown in the field 510 may represent an input of the logic control unit LCU (i.e., the comparison result CMP). “Current State” shown in the field 520 may represent an operation mode of a current cycle and a previous cycle of the logic control unit LCU. “Next Output” shown in the field 530 may represent an output of the logic control unit LCU (i.e., the mode switching signal MS of the next cycle).

In detail, “X” shown in a field 511 is the first value stored in the memory unit RAM. The first value X may be the comparison result CMP in the buck mode of a latest cycle (i.e., the latest one). “Y” shown in a field 512 is the second value stored in the memory unit RAM. The second value Y may be the comparison result CMP in the boost mode of the latest cycle (i.e., the latest one).

“State” shown in a field 521 may represent the operation modes of the previous cycle and the current cycle. In this embodiment, the operation modes of the previous cycle and the current cycle may include the buck mode, the boost mode, the buck-boost mode, and the boost-buck mode, and are represented by codes S0 to S3 respectively. For example, the code S0 may indicate that the operation modes of the previous cycle and the current cycle are both the buck mode (i.e., buck). The code S1 may indicate that the operation mode of the previous cycle is the buck mode, and the operation mode of the current cycle is the boost mode (i.e., bb-boost). The code S2 may indicate that the operation mode of the previous cycle is the boost mode, and the operation mode of the current cycle is the buck mode (i.e., bb-buck). The code S3 may indicate that the operation modes of the previous cycle and the current cycle are both the boost modes (i.e., boost).

“Q1” shown in a field 522 may represent a value of the mode switching signal MS of the previous cycle. When the mode switching signal value Q1 is 0, the value of the mode switching signal MS indicating the previous cycle is 0 indicating the buck mode. When the mode switching signal value Q1 is 1, the value of the mode switching signal MS indicating the previous cycle is 1 indicating the boost mode. On the other hand, “Q0” shown in a field 523 may represent the mode switching signal value of the current cycle. When the mode switching signal value Q0 is 0, the value of the mode switching signal MS indicating the current cycle is 0 indicating the buck mode. When the mode switching signal value Q0 is 1, the value of the mode switching signal MS indicating the current cycle is 1 indicating the boost mode.

It should be noted that the mode switching signal MS of the previous cycle and the current cycle may be represented by the mode switching signal values Q1 and Q0 respectively. That is to say, the logic control unit LCU generates the mode switching signal MS of the next cycle according to the first value X, the second value Y, the mode switching signal value Q0 of the current cycle, and the mode switching signal value Q1 of the previous cycle.

The mode switching signal values Q1 and Q0 may also be combined into a set of 2-bit codes (i.e., the codes S0 to S3), which may simplify a circuit design of the logic control unit LCU. That is to say, the mode switching signal MS of the current cycle carries information of the operation mode of the previous cycle. The logic control unit LCU generates the mode switching signal MS of the next cycle according to the first value X, the second value Y, and the mode switching signal value Q0 of the current cycle.

“Cycle” shown in a field 532 may represent the operation mode of the next cycle. “Mode” shown in a field 531 may represent the value of the mode switching signal MS of the next cycle. When the value Mode of the mode switching signal MS is 0, it indicates that the operation mode of the next cycle is the buck mode. When the value Mode of the mode switching signal MS is 1, it indicates that the operation mode of the next cycle is the boost mode.

Referring to FIGS. 3 to 5, the mode switching circuit 123 may operate in multiple consecutive cycles C1 to C8 according to a frequency signal CLK, and switch the operations between the buck mode, the boost mode, the buck-to-boost mode, and the boost-to-buck mode (i.e., the buck-boost mode). In this embodiment, the input voltage VIN may be a constant voltage, for example. The output voltage VOUT may be a voltage signal with a fixed slope, for example.

Specifically, in the cycles C1 to C2 (i.e., a period P1), a voltage value of the output voltage VOUT is less than a voltage value of the input voltage VIN, and the mode switching circuit 123 operates in the buck mode. In the cycles C3 to C5 (i.e., a period P2), the voltage value of the output voltage VOUT is gradually adjusted from a voltage value less than the voltage value of the input voltage VIN to a voltage value greater than the voltage value of the input voltage VIN, and the mode switching circuit 123 sequentially switches between the buck mode and the boost mode (i.e., the buck-boost mode). In the cycles C7 to C8 (i.e., a period P3), the voltage value of the output voltage VOUT is greater than the voltage value of the input voltage VIN, and the mode switching circuit 123 operates in the boost mode.

In this embodiment, each of the cycles C3 to C6 in the period P2 of the buck-boost mode is less than each of the cycles C1 to C2 and C7 to C8 in the period P1 of the buck mode or the period P3 of the boost mode. That is to say, a generation frequency of the frequency signal CLK in the period P2 is greater than a switching frequency of the frequency signal CLK in the period P1 or P3, which may be, for example, twice the frequency, so as to improve accuracy of the output voltage VOUT in the buck-boost mode.

In the initial first cycle C1, the memory unit RAM stores a preset value (i.e., [X, Y]=[0,0]) in a field R_C0 shown in FIG. 5. In the first cycle C1, the operation mode of the current cycle is the buck mode, so the mode switching signal value Q0 of the mode switching signal MS of the current cycle is 0. The mode switching signal MS of the previous cycle (hereinafter referred to as a mode switching signal MS− of the previous cycle) is defaulted to be in the buck mode, so the mode switching signal value Q1 of the mode switching signal MS− of the previous cycle is 0. The switch control signal SWB is a modulation signal (which may be, for example, the modulation signal PWM shown in FIG. 2). The switch control signal SWC is a long-off signal and has a logic low level. In this embodiment, the slope compensation circuit 122 shown in FIG. 2 selects the input voltage VIN based on the buck mode to generate the slope compensation signal Vramp according to the input voltage VIN.

At time t1, a voltage value of the switch control signal SWB is switched from a logic high level to a logic low level, thereby generating the falling edge. The sample circuit 312 is triggered according to the falling edge of the switch control signal SWB. The sample circuit 312 performs the sampling operation on the slope compensation signal Vramp to provide a sample value VRS1, and the comparison circuit 313 compares the sample value VRS1 with the reference value of the reference signal VTH to generate a comparison result of CMP=1. Since the current cycle is in the buck mode, and the sample value VRS1 is greater than the reference value of the reference signal VTH, a value of the comparison result of CMP=1 is stored in the first value X, so that X=1.

Based on the excitation table shown in FIG. 5, the logic control unit LCU substitutes the first value of X=1 of the comparison result CMP into the corresponding value (that is, X=0 is updated to X=1) in the field R_C0. The logic control unit LCU maintains a corresponding second value of Y=0 in the field R_C0. Since the mode switching signal values Q1 and Q0 are 0 and 0 respectively, before an end of the first cycle C1, the memory unit RAM stores multiple corresponding values (i.e., [X, Y, MS−, MS]=[1,0,0,0]) in a row R_C1 shown in FIG. 5.

Based on the excitation table shown in FIG. 5, a value of Mode=0 of the corresponding mode switching signal MS in the row R_C1 output by the logic control unit LCU is used as the mode switching signal MS of the next cycle (hereinafter referred to as a mode switching signal MS+ of the next cycle), so that the operation mode of the next cycle is still the buck mode.

In the second cycle C2, the operation mode of the current cycle is the buck mode, so the mode switching signal value Q0 of the mode switching signal MS of the current cycle is 0. The operation mode of the previous cycle is the buck mode, so the mode switching signal value Q1 of the mode switching signal MS− of the previous cycle (i.e., the first cycle C1) is 0. The switch control signal SWB is the modulation signal and has a shorter pulse width than the first cycle C1. The switch control signal SWB is the long-off signal and has the logic low level. In this embodiment, the slope compensation circuit 122 shown in FIG. 2 selects the input voltage VIN based on the buck mode to generate the slope compensation signal Vramp according to the input voltage VIN.

At time t2, the switch control signal SWB generates the falling edge to trigger the sample circuit 312. The sample circuit 312 performs the sampling operation on the slope compensation signal Vramp to provide a sample value VRS2, and the comparison circuit 313 compares the sample value VRS2 with the reference value of the reference signal VTH to generate the comparison result CMP. In the buck mode, since the sample value VRS2 is less than the reference value of the reference signal VTH, the first value X of the comparison result CMP is 0.

Based on the excitation table shown in FIG. 5, the logic control unit LCU substitutes the first value of X=0 of the comparison result CMP into the corresponding first value (that is, X=1 is updated to X=0) in the row R_C1. The logic control unit LCU maintains the corresponding second value of Y=0 in the row R_C1. Since the mode switching signal values Q1 and Q0 are 0 and 0 respectively, before an end of the second cycle C2, the memory unit RAM stores multiple corresponding values (i.e., [X, Y, MS−, MS]=[0,0,0,0]) in a row R_C2 shown in FIG. 5.

Based on the excitation table shown in FIG. 5, a corresponding mode switching signal value of Mode=1 in the row R_C2 output by the logic control unit LCU is used as the mode switching signal MS+ of the next cycle, so that the operation mode of the next cycle is switched to the boost mode.

In the third cycle C3, the operation mode of the current cycle is the boost mode, so the mode switching signal value Q0 of the mode switching signal MS of the current cycle is 1. The operation mode of the previous cycle is the buck mode, so the mode switching signal value Q1 of the mode switching signal MS− of the previous cycle (i.e., the second cycle C2) is 0. The switch control signal SWB is the long-off signal and has the logic low level. The switch control signal SWC is the modulation signal (which may be, for example, PWM shown in FIG. 2). In this embodiment, the slope compensation circuit 122 shown in FIG. 2 selects the output voltage VOUT based on the boost mode to generate the slope compensation signal Vramp according to the output voltage VOUT.

At time t3, the switch control signal SWC generates the falling edge to trigger the sample circuit 312. The sample circuit 312 performs the sampling operation on the slope compensation signal Vramp to provide a sample value VRS3, and the comparison circuit 313 compares the sample value VRS3 with the reference value of the reference signal VTH to generate the comparison result CMP. In the boost mode, since the sample value VRS3 is less than the reference value of the reference signal VTH, the second value Y of the comparison result CMP is 0.