The plurality of lower option pads 230 may be disposed to be spaced apart from the pattern routing region PRR of the package substrate 100 in the second horizontal direction (Y direction). Since the plurality of lower option pads 230 are not directly connected to the power pad 152 or the ground pad 154, space utilization of the package substrate 100 may be increased through the pattern routing region PRR.

In example embodiments, the second semiconductor chip 300 may be stacked on the first semiconductor chip 200. For example, the first semiconductor chip 200 may be between the package substrate 100 and the second semiconductor chip 300. The first and second semiconductor chips 200 and 300 may be sequentially stacked in a stepped shape on the first surface 102 of the package substrate 100. For example, the stepped shape of the first and second semiconductor chips 200 and 300 may extend in the second horizontal direction (Y direction). The second semiconductor chip 300 may have a second upper surface 302 and a second lower surface 304 opposite to the second upper surface 302.

The second semiconductor chip 300 may include at least one first upper chip pad 310, at least one second upper chip pad 320, and a plurality of upper option pads 330 that are arranged to be spaced apart from each other in the first horizontal direction (X direction). The first upper chip pad 310, the second upper chip pad 320, and the plurality of upper option pads 330 may be exposed from the second upper surface 302 of the second semiconductor chip 300. That is, the first upper chip pad 310, the second upper chip pad 320, and the plurality of upper option pads 330 may be free of the second upper surface 302 of the second semiconductor chip 300 thereon.

The first upper chip pad 310 may be disposed to be spaced apart from the first lower chip pad 210 in the second horizontal direction (Y direction). The first upper chip pad 310 may be provided on a first extension line that extends along the first lower chip pad 210 and the power pad 152 in the second horizontal direction (Y direction). The first upper chip pad 310 may be electrically connected to the power pad 152 through the plurality of connection wires 400. The first upper chip pad 310 may receive the power signal from the power pad 152.

The second upper chip pad 320 may be disposed to be spaced apart from the second lower chip pad 220 in the second horizontal direction (Y direction). The second upper chip pad 320 may be provided on a second extension line that extends along the second lower chip pad 220 and the ground pad 154 in the second horizontal direction (Y direction). The second upper chip pad 320 may be electrically connected to the ground pad 154 through the plurality of the connection wires 400. The second upper chip pad 320 may receive the ground signal from the ground pad 154.

The plurality of upper option pads 330 may be disposed to be spaced apart from the first and second upper chip pads 310 and 320 in the first horizontal direction (X direction). The plurality of upper option pads 330 may be spaced apart from the plurality of lower option pads 230 in the second horizontal direction (Y direction). The plurality of upper option pads 330 may receive at least one of the power signal, the ground signal, or the data signal from the package substrate 100.

The plurality of upper option pads 330 may be disposed to be spaced apart from each other in the first horizontal direction (X direction). The plurality of upper option pads 330 may be spaced apart from each other by a second distance L2 (also referred to as a second interval L2) (e.g., see FIG. 3). That is, the plurality of upper option pads 330 may be spaced apart at a second interval L2 in the first horizontal direction (X direction). For example, the second distance L2 (i.e., second interval L2) may be within a range of 50 μm to 80 μm. The number of the upper option pads 330 may be within a range of 4 to 8.

The plurality of upper option pads 330 may be disposed to be spaced apart from the pattern routing region PRR of the package substrate 100 in the second horizontal direction (Y direction). Since the plurality of upper option pads 330 are not directly connected to the power pad 152 or the ground pad 154, space utilization of the package substrate 100 may be increased through the pattern routing region PRR. The package substrate 100 may include additional upper conductive patterns 130 that are provided in the pattern routing region PRR to improve signal characteristics.

In example embodiments, the plurality of connection wires 400 may electrically connect the package substrate 100 and the first and second semiconductor chips 200 and 300 to each other. The plurality of connection wires 400 may include first, second and third conductive wires 410, 420, and 430.

The first and second conductive wires 410 and 420 may extend in the second horizontal direction (Y direction), respectively. The third conductive wires 430 may extend in a diagonal direction between the first and second horizontal directions (X direction and Y direction). The third conductive wires 430 may extend to cross the first and second conductive wires 410 and 420. The diagonal direction may be within a range of 0 degrees to 90 degrees from the first horizontal direction (X direction).

The first conductive wires 410 may transmit the power signal or the ground signal between the package substrate 100 and the first semiconductor chip 200. The first conductive wires 410 may electrically connect the power pad 152 and the ground pad 154 to the first and second lower chip pads 210 and 220, respectively. The first conductive wires 410 may transmit the power signal from the power pad 152 to the first lower chip pad 210. The first conductive wires 410 may transmit the ground signal from the ground pad 154 to the second lower chip pad 220.

The second conductive wires 420 may transmit the power signal or the ground signal between the first and second semiconductor chips 200 and 300. The second conductive wires 420 may electrically connect the first and second lower chip pads 210 and 220 to the first and second upper chip pads 310 and 320, respectively. The second conductive wires 420 may transmit the power signal from the first lower chip pad 210 to the first upper chip pad 310. The second conductive wires 420 may transmit the ground signal from the second lower chip pad 220 to the second upper chip pad 320.

The third conductive wires 430 may electrically connect the first upper chip pad 310 or the second upper chip pad 320 to at least one of the lower option pads 230. The at least one of the lower option pads 230 may receive the power signal or the ground signal from the power pad 152 or the ground pad 154 through the first to third conductive wires 410, 420, and 430