224 triggered by the assertion of the data modification complete signal mCmplt then writes the data bits of the modified data word back to the bit lines 216 to be stored at the accessed data word location in the memory array 214. It will be noted that because of read multiplexing circuitry, not explicitly shown, the data sensing circuit 218 at this point in time has been disconnected from the bit lines and the SAEN signal is no longer asserted. Following completion of the data write, the word line signal is deasserted. Timing of completion of the write operation can be controlled based on a dummy write operation performed by the SRAM 212. This ensures that the data bits of the modified data word remain on the bit lines 216 for a sufficient amount of time to ensure successful write back into the memory cells M.

Reference is now made to FIG. 6 which shows a timing diagram for operation of the circuit 210. At time t1, the SRAM 212 is enabled for operation and the bit lines 216 are precharged to a precharge voltage level (shown here, by example only, at Vdd). At time t2, the memory address (Address) is applied and the clock signal CLK pulses. The Address is decoded by the SRAM 212 and the word line (WL) coupled to the data word location (dw loc) corresponding to the decoded Address is asserted logic high at time t3. In response to the asserted word line signal and the logic state of the stored data, the voltage on the bit lines begins to discharge from Vdd. At time t4, the sense amplifier enable (SAEN) signal is asserted logic high to enable operation of the sense amplifiers within the data sensing circuit 218. The sense amplifiers respond at time t5 to sense the voltage on the bit lines 216 and drive corresponding output signals (SA out) from the data sensing circuit 218 to logic high or logic low levels dependent on the logic state of the bits of the data word stored in the accessed data word location. Thus, the data word has been read (step 1) from the memory array 214 and the output of the data sensing circuit 218 now reflects the count value (Count). The data latch circuit 220 latches the read data word from the output of the data sensing circuit 218 at time t6, and thus the latched data also reflects the count value (Count). The data modification circuit 222 then performs the mathematical modify operation (step 2) at time t7, which in this example case is an increment by one (+1) operation, and the output modified data from the data modification circuit 222 at time t8 reflects the incremented count value (Count+1). Simultaneously, the value dependent delay circuit 221 processes the binary count value (Count) to determine a dynamically variable duration of a timing delay (that duration being dependent on the binary count value) after the expiry of which the data modification complete signal mCmplt is asserted. In response to assertion of data modification complete signal mCmplt, the data write circuit 124 then applies the data bits of the modified data word back to the bit lines 216. Because the signal on the word line (WL) remains asserted logic high, the modified data word is then written (step 3) at time t9 for storage at the accessed data word location in the memory array 214. Following completion of the data write operation at time t10, a reset is performed at time t11 and the word line (WL) is deasserted logic low.

It will be noted that the duration of the self-time delay for controlling the assertion of the wordline (i.e., the time between time t3 and time t11) in this implementation is dynamically variable (and dependent on the binary count value read from the memory). The portion of the self-time delay for the read of the memory (from time t3 to time t6—step 1) is controlled by the fixed duration of time associated with performing the dummy read operation, assertion of the sense amp enable (SAEN) signal and latching of the read data by the data latch circuit. The portion of the self-time delay for the increment operation (from time t6 to time t8-step 2), however, is dynamically variable (not fixed; compare to FIG. 4) and is controlled by the dynamically variable duration of a delay time for assertion of the data modification complete signal mCmplt that is dependent on the binary count value of the latched data. Furthermore, the portion of the self-time delay for the write of the memory (from time t8 to time t11—step 3) is controlled by the fixed duration of time associated with performing the dummy write operation and writing the data back to the memory.

The foregoing may be better understood by the consideration of some examples.

First, assume that the binary count value stored in the memory is <00000001> (or decimal 1). The binary count value <00000001> read from the memory is latched by the latch circuit. The increment operation performed by the data modification circuit 222 is an increment by one (+1) operation to generate a binary modified count value <00000010> (decimal 2). Note here that only the first and second bits of the n=8-bit data word change logic state to increment from decimal 1 to decimal 2. Once the data modification circuit 222 has completed changing those two bits, the incremented count value (Count+1) is ready at that point in time to be written back to the memory. There is no need to further delay triggering the write operation while the remaining bits are processed because their individual bit values will not change in the increment by one operation. The value dependent delay circuit 221, based on the processing of the binary count value (Count)<00000001>, determines the dynamically variable duration of the timing delay needed to process the two least significant bits by the data modification circuit 222, and then asserts the data modification complete signal mCmplt when processing of those least significant bits has been completed. FIG. 7A illustrates the variability of the portion of the self-time delay for the increment operation (from time t6 to time t8) in this example where a two bit delay for processing only the two least significant bits by the data modification circuit 222 is applied by the value dependent delay circuit before asserting the data modification complete signal mCmplt.

Now assume that the binary count value stored in the memory is <00010001> (or decimal 17). The binary count value <00010001> read from the memory is latched by the latch circuit. The increment operation performed by the data modification circuit 222 is an increment by one (+1) operation to generate a binary modified count value <00010010> (decimal 18). Note here that only the first and second bits of the n=8-bit data word change logic state to increment from decimal 17 to decimal 18. Once the data modification circuit 222 has completed changing those two bits, the incremented count value (Count+1) is ready to be written back to the memory. There is no need to further delay triggering the write operation while the remaining bits are processed because their individual bit values will not change in the increment by one operation. The value dependent delay circuit 221, based on the processing of the binary count value (Count) <00010001>, determines the dynamically variable duration of the timing delay needed to process the two least significant bits by the data modification circuit 222, and then asserts the data modification complete signal mCmplt when processing of those least significant bits has been completed. FIG. 7A illustrates the variability of the portion of the self-time delay for the increment operation (from time t6 to time t8) in this example where a two bit delay for processing only the two least significant bits by the data modification circuit 222 is applied by the value dependent delay circuit before asserting the data modification complete signal mCmplt.

For another example, assume that the binary count value stored in the memory is <00001111> (or decimal 15). The binary count value <00001111> read from the memory is latched by the latch circuit. The increment operation performed by the data modification circuit 222 is an increment by one (+1) operation to generate a binary modified count value <00010000> (decimal 16). Note here that the first through fifth bits of the n=8-bit data word change logic state to increment from decimal 15 to decimal 16. Once the data modification circuit 222 has completed changing those five bits, the incremented count value (Count+1) is ready to be written back to the memory. There is no need to further delay triggering the write operation while the remaining bits are processed because their individual bit values will not change in the increment by one operation. The value dependent delay circuit 221, based on the processing of the binary count value (Count) <00001111>, determines the dynamically variable duration of the timing delay needed to process the five least significant bits by the data modification circuit 222, and then asserts the data modification complete signal mCmplt when processing of those least significant bits has been completed. FIG. 7B illustrates the variability of the portion of the self-time delay for the increment operation (from time t6 to time t8) in this example where a five bit delay for processing the two least significant bits by the data modification circuit 222 is applied by the value dependent delay circuit before asserting the data modification complete signal mCmplt.

To contrast this dynamically variable duration self-time delay of the circuit 210 (FIG. 5) to the fixed duration self-time delay of the circuit 110 (FIG. 3), consideration is made of the previous example where the binary count value stored in the memory is <00001111> (or decimal 15). The binary count value <00001111> read from the memory is latched by the latch circuit. The increment operation performed by the data modification circuit 122 is an increment by one (+1) operation to generate a binary modified count value <00010000>. As discussed above, the dummy adder circuit (triggered by latching of the read data word) would perform a sequential addition operation over n=8 bits and then assert the data modification complete signal mCmplt only after all eight bits are processed and the adder circuit overflows (see, FIG. 4). So, the circuit 110 would implement a fixed duration delay of eight bits while the circuit 210 would implement a dynamically variable duration delay of just five bits for the same binary count value.

Likewise, assume that the binary count value stored in the memory is <00000001> (or decimal 1). The binary count value <00000001> read from the memory is latched by the latch circuit. The increment operation performed by the data modification circuit 122 is an increment by one (+1) operation to generate a binary modified count value <00000010>. Again, the dummy adder circuit (triggered by latching of the read data word) would perform a sequential addition operation over n=8 bits and then assert the data modification complete signal mCmplt only after all eight bits are processed and the adder circuit overflows (see, FIG. 4). So, the circuit 110 would implement a fixed duration delay of eight bits while the circuit 210 would implement a dynamically variable duration delay of just two bits for the same binary count value.

The following table shows a comparison of the increment self-time delay portion for the circuits 110 and 210 for a number of example decimal values read from the memory and latched by the latch circuit (with the performance of an increment by one operation):

Decimal
Binary value (8-bit)
Increment self-time delay (bit count)

value (latched)
7
6
5
4
3
2
1
0
Circuit 110
Circuit 210
Gain

0
0
0
0
0
0
0
0
0
8
1
7

1
0
0
0
0
0
0
0
1
8
2
6

2
0
0
0
0
0
0
1
0
8
1
7

. . .

10
0
0
0
0
1
0
1
0
8
1
7

. . .

15
0
0
0
0
1
1
1
1
8
5
3

. . .

23
0
0
0
1
0
1
1
1
8
4
4

. . .

67
0
1
0
0
0
0
1
1
8
3
5

. . .

103
0
1
1
0
0
1
1
1
8
4
4

. . .

124
0
1
1
1
1
1
0
0
8
1
7

. . .

127
0
1
1
1
1
1
1
1
8
8
0

. . .

219
1
1
0
1
1
0
1
1
8
3
5

. . .

The bit delay for the circuits 110 and 210 is provided and the last column shows the gain in performance (i.e., the shortening of the self-time delay duration) for the circuit 210 in comparison to the circuit 110 for read-modify-write processing a same binary count value. For the circuit 210: the maximum increment self-time delay is an 8 bit delay; the minimum increment self-time delay is a 1 bit delay; and the average increment self-time delay is approximately a 2 bit delay (i.e., 1.97). This is contrasted to the circuit 110 where the maximum, minimum and average increment self-time delay is an 8 bit delay.

It is important to recognize that the value dependent delay circuit 221 advantageously controls the timing for assertion of the mCmplt signal in a dynamic manner that is dependent on the value of the latched data (i.e., on the read Count value) so as to provide for an improvement in, and dynamic control over, the duration of the step 2 mathematically modify portion of the single clock cycle read-modify-write operation. In comparison to fixed delay circuit implementations, like that shown in FIG. 3, there is a noted gain in performance due to the dynamic control exercised over the step 2 duration.

Reference is now made to FIG. 8 which shows a block diagram for an embodiment of the value dependent delay circuit 221. A latching end detect circuit 232 is coupled to the data latch circuit 220. The latching end detect circuit 232 operates to detect when the least significant bit of the count value data sensed by the sense amplifier SA has been successfully latched by the data latch circuit 220. In response to this detection, the latching end detect circuit 232 asserts an end signal END. The end signal END is applied to the input of an n-tap delay line 233. A different time delayed version of the end signal END is output from each tap of the n-tap delay line. A decoder circuit 235 receives the read count value from the data latch circuit 220 and decodes that count value to drive selection by a multiplexing circuit 237 of the delayed end signal END for output as the data modification complete signal mCmplt. The decoder circuit 235 correlates each binary count value with a specific bit delay associated with one of the n-taps of the delay line 233. For example, for the example noted above where the binary count value stored in the memory is <00000001> (or decimal 1), there needs to be a two bit delay, so the decoder 235 would decode <00000001> to control multiplexer 237 selection of the second tap of the n-taps of the delay line 233 where the end signal END is delayed by two bits for the assertion of the data modification complete signal mCmplt. Similarly, for the example noted above where the binary count value stored in the memory is <00001111> (or decimal 15), there needs to be a five bit delay, so the decoder 235 would decode <00001111> to control multiplexer 237 selection of the fifth tap of the n-taps of the delay line 233 where the end signal END is delayed by five bits for the assertion of the data modification complete signal mCmplt.

FIG. 9 is a block diagram of a portion of the memory 212. The memory array 214 includes a plurality of SRAM cells (M) (for example, of the 6T or 8T type as is well known in the art). The cells M are arranged in an array including j rows and k columns. The cells M in each row are coupled to a corresponding word line (WL), and the cells in each column are coupled to at least one corresponding bit line (BL). In an implementation using the 6T type SRAM circuit, a pair of complementary bit lines are present and are used in connection with both writing data to and reading data from the memory cell of a column. In an implementation using the 8T type SRAM circuit, a pair of complementary write bit lines and a single read bit line are present, with the write bit lines used in connection with writing data to the memory cell and the read bit line used in connection with reading data from the memory cell. The memory cells M of each row at a given memory address location form a bin which stores a data word corresponding to a count value (Count) of the histogram. In the illustrated implementation, the bit stored in the memory cell of column 0 is the least significant bit (LSB) of the count value and the bit stored in the memory cell of column k−1 is the most significant bit (MSB) of the count value.

The SRAM 212 further includes a row decoder circuit that is configured to receive the memory address (Address). The row decoder circuit responds thereto by decoding the received memory address and selectively actuating one word line (WL) which corresponds to the decoded memory address in the memory. Details of the circuitry for the row decoder circuit are not provided as such circuitry is well known to those skilled in the art.

The SRAM 212 further includes a control circuit that is configured to control operation of the memory circuitry to perform read and write operations. Details of the circuitry for the control circuit are not provided as such circuitry is well known to those skilled in the art.

Data input/output (I/O) circuitry 320 for the SRAM 212 includes an I/O circuit 322 for each column of the memory. Each I/O circuit 322 includes a sense amplifier SA circuit connected to the bit line BL of the corresponding column. The sense amplifier SA circuit functions, in response to assertion of a sense amplifier enable SAEN signal generated by the control circuit, to drive an output signal (SA out) to a supply rail (Vdd or ground, for example) as a function of the logic state of the data bit stored in the memory cell M of the row which is selected by the actuation of the word line WL. The plurality of sense amplifier SA circuits in the data input/output (I/O) circuitry 320 form the data sensing circuit 218 (see, FIG. 5). The logic state of the data bit output by the sense amplifier SA circuit in the SA out signal is then latched by a bit latch circuit 324. The plurality of bit latch circuits 324 form the data latch circuit 220 (see, FIG. 5). In connection with a conventional data read mode of operation for the SRAM