112A to 112N can be grouped as memory pages or blocks that can refer to a unit of the memory component 112 used to store data. In some examples, the memory cells of the memory components 112A to 112N can be grouped into a set of different zones or virtual blocks (VB) of equal or unequal size used to store data for corresponding applications. In such cases, each application can store data in an associated zone of the set of different zones.

The memory sub-system controller 115 can communicate with the memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory components 112A to 112N and other such operations. The memory sub-system controller 115 can communicate with the memory components 112A to 112N to perform various memory management operations, such as different scan rates, different scan frequencies, different wear leveling, different read disturb management, different near miss ECC operations, different defragmentation operations, and/or different dynamic data refresh.

The memory sub-system controller 115 can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The memory sub-system controller 115 can be a microcontroller, special-purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor. The memory sub-system controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, and so forth. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the example memory sub-system 110 in FIG. 1 has been illustrated as including the memory sub-system controller 115, in another embodiment of the present disclosure, a memory sub-system 110 may not include a memory sub-system controller 115, and can instead rely upon external control (e.g., provided by an external host, or by a processor 117 or controller separate from the memory sub-system 110).

In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. In some examples, the commands or operations received from the host system 120 can specify regression levels and/or regression thresholds for the memory components 112A to 112N. In some examples, the memory sub-system controller 115 can provide or transmit commands or operations to the host system 120 specifying regression levels and/or regression thresholds for collections of LBAs associated with FBO entries stored in the memory components 112A to 112N.

The memory sub-system controller 115 can be responsible for other memory management operations, such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system 120 into command instructions to access the memory components 112A to 112N as well as convert responses associated with the memory components 112A to 112N into information for the host system 120.

The memory sub-system 110 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM or other temporary storage location or device) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory sub-system controller 115 and decode the address to access the memory components 112A to 112N.

The memory devices can be raw memory devices (e.g., NAND), which are managed externally, for example, by an external controller (e.g., memory sub-system controller 115). The memory devices can be managed memory devices (e.g., managed NAND), which is a raw memory device combined with a local embedded controller (e.g., local media controllers) for memory management within the same memory device package. Any one of the memory components 112A to 112N can include a media controller (e.g., media controller 113A and media controller 113N) to manage the memory cells of the memory component (e.g., to perform one or more memory management operations), to communicate with the memory sub-system controller 115, and to execute memory requests (e.g., read or write) received from the memory sub-system controller 115.

The memory sub-system controller 115 can include a media operations manager 122. The media operations manager 122 can be configured to selectively and adaptively perform different memory management operations (e.g., defragmentation operations) on the memory components 112A to 112N on the basis of the regression levels of the FBO entries associated with the respective memory components 112A to 112N. For example, the media operations manager 122 can receive an FBO entry from the host system 120 which identifies LBAs of an individual file or collection of files. Using the FBO entry, the memory sub-system controller 115 can determine a regression level of the individual file, such as by computing how many read operations need to be performed to retrieve the data from the memory relative to a maximum number of read operations that may need to be performed. The regression level can be communicated back to the host system 120 to determine whether there is a need to perform one or more defragmentation operations. In some cases, the defragmentation operations are selectively performed on the basis of the type of memory used to store the data for the FBO entry. Namely, if the data is stored in the TLC or SLC memory type, the regression level can be communicated back to the host as being lower than the actual regression level to prevent performing defragmentation operations. If the data is stored in the QLC memory type, the regression level can be communicated back to the host as being the actual regression level to cause performing defragmentation operations.

In some examples, the memory sub-system controller 115 compares the regression level of the FBO entry to a regression level threshold. The memory sub-system controller 115 can determine that the regression level transgresses the threshold. On the basis of whether the regression level transgresses the threshold, the memory sub-system controller 115 can perform one or more data defragmentation operations. The data defragmentation operations can include rearranging how physical addresses mapped to the LBAs of the FBO entry are read from one or more of the memory components 112A-N. The data defragmentation operations can include copying data of the FBO entry that is distributed across many VBs on the memory components 112A-N into fewer VBs or into a single VB to reduce the number of reads that are needed to be performed to read the data corresponding to the FBO entry. In some cases, the data is only copied into a new VB if the quantity of available free VBs is below a threshold quantity. If not, the memory sub-system controller 115 can delay copying the data into the new VB until the number of available free VBs transgresses the threshold quantity.

Depending on the embodiment, the media operations manager 122 can comprise logic (e.g., a set of transitory or non-transitory machine instructions, such as firmware) or one or more components that causes the media operations manager 122 to perform operations described herein. The media operations manager 122 can comprise a tangible or non-tangible unit capable of performing operations described herein. Further details with regards to the operations of the media operations manager 122 are described below.

FIG. 2 is a block diagram of an example media operations manager 200, in accordance with some implementations of the present disclosure. As illustrated, the media operations manager 122 includes regression computation module 220, a page table 230, and a defragmentation operations module 240. For some embodiments, the media operations manager 122 can differ in components or arrangement (e.g., less or more components) from what is illustrated in FIG. 2.

The media operations manager 200 receives from the host system 120 an FBO entry that lists a plurality of LBAs of an individual file. In response to receiving the FBO entry, the regression computation module 220 accesses the page table 230 to identify a list of physical addresses that are mapped to each respective LBA in the FBO entry. The regression computation module 220 computes a regression level for the FBO entry by analyzing the arrangement of the identified physical addresses. Namely, the regression computation module 220 computes how many total read operations need to be performed to read the data from all of the identified physical addresses relative to the maximum amount of read operations that need to be performed.

Specifically, the regression computation module 220 can determine a worst-case-scenario for fragmentation of the data corresponding to the FBO entry. This can be the case when each LBA of the FBO is associated with a physical address (e.g., page) that is in a different VB. Namely, the data of the FBO entry can be stored across a quantity of VBs corresponding to the number of LBAs in the FBO. In such worst-case-scenarios, the memory sub-system controller 115 may need to perform a maximum number of read operations corresponding to the number of LBAs in the FBO to obtain all the data for the FBO entry. For example, if the FBO entry includes 10 LBAs, the worst-case-scenario for reading the data corresponding to the FBO entry is performing a maximum of 10 reads to access 10 different VBs from the memory components 112A-N.

The regression computation module 220 can compute the total actual number of read operations needed to be performed to read the data corresponding to the FBO entry by determining how many VBs are used to store the data corresponding to the FBO entry. In some cases, the regression computation module 220 can traverse the identified list of physical addresses corresponding to the plurality of LBAs. In response to determining that a first LBA corresponds to a first physical address that is not adjacent to a second physical address corresponding to a second LBA that is sequentially adjacent to the first LBA, the regression computation module 220 can increment a counter representing the number of reads. This can be because reading the non-adjacent physical address can require an additional read to be performed. In this way, the regression computation module 220 identifies pairs of adjacent LBAs in the page table 230 corresponding to the FBO entry that corresponds to non-adjacent physical addresses. The regression computation module 220 computes the number of read operations that need to be performed to read the data corresponding to the FBO entry (e.g., the first quantity) as a function of a quantity of the identified plurality of adjacent pairs. The regression computation module 220 can compute the regression level for the FBO as a ratio of the first quantity of read operations to the maximum number of read operations and can provide this regression level back to the host system 120.

FIG. 3 is a block diagram of an example page table 300, in accordance with some implementations of the present disclosure. The regression computation module 220 can communicate with the page table 230 to obtain the page table 300 corresponding to the FBO entry received from the host system 120. The page table 300 can include a list of LBAs 310 corresponding to the FBO entry and their respective physical addresses 320. The regression computation module 220 can determine that the first LBA1 312 is adjacent to the second LBA2 314. The regression computation module 220 can determine that the first physical address (PA1) 322 corresponding to the first LBA1 312 is adjacent to the second physical address (PA2) 324 corresponding to the second LBA2 314. In such cases, the regression computation module 220 determines that the same read operation can be performed to obtain the data for the first LBA1 312 and the second LBA2 314.

The regression computation module 220 can determine that a third LBA4 316 is adjacent to the fourth LBA5 318. The regression computation module 220 can determine that the third physical address (PA8) 326 corresponding to the third LBA 4 316 is not adjacent to the fourth physical address PA10 328 corresponding to the fourth LBA5 318. In such cases, the regression computation module 220 determines that the two read operations need to be performed to obtain the data for the third LBA4 316 and the fourth LBA5 318. In response, the regression computation module 220 updates or increments a counter of the number of reads that need to be performed to obtain the data for the FBO entry. After completely traversing or processing the LBAs 310 for the FBO entry, the regression computation module 220 uses the current value of the counter as the first quantity of reads that need to be performed to read the data corresponding to the FBO entry. The regression computation module 220 computes a regression level for the FBO entry as a function of the first quantity and the worst-case-scenario maximum number of read operations that need to be performed to read the data corresponding to the FBO entry. The regression computation module 220 can return this regression level to the host system 120.

In some cases, the regression computation module 220 provides the regression level to the defragmentation operations module 240. The defragmentation operations module 240 can compare the regression level to a regression level threshold (which can be provided by the host system 120). The defragmentation operations module 240 can perform one or more defragmentation operations based on the current regression level of the data corresponding to the FBO entry. In some cases, the defragmentation operations module 240 performs one or more data defragmentation operations in response to determining that the regression level of the file transgresses the threshold regression level.

For example, the defragmentation operations module 240 can modify a read order for the physical addresses of the set of memory components associated with the plurality of LBAs as one of the defragmentation operations. Specifically, the defragmentation operations module 240 identifies a first set of physical addresses associated with a first set of the plurality of LBAs that corresponds to a same channel of the set of memory components 112A-N as a second set of physical addresses associated with a second set of the plurality of LBAs, the first set of physical addresses corresponding to a first chip enable and the second set of physical addresses corresponding to a second chip enable on the same channel. The defragmentation operations module 240 instructs the same channel of the set of memory components 112A-N to interleave reading the second set of physical addresses based on the second chip enable with transferring data read from the first set of physical addresses to the memory sub-system controller 115.

In some cases, the defragmentation operations module 240 instructs the same channel of the set of memory components 112A-N to read the data from the first set of physical addresses based on the first chip enable. The defragmentation operations module 240 after the data is read from the first set of physical addresses and while the data is transferred from the set of memory components to the memory sub-system controller 115, instructs the same channel of the set of memory components 112A-N to read data from the second set of physical addresses based on the second chip enable. A last LBA in the first set of the plurality of LBAs can be non-adjacent to a first LBA in the second set of the plurality of LBAs.

FIG. 4 is a block diagram 400 of an example set of channels for multiple memory dies, in accordance with some implementations of the present disclosure. Each memory die shown in FIG. 4 can correspond to a different one of the set of memory components 112A-N. In some examples, the defragmentation operations module 240 can virtually defragment the data associated with the FBO entry by controlling the order at which the physical addresses corresponding to the LBAs are read from the memory components 112A-N. So rather than reading the second physical address 324 corresponding to the second LBA 314 after reading the data corresponding to the first physical address 322, the defragmentation operations module 240 can read the data from the third physical address 326 after reading the data from the first physical address 322. This can be performed if the defragmentation operations module 240 determines that the third physical address 326 is in a same channel as the first physical address 322 and on a different memory component 112A-N. Namely, the defragmentation operations module 240 can determine that the third physical address 326 is on the same channel as the first physical address 322 and not on the same channel as the second physical address 324. In such cases, the defragmentation operations module 240 can interleave reading the data from the third physical address 326 with reading the data from the first physical address 322.

Specifically, the defragmentation operations module 240 can determine that the third physical address 326 corresponding to the third LBA 316 is not adjacent to the fourth physical address 328 corresponding to the fourth LBA 318. In addition, the defragmentation operations module 240 can determine that the third physical address 326 and the fourth physical address 328 correspond to different memory components 112A-N of the same channel. Specifically, the defragmentation operations module 240 can determine that the third physical address 326 corresponds to a first chip enable 412 of a first memory component 112A and the fourth physical address 328 corresponds to a second chip enable 414 of a second memory component 112N. The defragmentation operations module 240 can also determine that the first and second memory components 112A and 112N are on a same channel 410 of the memory sub-system.

In such cases, the defragmentation operations module 240 can interleave reading the data from the third physical address 326 with the data from the fourth physical address 328. This can reduce the amount of time it takes to retrieve and read the data from the same channel 410. Namely, the defragmentation operations module 240 can instruct the first memory component 112A (using the first chip enable 412) to read the data corresponding to the third physical address 326. After the data is read from the third physical address 326 and while the data is being transferred to the memory sub-system controller 115, the memory sub-system controller 115 instructs the same channel 410 to read the data corresponding to the fourth physical address 328 from the second memory component 112N (using the second chip enable 414). In this way, the memory sub-system controller 115 does not have to wait for the transfer of the data corresponding to the third physical address 326 to be completed before the data corresponding to the fourth physical address 328 is initiated which reduces the overall amount of lag experienced by the memory sub-system controller 115.

The defragmentation operations module 240 can perform similar operations to interleave data read from a second channel 420 that includes memory components 112C and 112D (not shown) corresponding to other chip enables 422 and 424. This reduces the overall amount of lag experienced by the memory sub-system controller 115 which virtually defragments the data.

In some examples, the defragmentation operations module 240 (or host system 120) can determine that the regression level of the FBO entry transgresses a regression level threshold. The defragmentation operations module 240 can determine or receive an instruction from the host system 120 to actively defragment the data corresponding to the FBO entry. To do so, the defragmentation operations module 240 can determine how many free VBs are currently available. The defragmentation operations module 240 can determine that the number of free VBs that are available transgresses a threshold. The defragmentation operations module 240 can compute how many VBs are needed to defragment or store all of the data corresponding to the FBO entry. The defragmentation operations module 240 can decrement the needed number of VBs from the current available number of free VBs. The defragmentation operations module 240 can determine whether the decremented number still transgresses the threshold. If so, the defragmentation operations module 240 can copy all of the data corresponding to the FBO entry into the free VBs and update the page table 300. In some cases, the defragmentation operations module 240 can compute the minimum LBA start and maximum length of the FBO entry to determine the number of VBs needed to store the data corresponding to the FBO entry.

If the decremented number no longer transgresses the threshold, the defragmentation operations module 240