200 and isolates the stresses and strains on the epitaxial layer 214 caused by the deformation. In this way, the non-contiguous and/or isolated portions of the epitaxial layer 214 deform locally instead of transferring the stresses and strains of the deformation across the entire epitaxial layer 214, which may reduce and/or isolate cracking and/or breakage of the epitaxial layer 214 and/or the substrate 202.

In some implementations, various materials are used for the epitaxial layer 214, such as GaN, indium nitride (InN), aluminum nitride (AlN), another III-nitride (e.g., a nitride of a group III element), another III-V material, and/or the like. In some implementations, the semiconductor processing tool may form or grow the epitaxial layer 214 (and/or the portions thereof) using an MBE process, an MOCVD process, or another type of deposition process. In some implementations, the semiconductor processing tool forms or grows the epitaxial layer 214 such that the portions of the epitaxial layer 214 have the same properties and/or parameters. In some implementations, the semiconductor processing tool forms or grows the epitaxial layer 214 such that the portions of the epitaxial layer 214 have one or more different properties and/or parameters.

The properties and/or parameters for each portion of the epitaxial layer 214 may include a height (H) of the portion, a width (W) of the portion, a length of the portion, a shape of the portion, and/or another property and/or parameter. In some implementations, the height and the width of a portion of the epitaxial layer 214 may define (or may be defined by) an aspect ratio for the portion. As an example, epitaxial layer 214a may have an example width (W1) and an example height (H1) such that epitaxial layer 214a has a width-to-height aspect ratio in a range of approximately 3 to approximately 6. As another example, epitaxial layer 214a may have an example width (W2) and an example height (H2) such that epitaxial layer 214b has a width-to-height aspect ratio in a range of approximately 1 to approximately 3. As another example, epitaxial layer 214c may have an example width (W3) and an example height (H3) such that epitaxial layer 214c has a width-to-height aspect ratio in a range of approximately 0.1 to approximately 0.8.

In some implementations, a portion of the epitaxial layer 214 may be formed such that the height for the portion is greater than the width for the portion (e.g., such that the aspect ratio for the portion is greater than 1), as a portion may experience less vertical stress and strain as the width of the portion decreases. Similarly, the associated strain relief trench 212 may be formed such that the depth of the strain relief trench 212 is greater than the width for the strain relief trench 212.

As further shown in FIG. 2G, the portions of the epitaxial layers 214 may have tapered walls. In these examples, the one or more properties and/or parameters may include a wall angle (A). For example, epitaxial layer 214a may have a tapered wall angle (A1), epitaxial layer 214b may have a tapered wall angle (A2), and epitaxial layer 214c may have a tapered wall angle (A3). In some implementations, the wall angles for each portion of the epitaxial layer 214 may be the same angle. In some implementations, two or more portions of the epitaxial layer 214 may have different wall angles. An example wall angle range may include approximately 10 degrees to approximately 15 degrees past 90 degrees.

As indicated above, FIGS. 2A-2G are provided as one or more examples. Other examples may differ from what is described with regard to FIGS. 2A-2G. As an example, instead of using a photoresist layer to etch the substrate 202 to form the strain relief trenches 212, a hardmask may be used. The hardmask may be an oxide mask, such as silicon dioxide (SiO₂). A semiconductor processing tool (e.g., the deposition tool 110) may form the hardmask on the substrate 202 using a chemical vapor deposition process or a physical vapor deposition process (e.g., sputtering).

FIGS. 3A and 3B are diagrams of example strain relief trench configurations described herein. As shown in FIG. 3A, an example trench configuration 302 includes a grid pattern of perpendicular and intersecting trenches 304 (and associated epitaxial layer portions formed therein). As further shown in FIG. 3A, the spacing between parallel trenches 304 may be substantially the same. As shown in FIG. 3B, another example trench configuration 306 includes a grid pattern of perpendicular and intersecting trenches 308 (and associated epitaxial layer portions formed therein). As further shown in FIG. 3A, the spacing between subsets of the trenches 308 may be different. For example, some of the trenches 308 in the example trench configuration 306 are spaced more closely together than other trenches 308 in the example trench configuration.

As indicated above, FIGS. 3A and 3B are provided as one or more examples. Other example trench configurations may differ from what is described with regard to FIGS. 3A and 3B. For example, the any of the properties and/or parameters of strain relief trenches described above in connection with FIGS. 2A-2G (and/or the pattern of strain relief trenches), or a combination thereof, may be varied, configured, and/or adjusted for different trench configurations.

FIGS. 4A-4E are diagrams of example strain relief trench configurations described herein. In particular, FIGS. 4A-4E illustrate some examples for how different cross-sectional properties and/or parameters for strain relief trenches in a substrate may be varied or configured.

FIG. 4A illustrates a cross-sectional view of an example strain relief trench configuration 402. As shown in the example strain relief trench configuration 402, strain relief trenches may be half-circle shaped in a cross-sectional view of the strain relief trenches. FIG. 4B illustrates a cross-sectional view of an example strain relief trench configuration 404. As shown in the example strain relief trench configuration 404, strain relief trenches may be rectangle (or square) shaped in a cross-sectional view of the strain relief trenches.

FIG. 4C illustrates a cross-sectional view of an example strain relief trench configuration 406. As shown in the example strain relief trench configuration 406, strain relief trenches may be triangle shaped in a cross-sectional view of the strain relief trenches. FIG. 4D illustrates a cross-sectional view of an example strain relief trench configuration 408. As shown in the example strain relief trench configuration 508, strain relief trenches may be complex and/or non-standard shaped in a cross-sectional view of the strain relief trenches. As an example, strain relief trenches may include a mirrored triangle shape, as shown in FIG. 4D. FIG. 4E illustrates a cross-sectional view of an example strain relief trench configuration 410. As shown in the example strain relief trench configuration 410, strain relief trenches may be complex and/or non-standard shaped in a cross-sectional view of the strain relief trenches. As an example, strain relief trenches may include a mirrored triangle shape with a flat center portion, as shown in FIG. 4E.

As indicated above, FIGS. 4A-4E are provided as one or more examples. Other examples may differ from what is described with regard to FIGS. 4A-4E. For example, any of the properties and/or parameters of strain relief trenches described above in connection with FIGS. 2A-2G (and/or the pattern of strain relief trenches), or a combination thereof, may be varied, configured, and/or adjusted for different trench configurations and/or for different epitaxial layer growth directions and patterns. Moreover, strain relief trenches formed in the same substrate may be formed to have different properties and/or parameters.

FIG. 5 is a diagram of an example of degradation data 500 associated with one or more semiconductor structures (e.g., epitaxial layer 214 of FIGS. 2A-2G, semiconductor structure 600 of FIG. 6 below, and/or the like) described herein. As shown in FIG. 5, the example degradation data 500 may include information identifying degradation experienced by semiconductor structures as a function of stress time (in hours). The degradation may be an on-resistance (R_ON) degradation of a GaN HEMT.

As further shown in FIG. 5, a semiconductor structure (e.g., of a GaN HEMT) that is formed without strain relief trenches 212 experiences relatively high R_ONdegradation (e.g., 5.8×R_ONdegradation) as stress time approaches 60 hours. A semiconductor structure (e.g., of a GaN HEMT) that is formed with strain relief trenches 212 experiences lower R_ONdegradation (e.g., 1.04×R_ONdegradation) compared with the semiconductor structure that is formed without strain relief trenches 212 as stress time approaches 60 hours.

As indicated above, FIG. 5 is provided as an example. Other examples may differ from what is described with regard to FIG. 5.

FIG. 6 is an illustration of an example semiconductor structure 600 formed based on the example techniques described in connection with FIGS. 2A-2G. Example semiconductor structure 600 may be an example of an epitaxial layer that may be grown on a substrate having one or more strain relief trenches formed therein, such as the substrate 202 described above in connection with FIGS. 2A-2G.

As shown in FIG. 6, the example semiconductor structure 600 may include a plurality of layers. In some implementations, the semiconductor structure 600 may be a portion of a HEMT or another type of semiconductor device having one or more GaN layers. The plurality of layers may include a substrate 602, which may be a substrate of a wafer (e.g., wafer 200). In some implementations, the substrate 602 includes one or more strain relief trenches (e.g., strain relief trenches 212) formed therein. The substrate 602 may be an Si substrate, an SiC substrate, a sapphire substrate, or a substrate formed of another material.

As further shown in FIG. 6, a buffer layer 604 may be formed above, over, and/or on the substrate 602. The buffer layer 604 may include an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, a GaN layer, an Indium gallium nitride (InGaN), and/or the like. As further shown in FIG. 6, a spacer layer 606 (e.g., a GaN spacer layer) may be formed above, over, and/or on the buffer layer 604. As further shown in FIG. 6, a channel layer 608 (e.g., a GaN channel layer) may be formed over, above, and/or on the spacer layer 606. As further shown in FIG. 6, a barrier layer 610 may be formed over, above, and/or on the channel layer 608. The barrier layer 610 may include an AlGaN layer, an AlN layer, an ALGaN layer, a GaN layer, and/or the like. As further shown in FIG. 6, a p-doped GaN layer 612 may be formed over, above, and/or on the barrier layer 610.

The number and arrangement of layers shown in FIG. 6 is provided as an example. In practice, there may be additional layers, fewer layers, different layers, or differently arranged layers than those shown in FIG. 6.

FIG. 7 is a diagram of example components of a device 700. In some implementations, one or more of the tools 102-110 and/or the wafer/die transport device 112 may include one or more devices 700 and/or one or more components of device 700. As shown in FIG. 7, device 700 may include a bus 710, a processor 720, a memory 730, a storage component 740, an input component 750, an output component 760, and a communication interface 770.

Bus 710 includes a component that permits communication among multiple components of device 700. Processor 720 is implemented in hardware, firmware, and/or a combination of hardware and software. Processor 720 is a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a microprocessor, a microcontroller, a digital signal processor (DSP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or another type of processing component. In some implementations, processor 720 includes one or more processors capable of being programmed to perform a function. Memory 730 includes a random access memory (RAM), a read only memory (ROM), and/or another type of dynamic or static storage device (e.g., a flash memory, a magnetic memory, and/or an optical memory) that stores information and/or instructions for use by processor 720.

Storage component 740 stores information and/or software related to the operation and use of device 700. For example, storage component 740 may include a hard disk (e.g., a magnetic disk, an optical disk, and/or a magneto-optic disk), a solid state drive (SSD), a compact disc (CD), a digital versatile disc (DVD), a floppy disk, a cartridge, a magnetic tape, and/or another type of non-transitory computer-readable medium, along with a corresponding drive.

Input component 750 includes a component that permits device 700 to receive information, such as via user input (e.g., a touch screen display, a keyboard, a keypad, a mouse, a button, a switch, and/or a microphone). Additionally, or alternatively, input component