230, which may include volatile memory and/or persistent storage. The CPU 220 comprises a plurality of processor cores 225-1, . . . , 225-N having any suitable implementation.

The CPU 220 further comprises an IO processor 235 that is communicatively coupled with the plurality of processor cores 225-1, . . . , 225-N. In some embodiments, the CPU 220 further comprises a PCIe bridge unit (PBU) 240 that is communicatively coupled with the IO processor 235 and with the IO subsystem 210. The IO processor 235 comprises a trace assist unit that is communicatively coupled with the plurality of processor cores 225-1, . . . , 225-N and receives and processes trace events therefrom. The trace assist unit is described in greater detail below with respect to FIGS. 3, 4, and 5. While the various components are described as being included in the CPU 220, alternate embodiments may have different arrangements of the components within the CPC 205. For example, the IO processor 235 may be implemented separate from the CPU 220 in one alternate implementation.

The IO subsystem 210 comprises a switch 245 that is communicatively coupled to the PBU 240 via communication links 215, and with a plurality of IO adapters 255 of the IO subsystem 210 via communication links 250. The communication links 215, 250 are implemented using a plurality of conductors in any suitable form (e.g., conductive traces or wires). In one non-limiting example, the communication links 215, 250 each comprise an 8-lane PCIe connection, where each of the lanes comprises a respective two conductors. Other configurations of the communications links 215, 250, which may include the use of different protocols, are also contemplated. The plurality of IO adapters 255 connect the computing system 200 to an external network 260, e.g., a storage area network (SAN) having one or more storage devices, using any suitable technology such as Ethernet.

The computing system 200 (more specifically, the IO processor 235) defines a plurality of channels (or communication paths) between the CPC 205 and various devices of the external network 260. Each channel is assigned a distinct channel path identifier (CHPID), which may represent both a physical channel port location (PCHID) and a logical channel subsystem. In some embodiments, the channels established by the IO processor 235 are virtualized, so that any operating system instance executing on one of the processor cores 225-1, . . . , 225-N is able to access any channel.

The architecture of the computing system 200, and more specifically the use of the IO processor 235 within the CPC 205, provides a number of benefits. In general terms, the computing system 200 provides a more efficient operation reflecting updates to the architecture of the CPC 205. First, providing the IO processor 235 within the CPC 205 shortens a path length from the processor cores 225-1, . . . , 225-N to the IO functionality, supporting greater throughput and responsiveness. The IO processor 235 may be reconfigured and therefore adaptable to new types of communication links used by the IO subsystem 210. Further, use of the IO processor 235 allows new types of IO adapters 255 to be integrated into the computing system 200 without requiring development of custom interface hardware in the IO subsystem 210 (e.g., implementing using a unique ASIC and IO card). In this way, the overall cost of the computing system 200 and/or its power consumption may be reduced.

Refer now to diagram 300 of FIG. 3, in which the IO processor 235 comprises a plurality of processing elements 302 that provide connectivity for the plurality of channels, as well as implement protocols on the plurality of channels. The plurality of processing elements 302 may have any suitable implementation. In one non-limiting example, the plurality of processing elements 302 implement the RISC-V instruction set architecture, which allows the plurality of processing elements 302 to be dynamically updated to support new features and/or functions, as well as to provide functionality beyond the operations discussed above.

The IO processor 235 is communicatively coupled with the plurality of processor cores 225-1, 225-2, . . . , 225-N through a communication fabric 310. Generally, the communication fabric 310 comprises components and logic that support dynamic formation of interconnections between the various nodes connected to the communication fabric 310. In the example shown in diagram 300, each of the plurality of processor cores 225-1, 225-2, . . . , 225-N is connected with each other through the communication fabric 310, as well as with the IO processor 235.

The IO processor 235 further comprises a trace assist unit (TAU) 305 that receives and processes trace events received from the plurality of processor cores 225-1, 225-2, . . . , 225-N through the communication fabric 310. The trace events generally represent a record of program execution by the plurality of processor cores 225-1, 225-2, . . . , 225-N. The trace events are typically timestamped and may vary in size.

Even with the compressed format of the trace events, the plurality of processor cores 225-1, 225-2, . . . , 225-N generate a large amount of trace data during program execution. According to embodiments described herein, the TAU 305 is capable of managing the large amount of trace data using a plurality of physical buffers. In some embodiments, the plurality of physical buffers are dedicated buffers that are written by the TAU 305 without using cache memory of subsystems of the IO processor 235 or cache memory of subsystems of the processor cores 225-1, . . . , 225-N. In this way, writing the trace events can be performed without requiring coherency handling of the cache lines in the various processor subsystems, which provides improvements through increased speed and/or decreased energy consumption of the CPC 205.

Using one or more levels of categorization for the trace events, the TAU 305 packs those trace events having a same categorization into particular physical buffer(s) that are dynamically assigned to the particular categorization. The plurality of physical buffers may be relatively small in size, as the trace events tend to be received from the plurality of processor cores 225-1, 225-2, . . . , 225-N in bursts. In one non-limiting example, the categorization may include the particular channel on which the trace event was received, and/or a particular class of a plurality of classes within the channel. The trace events packed into the physical buffer are unloaded by the TAU to an external memory (e.g., an external cache of the CPC 205) responsive to one or more predefined conditions, such as the physical buffer being full, no physical buffers being available for storing the received trace event (that is, no physical buffers are assigned to the particular categorization), or the occurrence of an error event requiring the physical buffer to be flushed. In some embodiments, the external cache is backed by a much larger system memory that can allocate multiple gigabytes for storing trace data. The stored trace data may be separately collected and parsed by software that is executed separate from the trace generation and processing functionality.