FIGS. 6, 7, and 8.

As shown in FIG. 3, the clock generation circuit 300 includes a first BIST switch logic circuit 302, a second BIST switch logic circuit 304, a number of transistors 306, 308, 310, 312, 314, 316, 318, 320, 322, and 324, and an inverter 326. The transistor 306, 308, 316, and 318 may be implemented as an n-type metal-oxide-semiconductor transistor, and the transistors 310, 312, 314, 320, 322, and 324 may each be implemented as a p-type metal-oxide-semiconductor transistor, while the transistors 306 to 324 may each be implemented as any of various other types of transistors while remaining within the scope of the present disclosure.

The first BIST switch logic circuit 302 can receive the internal clock enable signal CKEN, and the control signal BIST (or its logic inverse, BISTB) to generate the intermediate clock enable signal CKENI. The second BIST switch logic circuit 304 can receive the same internal clock enable signal CKEN, and the control signal BIST (or its logic inverse, BISTB) to generate the intermediate clock enable signal CKENIM. The intermediate clock enable signal CKENI and CKENIM are configured to gate the transistors 308 and 318, respectively. The transistor 306, serially connected to the transistor 308, may be gated by the first clock signal CLK; and the transistor 316, serially connected to the transistor 318, may be gated by the second clock signal CLKM. The transistor 310 may be gated by the clock enable signal CKEN. The transistor 312 may be gated by the control signal BIST. The transistor 314 may be gated by the first clock signal CLK. The transistor 322 may be gated by the control signal BISTB. The transistor 320 may be gated by the second clock signal CLKM. The transistor 324 may be gated by another internal signal CKPI, which may be generated by a control circuit (e.g., 104). A logic state of the signal CKPI may change in accordance with the first clock signal CLK or second clock signal CLKM, in some embodiments.

In some embodiments, the first BIST switch logic circuit 302 is activated and the second BIST switch logic circuit 304 is deactivated, when the control signal BIST is at logic low and the control signal BISTB is at logic high (e.g., the normal operation mode); and the second BIST switch logic circuit 304 is activated and the first BIST switch logic circuit 302 is deactivated, when the control signal BIST is at logic high and the control signal BISTB is at logic low (e.g., the BIST mode). Similarly, the clock enable signal CKEN can be first asserted to logic high when either of the first BIST switch logic circuit 302 or second BIST switch logic circuit 304 is activated, next to logic low for a predetermined period of time, and then back to logic high after the predetermined period of time elapses. Accordingly, When at the normal operation mode, following the clock enable signal CKEN, the intermediate clock enable signal CKENI is first pulled up to logic high, next to logic low, and then to logic low, and a first conduction path 332 can be intervally or periodically formed to output the first clock signal CLK as the clock pulse signal CKP. When at the BIST mode, following the clock enable signal CKEN, the intermediate clock enable signal CKENIM is first pulled up to logic high, next to logic low, and then to logic low, a second conduction path 334 can be intervally or periodically formed to output the second clock signal CLKM as the clock pulse signal CKP.

For example, when the control signal BIST is configured at logic low (i.e., the control signal BISTB at logic high), the first BIST switch logic circuit 302 is activated and the second BIST switch logic circuit 304 is deactivated. The first BIST switch logic circuit 302 can first pull up, next pull down, and then pull up the intermediate clock enable signal CKENI based on a logic combination of the clock enable signal CKEN and the control signal BIST. The transistors 308 and 306 are turned on and off by the intermediate clock enable signal CKENI and the first clock signal CLK, respectively. As indicated above, the intermediate clock enable signal CKENI, which follows the clock enable signal CKEN, may have a lower frequency than the first clock signal CLK. As such, the first conduction path 332 is intervally or periodically formed to propagate through the transistors 306-308 and the inverter 326, which includes only two gate delays.

When the control signal BIST is configured at logic high (i.e., the control signal BISTB at logic low), the first BIST switch logic circuit 302 is deactivated and the second BIST switch logic circuit 304 is activated. The second BIST switch logic circuit 304 can first pull up, next pull down, and then pull up the intermediate clock enable signal CKENIM based on a logic combination of the clock enable signal CKEN and the control signal BISTB. The transistors 318 and 316 are turned on and off by the intermediate clock enable signal CKENIM and the second clock signal CLKM, respectively. As indicated above, the intermediate clock enable signal CKENIM, which follows the clock enable signal CKEN, may have a lower frequency than the second clock signal CLKM. As such, the second conduction path 334 is intervally or periodically formed to propagate through the transistors 316-318 and the inverter 326, which includes only two gate delays.

FIGS. 4 to 8 respectively illustrate example circuit diagrams of the clock generation circuit 102 (FIG. 1), in accordance with various embodiments. Specifically, FIGS. 4 and 5 illustrate various example circuit diagrams of the clock generation circuit 200 (FIG. 2); and FIGS. 6, 7, and 8 illustrate various example circuit diagrams of the clock generation circuit 300 (FIG. 3). Thus, some of the reference numerals of FIG. 2 may be reused in FIGS. 4 and 5; and some of the reference numerals of FIG. 3 may be reused in FIGS. 6, 7, and 8. It should be understood that the clock generation circuit 200 or clock generation circuit 300 is not limited to the circuit diagrams shown in FIGS. 4-8. Other circuit diagrams may also be contemplated.

Referring first to FIG. 4, an implementation of the clock generation circuit 200 is depicted, hereinafter “clock generation circuit 400.” In FIG. 4, the first BIST switch logic circuit 202 includes transistors 402 and 412; and the second BIST switch logic circuit 204 includes transistors 404 and 414. Although the transistors 402 to 414 are each implemented as an n-type metal-oxide-semiconductor transistor in the illustrated example of FIG. 4, it should be understood that the transistors 402 to 414 can each implemented as any of various other transistors while remaining within the scope of the present disclosure. The transistors 402 and 412 of the first BIST switch logic circuit 202 are gated by the first clock signal CLK and the control signal BISTB, respectively; and the transistors 404 and 414 of the second BIST switch logic circuit 204 are gated by the second clock signal CLKM and the control signal BIST, respectively.

As a result, when the control signal BIST is received as logic low (i.e., the control signal BISTB is at logic high), the transistor 412 is turned on and the transistor 402 can be toggled (by the first clock signal CLK) to form the first conduction path 232, i.e., outputting the first clock signal CLK as the clock pulse signal CKP with a different (e.g., slower) frequency. On the other hand, when the control signal BIST is received as logic high (i.e., the control signal BISTB is at logic low), the transistor 414 is turned on and the transistor 404 can be toggled (by the second clock signal CLKM) to form the second conduction path 234, i.e., outputting the second clock signal CLKM as the clock pulse signal CKP with a different (e.g., slower) frequency.

Referring next to FIG. 5, another implementation of the clock generation circuit 200 is depicted, hereinafter “clock generation circuit 500.” In FIG. 5, the first BIST switch logic circuit 202 includes a transmission gate 502 and transistors 512 and 522; and the second BIST switch logic circuit 204 includes a transmission gate 504 and transistors 514 and 524. Although the transistors 512-522 and 514-524 are each implemented as an n-type metal-oxide-semiconductor transistor in the illustrated example of FIG. 5, it should be understood that the transistors 512-522 and 514-524 can each implemented as any of various other transistors while remaining within the scope of the present disclosure. The transmission gate 502 can be controlled by the control signals BIST and BISTB to selectively pass the first clock signal CLK; and the transmission gate 504 can be controlled by the control signals BIST and BISTB to selectively pass the second clock signal CLKM. When the first clock signal CLK is allowed to pass, the transistor 522 can be gated by the first clock signal CLK; and when the second clock signal CLKM is allowed to pass, the transistor 524 can be gated by the second clock signal CLKM.

As a result, when the control signal BIST is received as logic low (i.e., the control signal BISTB is at logic high), the first clock signal CLK is allowed to pass through the transmission gate 502, and can thus gate (e.g., toggle) the transistor 522. The first conduction path 232 can thus be formed, i.e., outputting the first clock signal CLK as the clock pulse signal CKP with a different (e.g., slower) frequency. On the other hand, when the control signal BIST is received as logic high (i.e., the control signal BISTB is at logic low), the second clock signal CLKM is allowed to pass through the transmission gate 504, and can thus gate (e.g., toggle) the transistor 524. The second conduction path 234 can thus be formed, i.e., outputting the second clock signal CLKM as the clock pulse signal CKP with a different (e.g., slower) frequency.

Referring next to FIG. 6, an implementation of the clock generation circuit 300 is depicted, hereinafter “clock generation circuit 600.” In FIG. 6, the first BIST switch logic circuit 302 includes an inverter 602 and a NOR gate 612; and the second BIST switch logic circuit 304 includes an inverter 604 and a NOR gate 614. The NOR gate 612 has two inputs, one of which receives the control signal BIST and the other of which receives a logic inverse of the internal clock enable signal CKEN; and the NOR gate 614 has two inputs, one of which receives the control signal BISTB and the other of which receives the logic inverse of the internal clock enable signal CKEN.

As a result, when the control signal BIST is received as logic low (i.e., the control signal BISTB is at logic high), the NOR gate 612 can toggle the intermediate clock enable signal CKENI (a NOR′ed signal of the control signal BIST and the logic inverse of the internal clock enable signal CKEN) with a frequency based on the frequency of the clock enable signal CKEN, and the NOR gate 614 can keep the intermediate clock enable signal CKENIM (a NOR′ed signal of the control signal BISTB and the logic inverse of the internal clock enable signal CKEN) at logic low. The conduction path 332 can thus be intervally or periodically formed, i.e., outputting the first clock signal CLK as the clock pulse signal CKP with a different (e.g., slower) frequency. On the other hand, when the control signal BIST is received as logic high (i.e., the control signal BISTB is at logic low), the NOR gate 614 can toggle the intermediate clock enable signal CKENIM (a NOR′ed signal of the control signal BISTB and the logic inverse of the internal clock enable signal CKEN) with a frequency based on the frequency of the clock enable signal CKEN, and the NOR gate 612 can keep the intermediate clock enable signal CKENI (a NOR′ed signal of the control signal BIST and the logic inverse of the internal clock enable signal CKEN) at logic low. The conduction path 334 can thus be intervally or periodically formed, i.e., outputting the second clock signal CLKM as the clock pulse signal CKP with a different (e.g., slower) frequency.

Referring next to FIG. 7, another implementation of the clock generation circuit 300 is depicted, hereinafter “clock generation circuit 700.” In FIG. 7, the first BIST switch logic circuit 302 includes transistors 702, 712, 722, and 732; and the second BIST switch logic circuit 304 includes transistors 704, 714, 724, and 734. Although the transistors 712-732 and 714-734 are each implemented as an n-type metal-oxide-semiconductor transistor and the transistor 702 and transistor 704 are each implemented as a p-type metal-oxide-semiconductor transistor in the illustrated example of FIG. 7, it should be understood that the transistors 702-732 and 704-734 can each implemented as any of various other transistors while remaining within the scope of the present disclosure. The transistors 702 and 712 may form a first inverter receiving the control signal BISTB as its input signal and outputting the intermediate clock enable signal CKENI as its output signal; and the transistors 704 and 714 may form a second inverter receiving the control signal BIST as its input signal and outputting the intermediate clock enable signal CKENIM as its output signal. Further, each of the first and second inverters is biased between the internal clock enable signal CKEN and ground.

As a result, when the control signal BIST is received as logic low (i.e., the control signal BISTB is at logic high), the intermediate clock enable signal CKENIM is outputted by the second inverter formed by the transistors 704 and 714 as toggling between logic high and low with a frequency based on the frequency of the clock enable signal CKEN, and the intermediate clock enable signal CKENI remains at logic low. The conduction path