104 and the core area 105.

In this case, packaging (PKG) of the two wafers stacked together may influence their reliability. In a packaging process, in order to reduce the overall thickness of the two wafers stacked together, they are usually thinned, for example, back grinding (BG) is performed on the two wafers, wherein before grinding the back of one of the two wafers, the back of the other wafer needs to be protected and fixed. The protection method may be to attach a BG tape on a side surface of each of the remaining marginal area 104 and the core area 105, and the method of fixing may include the use of a relevant device (such as a sucking disc) of a machine table to fix the BG tape. FIG. 2 shows a schematic cross-sectional diagram of attaching a BG tape provided in implementations of the present disclosure, wherein when grinding the back (a side surface of the second wafer 102 far away from the first wafer 101) of the second wafer 102, the BG tape 106 is attached to a side surface of each of the remaining marginal area 104 and the core area 105 with the height difference, and fixed by a workbench 108.

Due to the presence of the height difference, a stress difference also exists between the remaining marginal area 104 and the core area 105, such that sidewalls of the remaining marginal area 104 and the core area 105 are more prone to generate cracks and particle impurities when the back grinding is performed on the remaining marginal area 104 and the core area 105; moreover, the larger the height difference of the remaining marginal area 104 and the core area 105 is, the larger the stress difference existing therebetween is, and the remaining marginal area 104 is more prone to drop particle impurities, thereby causing greater damage to the memory cell layer or peripheral circuit due to the dropped particle impurities during the grinding process. Although the BG tape 106 has a certain capability of adhesion for the particle impurities, the larger the height difference of the remaining marginal area 104 and the core area 105 is, the larger a void 107 formed at a connection of the remaining marginal area 104 and the core area 105 is, and the looser the BG tape 106 is attached to the remaining marginal area 104; as such, the BG tape 106 cannot effectively adhere the particle impurities.

Based on this, in order to address one or more of the above problems, implementations of the present disclosure provide a semiconductor structure and a fabrication method thereof, a memory device and a memory system. FIG. 3 shows a schematic flow diagram of a fabrication method of a semiconductor structure provided by implementations of the present disclosure. The method comprises the following operations:

- operation S201: providing a stack structure comprising a first stack layer and a second stack layer stacked together, wherein a first region and a second region surrounding the first region are disposed in the stack structure, and a first surface of the first region and a first surface of the second region are coplanar; and
- operation S202: forming a filling structure covering a second surface of the second region, wherein the second surface and the first surface of the second region are respectively two surfaces of the second region disposed oppositely in a first direction that is parallel to a stacking direction of the first stack layer and the second stack layer.

FIGS. 4a-4j are examples of cross-sectional views of a fabrication process of a semiconductor structure provided by implementations of the present disclosure. The operations as shown in FIG. 3 are not exclusive, and other operations can also be performed before, after, or between any of the illustrated operations. A formation process of the semiconductor structure of this embodiment is further described below in conjunction with FIGS. 3 and 4a-4j.

Operation S201 is performed to provide a stack structure.

In some implementations, providing the stack structure comprises: providing a first semiconductor layer and a second semiconductor layer stacked together. Providing the first semiconductor layer and the second semiconductor layer stacked together comprises:

- providing a first substrate, forming a first functional layer covering the first substrate. and forming a first bonding layer covering the first functional layer to form the first semiconductor layer;
- providing a second substrate, forming a second functional layer covering the second substrate, and forming a second bonding layer covering the second functional layer to form the second semiconductor layer; and
- bonding the first bonding layer to the second bonding layer to form the first semiconductor layer and the second semiconductor layer stacked together.

FIG. 4a shows a schematic cross-sectional structure diagram of the first semiconductor layer 30, wherein the first substrate 301 is provided, and the first substrate 301 may include an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), a silicon on insulator (SOI) substrate, a germanium on insulator (GeOI) substrate, etc. Preferably, the first substrate 301 is a silicon substrate. Next, the first functional layer 302 covering the first substrate 301 is formed, wherein the first functional layer 302 may comprise a peripheral circuit and an interconnection structure connected with the peripheral circuit, and the peripheral circuit may include any suitable digital, analog and/or hybrid signal circuit configured to facilitate a memory to achieve various operations such as a reading operation, writing operation, erasing operation and the like. For example, the peripheral circuit may comprise a control logic (e.g., a control circuit or a controller), a data buffer, a decoder, a driver and a reading-writing circuit, etc. When the control logic receives a reading-writing operation command and address data, under the action of the control logic, the decoder may apply respective voltages obtained from the driver to respective bit lines and word lines based on a decoded address, to achieve reading and writing of data.

Next, the first bonding layer 303 covering the first functional layer 302 is formed, and may comprise: a first dielectric layer, a plurality of first trenches penetrating through the first dielectric layer, and first conductive contacts located in the first trenches, wherein the first conductive contacts are connected with an interconnection structure in the first functional layer. The first semiconductor layer 30 may be divided into a core area 30a and a marginal area 30b surrounding the core area, wherein the peripheral circuit in the first functional layer 302 is located in the core area 30a of the first semiconductor layer.

FIG. 4b shows a schematic cross-sectional structure diagram of the second semiconductor layer 40, wherein the second substrate 401 is provided and may be the same as the first substrate 301. The second functional layer 402 may comprise a memory cell array and an interconnection structure connected with the memory cell array, wherein the memory cell array may comprise a plurality of memory dies; each memory die may comprise a plurality of memory planes; each of the memory planes may comprise a plurality of memory blocks; each of the memory blocks may comprise a plurality of memory pages; each of the memory pages may comprise a plurality of memory cells; and each of the memory cells may be programmed and store one or more bits of data. In some particular implementations, each memory block may be coupled to a plurality of word lines; a plurality of memory cells coupled to each of the separately controlled word lines constitute a memory page, and all memory cells coupled to each memory page constitute a memory cell layer. A plurality of memory cells are provided in a form of an array of memory strings, and each memory string extends vertically above the second substrate. In some implementations, each memory string comprises a plurality of memory cells that are coupled in series and stacked vertically. Here, each memory cell may hold a continuous analog value, such as a voltage or charges, which depends on the number of electrons trapped within a region of the memory cell. Each memory cell may be either a floating gate memory cell that comprises a floating gate transistor, or a charge trapping memory cell that comprises a charge trapping transistor.

Next, the second bonding layer 403 covering the second functional layer 402 is formed, and may comprise: a second dielectric layer, a plurality of second trenches penetrating through the second dielectric layer, and second conductive contacts located in the second trenches, wherein the second conductive contacts are connected with an interconnection structure in the second functional layer. The second semiconductor layer 40 may also be divided into a core area 40a and a marginal area 40b surrounding the core area 40a, wherein the memory cell array in the second functional layer 402 is located in the core area 40a of the second semiconductor layer.

The positions of the first functional layer 302 and the second functional layer 402 may be interchanged. A structural topography of the first bonding layer 303 and a structural topography of the second bonding layer 403 may be the same or may be different. In particular, radial widths (here, the radial width may be interpreted as a width of a cross-section along a width direction of the first trenches) of the first conductive contacts and radial widths of the second conductive contacts may be equal or different. In a practical application, cross-sections of the first trenches and the second trenches may be round, elliptical or strip-shaped, etc.; the materials of the first dielectric layer and the second dielectric layer include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric or any combination thereof; and the materials of the first conductive contacts and the second conductive contacts may include a conductive material, including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof. Here, both metal bonding (conductive contacts) and dielectric material bonding exist on a bonding interface between the first bonding layer 303 and the second bonding layer 403.

In the implementations of the present disclosure, the method of forming the first functional layer 302, the second functional layer 402, the first bonding layer 303 and the second bonding layer 403 includes, but is not limited to, a deposition process and an etching process, wherein the deposition process includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD). In some implementations, the deposition process further includes plasma-enhanced CVD (PECVD), metal-organic chemical vapor deposition (MOCVD), etc. The etching process includes, but is not limited to, dry etching, wet etching, etc.

Next, referring to FIG. 4c, the first bonding layer 303 of the first semiconductor layer is bonded to the second bonding layer 403 of the second semiconductor layer to form the first semiconductor layer 30 and the second semiconductor layer 40 stacked together along the first direction. In some implementations of the present disclosure, the first direction is perpendicular to the second direction. The first direction is a Z axis direction, and the second direction may be an X axis direction or a Y axis direction. For ease of clear and concise description, the first direction is the Z axis direction, and the second direction is the X axis direction as an example in each drawing. In some implementations, referring to FIG. 4c, projections of the core area 30a of the first semiconductor layer and the core area 40a of the second semiconductor layer along the first direction overlap, and projections of the marginal area 30b of the first semiconductor layer and the marginal area 40b of the second semiconductor layer along the first direction overlap. In other words, the projection of the core area 30a of the first semiconductor layer on an XOY plane and the projection of the core area 40a of the second semiconductor layer on the XOY plane overlap, and the projection of the marginal area 30b of the first semiconductor layer on the XOY plane and the projection of the marginal area 40b of the second semiconductor layer on the XOY plane overlap.

After bonding the first semiconductor layer 30 and the second semiconductor layer 40. the first conductive contacts are conductively connected with the second conductive contacts by means of contacting, such that the conductive connection of the peripheral circuit and the memory cell array can be achieved. The first bonding layer and the second bonding layer are conjoined together to form a bonding interface, wherein impurities such as bubbles or debris, etc. formed in a bonding process are present in the bonding interface.

Next, the marginal area of the second semiconductor layer is removed, with the remaining second semiconductor layer constituting the second stack layer; and part of the marginal area of the first semiconductor layer is removed, with the remaining first semiconductor layer constituting the first stack layer; and the first stack layer and the second stack layer are stacked together to constitute the stack structure. Removing the marginal area of the second semiconductor layer and part of the marginal area of the first semiconductor layer is to remove the bonding interface located in the marginal areas, such that the impurities in the bonding interface located in the marginal areas may be removed.

In some implementations, referring to FIG. 4d, removing the marginal area of the second semiconductor layer with the remaining second semiconductor layer constituting the second stack layer, comprises: removing the marginal area of the second semiconductor layer, and removing the remaining second substrate, with the remaining second functional layer and the remaining second bonding layer constituting the second stack layer 4001. A process of removing the marginal area includes, but is not limited to, dry etching, and a process of removing the second substrate includes, but is not limited to, chemical mechanical polishing (CMP).

At the same time as removing the marginal area of the second semiconductor layer, part of the marginal area of the first semiconductor layer is removed, and the part of the marginal area of the first semiconductor layer at least comprises the first bonding layer located in the marginal area. Based on this, the remaining first semiconductor layer may comprise the first functional layer and the first substrate, or the remaining first semiconductor layer may comprise part of the first functional layer and the first substrate, or the remaining first semiconductor layer may comprise part of the first functional layer and part of the first substrate. In this case, the remaining first semiconductor layer forms the first stack layer 3001, and the first stack layer 3001 and the second stack layer 4001 constitute the stack structure 20.

In the implementations of the present disclosure, referring to FIG. 4d, the stack structure 20 may be divided into a first portion 20a and a second portion 20b surrounding the first portion 20a, wherein the core area of the first semiconductor layer and the core area of the second semiconductor layer after removing the second substrate constitute the first portion 20a, and the marginal area of the remaining first semiconductor layer constitutes the second portion 20b. Here, the second portion 20b surrounds the first portion 20a, and a first surface of the first portion 20a and a first surface of the second portion 20b are coplanar. In other words, the first surface of the first portion 20a and the first surface of the second portion 20b are essentially the same surface of the first substrate 301. It should be understood that, the height of the first portion in the first direction is greater than the height of the second portion in the first direction.

Next, referring to FIG. 4e, in order to reduce the height difference between a second surface of the first portion 20a and a second surface of the second portion 20b, increase relative stress of the second portion 20b and reduce the probability of dropping particle of the second portion 20b, operation S202 is performed, i.e., the filling structure 504 is formed on the second surface of the second portion 20b. The material of the filling structure 504 may be selected according to actual situations; for example, the remaining part of the first semiconductor layer at least comprises one layer structure; and the constituent material of the filling structure and the constituent material of the layer structure are the same or are different. Referring to FIG. 4c, the remaining part of the first semiconductor layer may comprise a plurality of layers, for example, the first substrate 301, part of the first functional layer 302 and the first bonding layer 303, wherein the constituent material of the filling structure 504 may be the same as or different from the material of the first substrate 301, may also be the same as or different from one of the materials in the first functional layer 302, and may also be the same as or different from one of the materials in the first bonding layer 303. For example, the constituent material of the filling structure 504 includes monocrystalline silicon, silicon oxide, silicon nitride, an organic compound, a photoresist material (e.g., photoresist (PR)) or any other suitable materials, etc. The method of forming the filling structure 504 includes, but is not limited to, CVD, PVD and other processes.

Considering that other material layers will form on the second surface of the first portion and the top face of the filling structure in a subsequent process, preferably, the second surface of the first portion and the top face of the filling structure are substantially flush. Based on this, the height of the filling structure in the first direction is less than or equal to the height difference of the first portion and the second portion in the first direction.

For example, referring to FIG. 4c, the height of the first portion 20a in the Z axis direction is a first distance L1, the height of the second portion 20b in the Z axis direction is a second distance L2, and the height of the filling structure 504 in the Z axis direction is a third distance L3. Here, the third distance L3 is less than or equal to the difference between the first distance L1 and the second distance L2, i.e., L3≤(L1−L2). In some particular implementations, the third distance L3 is greater than ⅓ of the difference between the first distance L1 and the second distance L2, i.e., ⅓(L1−L2)<L3≤(L1−L2); for example, the first distance L1=28 mil, the second distance L2=10 mil, and 6 mil<the third distance L3≤18 mil. The third distance L3 may also be selected and set according to actual requirements, that is to say, according to different implementation requirements, the sizes of the third distance L3 are different.

In some other implementations, the method further comprises: forming a third dielectric layer and a protection layer on a side surface of the second functional layer far away from the second bonding layer and a side surface of the filling structure far away from the second portion; here, the protection layer may comprise a first protection sub-layer and a second protection sub-layer. Exemplarily, referring to FIG. 4f, after forming the filling structure 504, a third dielectric layer 501 is formed on a side surface of the filling structure 504 far away from the second portion 20b and a side surface of the second functional layer 402 far away from the second bonding layer 403; and a first protection sub-layer 503a and a second protection sub-layer 503b covering a first protection sub-layer 503a are formed on the third dielectric layer 501. Here, the height L3 of the filling structure 504 in the Z axis direction is equal to the difference between the height L1 of the first portion in the Z axis direction and the height L2 of the second portion in the Z axis direction. As such, the height difference between the second portion 20b and the first portion 20a in the Z axis direction can be reduced by forming the filling structure 504 on the second surface of the second portion 20b, and when the first surface of the second portion 20b is ground and thinned, the relative stress of the second portion 20b is increased, and the dropping of the particle impurities is reduced. Meanwhile, the probability of dropping particle impurities of the sidewall of the first portion 20a can also be reduced, thereby protecting the first portion against damage and improving the reliability of the first portion.

The order of forming the filling structure and forming the protection layer may be exchanged according to actual requirements, wherein after removing the second substrate, the filling structure may be first formed on the second surface of the second portion, or the protection layer may be first formed on the second surface of the second portion. In some other implementations, the method further comprises: Before forming the filling structure, the protection layer is at least formed on the second surface of the second portion, and the second surface of the second portion and the first surface of the second portion are respectively two surfaces of the second portions disposed oppositely in the first direction.