As the IMPLY logic function is generally considered to be functionally complete, one or more IMPLY functions may be employed to perform other logic functions, such as NOT, NAND, NOR, AND, OR, XOR, and so on. For example, FIGS. 3A through 3G illustrate a series of operations using an IC memory device 300 that includes three charge-trapping devices 102, 104, and 106 to implement a two-input NAND function using multiple IMPLY functions. As shown in FIG. 3A, in some embodiments, the gates of the charge-trapping devices 102, 104, and 106 may be set to programming voltage V_PP(e.g., associated with a “programming” state for each charge-trapping device 102, 104, and 106) to store the state of 0 (low) in each of the charge-trapping devices 102, 104, and 106. In FIG. 3B, the gate of the first charge-trapping device 102 may then be set to V_PP(the “programming” state for the first charge-trapping device 102) or V_EE(the “erasing” state for the first charge-trapping device 102) to store a corresponding state P of 0 or 1, respectively. Concurrently, the gate of the second charge-trapping device 104 may be set to V_PPor V_EEto store a corresponding state Q of 0 or 1, respectively. Also at that time, the gate of the third charge-trapping device 106 may be set to an inhibiting voltage VINH (e.g., associated with an “inhibiting” state) that prevents the current state (0) of the third charge-trapping device 106 from changing while the first and second charge-trapping devices 102 and 104 are being programmed to the P and Q states, respectively.

Thereafter, as shown in FIG. 3C, the gate of the first charge-trapping device 102 may be set to V_R2(thus turning the first charge-trapping device 102 ON without disturbing its stored state P) and the gate of the second charge-trapping device 104 may be set to V_R1(thus placing the second charge-trapping device 104 in its read state to allow the output of its drain to be set based on its stored state Q). Concurrently, the gate of the third charge-trapping device 104 may be set to V_EE(for the erasing state to possibly set the current state(S) of the third charge-trapping device 106 to “erased” based on the expressed state Q of the second charge-trapping device 104).

FIG. 3D provides a truth table describing the result S′ that is stored in the third charge-trapping device 106 as a result of the attempted erasure operation indicated in FIG. 3C. More specifically, if the state of the second charge-trapping device 104 (Q) is low or 0, the second charge-trapping device 104 is ON when its gate is set to V_R1to place the second charge-trapping device 104 in its read state, thus enabling the erasure of the third charge-trapping device 106, resulting in its stored state S′ being erased (e.g., high or 1). If, instead, the state of the second charge-trapping device 104 (Q) is high or 1, the first charge-trapping device 102 is OFF when the gate is set to V_R1, thus disabling the erasure of the second charge-trapping device 104, resulting in its stored state S′ remaining equal to its previous state of 0. Accordingly, the resulting stored state S′ is an inverse of Q (S′=Q IMP 0=NOT Q).

Thereafter, FIG. 3E indicates the use of an additional IMPLY operation of P IMP S′. To perform this function, in some embodiments, the gates of the first, second, and third charge-trapping devices 102, 104, and 106 may be set to V_R1, V_R2, and V_EE, respectively. As a result, the state P of the first charge-trapping device 102 is expressed at its drain, and the second charge-trapping device 104 is turned ON, thus passing the state P of the first charge-trapping device 102 to the third charge-trapping device 106 while the second charge-trapping device 104 maintains its current state Q. Accordingly, the gate of the third charge-trapping device 104 being set to V_EEpossibly enables the erasure of the current state (S′) of the third charge-trapping device 106 based on the expressed state P of the first charge-trapping device 102.

FIG. 3F provides a truth table describing the result S″ that is stored in the third charge-trapping device 106 as a result of the attempted erasure operation indicated in FIG. 3E. More specifically, if the state of the first charge-trapping device 102 (P) is low or 0, the erasure of the third charge-trapping device 106 is enabled, resulting in its stored state S″ being erased (e.g., high or 1). If, instead, the state of the first charge-trapping device 102 (P) is high or 1, the first charge-trapping device 102 is OFF when the gate is set to V_R1to place the first charge-trapping device 102 in the read state, thus disabling the erasure of the third charge-trapping device 106, resulting in its stored state S″ remaining equal to its previous state S′. Accordingly, the resulting stored state S″=P IMP S′=P IMP (Q IMP 0)=P NAND Q.

Thereafter, as depicted in FIG. 3G, the new state S″ of the third charge-trapping device 106 may be output by way of its drain by setting the gates of the first and second charge-trapping devices 102 and 104 to V_R2(thus turning the first and second charge-trapping devices 102 and 104 ON while retaining their respective states P and Q), and setting the gate of the third charge-trapping device 106 to V_R1, thereby outputting the state S″ of the third charge-trapping device 106 via its drain connection.

FIG. 3H illustrates a cross-sectional view of some embodiments of the portion of the IC memory device 300 of FIG. 3A resulting from FEOL processing. A substrate 202 may include four source-drain regions 204 (e.g., doped regions). In some embodiments, in a manner similar to that shown in FIG. 2E, each of a plurality of charge-trapping structures 206 may be formed above the substrate 202 to join a corresponding pair of adjacent source-drain regions 204, and a gate structure 208 may be formed over each charge-trapping structure 206. Each gate structure 208, charge-trapping structure 206, and associated pair of source-drain regions 204 may thus form a corresponding one of the charge-trapping devices 102, 104, and 106 coupled in series.

Furthermore, in some embodiments, each charge-trapping structure 206 and associated gate structure 208 may be surrounded by a spacer 207. Also, in some embodiments, at least the source-drain regions 204 at opposing ends of the serially-coupled charge-trapping devices 102, 104, and 106 may be connected to other circuitry using contacts 213, vias 223 and 233, and metal structures 214, 224, and 234 located in one or more dielectric layers 212, 222, and 232. In some embodiments, each of the gate structures 208 may be coupled by way of contacts, vias, and metal structures not shown in FIG. 3H (e.g., to control circuit 105 of FIG. 1A) to control the charge-trapping devices 102, 104, and 106, as described herein.

FIG. 3I illustrates a cross-sectional view of some embodiments of the portion of the IC memory device 300 of FIG. 3A resulting from BEOL processing. In some embodiments, the substrate 202 may include source-drain regions 204 that have been doped, implanted, or the like. However, in this case, at least some adjacent pairs of the source-drain regions 204 may be bridged via a dielectric structure 258 and an associated gate structure 208 to create a MOSFET not directly associated with charge-trapping devices, as described herein. Further, in some embodiments, the MOSFETS may not be serially coupled, but may instead by isolated from each other by way of a non-conductive plug 205 formed in the substrate 202 through one of the source-drain regions 204, as described above in conjunction with FIG. 2F. Additionally, in some embodiments, the sources and drains of the MOSFETs may be coupled to other circuitry by way of contacts 213, vias 223 and 233, and associated metal structures 214, 224, and 234 located in one or more dielectric layers 212, 222, and 232. In some embodiments, each of the gate structures 208 may be coupled by way of contacts, vias, and metal structures not shown in FIG. 3I to control the MOSFETs.

In FIG. 3I, the charge-trapping devices 102 and 104 may be formed in an upper layer (e.g., dielectric layer 242 over dielectric layer 232) of the IC memory device 300 using thin-film transistor (TFT)-related processes instead of at the substrate 202. In some embodiments, a gate structure 248 is formed over a dielectric layer (e.g., dielectric layer 232) for each of the charge-trapping devices 102 and 104. Also, a corresponding charge-trapping structure 256 may be formed over each gate structure 248. Additionally, a corresponding channel structure 252 may be formed over each charge-trapping structure 256. A plurality of source-drain structures 257 may also be formed over the channel structures 252 such that the channel structures 252 are bridged by one of the source-drain structures 257, and each end of the channel structures 252 at opposing ends of the serially-coupled charge-trapping devices 102 and 104 is covered with a corresponding one of the source-drain structures 257. Further, in some embodiments, at least the source-drain structures 257 at the opposing ends of the serially-coupled charge-trapping devices 102 and 104 may be coupled to other circuitry (e.g., control circuit 105 of FIG. 1A) by way of contacts 253 and metal structures 254. In some embodiments, the gate structures 248 may be coupled to other electronic circuits by other contacts, vias, metal structures, etc. (e.g., within dielectric layer 232, but not shown in FIG. 3I).

FIG. 4 illustrates a methodology 400 in flowchart format that illustrates some embodiments of operation of the IC memory device 100 of FIGS. 2A-2F. Although this method and other methods illustrated and/or described herein are illustrated as a series of acts or events, it will be appreciated that the present disclosure is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

At act 402, a first charge-trapping device and a second charge trapping device coupled in series (e.g., charge-trapping devices 102 and 104 of FIG. 1A) are provided. At act 404, a first input of an IMPLY operation is stored as a stored value of the first charge-trapping device (e.g., state P, as shown in FIG. 2A). At act 406, a second input of the IMPLY operation is stored as a stored value of the second charge-trapping device (e.g., state Q, as shown in FIG. 2A). At act 408, the stored value of the second charge-trapping device is updated based on the stored value of the first charge-trapping device to perform the IMPLY operation (e.g., state Q′, as depicted in FIG. 2B).

FIG. 5 illustrates a methodology 500 in flowchart format that illustrates some embodiments of operation of the IC memory device 300 of FIGS. 3A-3I. At act 502, each of one or more inputs of a logic function is stored in a corresponding one of a plurality of charge-trapping devices coupled in series (e.g., charge-trapping devices 102, 104, and 106 of FIG. 3A, storing states P, Q, and 0, respectively, as shown in FIG. 3B). At act 504, one or more IMPLY operations are performed between corresponding pairs of the plurality of charge-trapping devices to execute the logic function (e.g., as shown in FIGS. 3C through 3F, producing state S″). At act 506, a result of the logic function is output from one of the plurality of charge-trapping devices.

FIG. 6 illustrates a schematic view of some embodiments of a portion of an IC memory device 600 including five charge-trapping devices 102, 104, 106, 108, and 110 to implement one or more logic functions using one or more IMPLY functions, while also serving as memory cells, according to the present disclosure. While five charge-trapping devices are depicted in FIG. 6, any number of charge-trapping devices greater than two may be employed in other embodiments. For example, in FIG. 6, first and second charge-trapping devices 102 and 104 may be employed to perform an IMPLY function (e.g., as described above in conjunction with FIGS. 2A through 2D) and/or third through fifth charge-trapping devices 106, 108, and 110 may be used to perform a NAND function (e.g., as discussed above in connection with FIGS. 3A through 3G).

In FIG. 6, in some embodiments, a gate connection 602 for each of the charge-trapping devices 102, 104, 106, 108, and 110 may be controlled (e.g., by control circuit 105 of FIG. 1A). In addition, a first source-drain connection 604 of the first charge-trapping device 102 and a second source-drain connection 605 of the fifth charge-trapping device 110, in conjunction with gate connections 602, may facilitate logic and/or output control for the five charge-trapping devices 102, 104, 106, 108, and 110 with respect to their logic and/or memory functions. In addition, at least one additional source-drain connection 606 coupling two adjacent charge-trapping devices (e.g., charge-trapping devices 104 and 106) may provide one or more outputs (e.g., one or more outputs of at least one logic function implemented by the charge-trapping devices 102, 104, 106, 108, and 110). While FIG. 6 shows a single additional source-drain connection 606, other embodiments may include multiple additional source-drain connections 606 involving multiple pairs of charge-trapping devices.

Consequently, in some embodiments, as illustrated in FIG. 6, a series of charge-trapping devices may be operated as a typical series-coupled IC memory device (e.g., a NAND memory) and concurrently serve as an IC logic device, such as for an in-memory computing architecture. Such embodiments may maintain the IC footprint typically consumed by the charge-trapping devices of an IC memory device (e.g., by providing the logical functions in the IC memory device via a separate control circuit of the IC memory device).

FIGS. 7A through 7F illustrate a series of incremental manufacturing steps as a series of cross-sectional views of the IC memory device 600 of FIG. 6 resulting from FEOL processing. FIG. 7A provides a substrate 202 as a basis upon which the resulting IC memory device 600 may be constructed. In some embodiments, the substrate 202 may be p-doped silicon, but other materials may be used in other embodiments.

In FIG. 7B, a plurality of doped regions 204 (e.g., n-doped regions) may be formed (e.g., via ion implantation) in the substrate 202. Also, in some embodiments, as depicted in FIG. 7C, each of a plurality of charge-trapping structures 206 (e.g., a ferroelectric structure including ferroelectric material) may be formed over the substrate 202 to bridge two consecutive doped regions 204. As also illustrated in FIG. 7C, in some embodiments, a gate structure 208 may be formed over each of the charge-trapping structures 206, resulting in the formation of the charge-trapping devices 102, 104, 106, 108, and 110 of FIG. 6. Additionally, in FIG. 7D, a spacer may be formed (e.g., conformally) about each charge-trapping structure 206 and associated gate structure 208.

In some embodiments, in FIG. 7E, in some embodiments, a dielectric layer 212 (e.g., an oxide, such as silicon dioxide) may be formed over the substrate 202. In addition, in some embodiments, a connection structure 215 including contacts 213 and associated metal structures 214 may be coupled to the source-drain region 204 at a first end of the charge-trapping devices (e.g., first charge-trapping device 102) to form the first source-drain connection 604. Also, the connection structure 215 may be coupled to the source-drain region 204 at a second end of the charge-trapping devices (e.g., fifth charge-trapping device 110) to form the second source-drain connection 605. Furthermore, the connection structure 215 may be coupled to the source-drain region 204 associated with the second and third charge-trapping devices 104 and 106 to form the additional source-drain connection 606. Moreover, as shown in FIG. 7F, the connection structure 215 may be connected to one or more vias 223 and 233, as well as additional metal structures 224 and 234, to extend one or more of the first source-drain connection 604, the second source-drain connection 605, and/or the additional source-drain connection 606. In some embodiments, the gate structures 208 may be coupled to other electronic circuits by other contacts, vias, metal structures, etc. (e.g., within dielectric layer 212, but not shown in FIGS. 7E and 7F).

FIG. 8 illustrates a methodology 800 in flowchart format that illustrates some embodiments of the present concept.

At act 802, a plurality of source-drain regions (e.g., source-drain regions 204) may be formed in a substrate (e.g., substrate 202). FIGS. 7A and 7B illustrate cross-sectional views of some embodiments corresponding to act 802.

At act 804, a plurality of charge-trapping structures (e.g., charge-trapping structures 206) may be formed over the substrate 202. FIG. 7C illustrates a cross-sectional view of some embodiments corresponding to act 804.

At act 806, a corresponding gate structure (e.g., gate structure 208) may be formed over each charge-trapping structure 206. FIGS. 7C and 7D illustrate cross-sectional views of some embodiments corresponding to act 806.

At act 808, a first connection (e.g., first source-drain connection 604) is formed between a first source-drain region at a first end of the plurality of charge-trapping devices and a first metal structure. FIG. 7E illustrates a cross-sectional view of some embodiments corresponding to act 808.

At act 810, a second connection (e.g., second source-drain connection 605) is formed between a second source-drain region at a second end of the plurality of charge-trapping devices and a second metal structure. FIG. 7E illustrates a cross-sectional view of some embodiments corresponding to act 810.

At act 812, a third connection (e.g., additional source-drain connection 606) is formed between an additional source-drain region of the plurality of source-drain regions and a third metal structure. FIG. 7E illustrates a cross-sectional view of some embodiments corresponding to act 812.

FIGS. 9A through 9F illustrate a series of incremental manufacturing steps as a series of cross-sectional views of the IC memory device 600 of FIG. 6 resulting from BEOL processing. FIG. 9A shows a starting structure at which the BEOL processing for the IC memory device 600 may begin. More specifically, FIG. 9A illustrates a plurality of MOSFETs that include source-drain regions 204, dielectric structures 258, gate structures 208, and non-conductive plugs