In sharp contrast to the manufacture of semiconductor device packages formed without use of the arrangements, the use of the arrangements eliminates burrs formed in dimple formation or in multiple pass saw step cutting processes on no-lead package terminals, and therefore eliminates the need for deburring the packages. Further the use of the arrangements advantageously simplifies the sawing operations to a single saw pass through the mold compound and the leadframe material, reducing costs and increasing throughput.

FIGS. 1A and 1B illustrate in projection views a semiconductor wafer 101 having semiconductor devices formed on it (FIG. 1A), and an individual semiconductor die 105 from the wafer for wire bonding and face up mounting (FIG. 1B), respectively. In FIG. 1A, a semiconductor wafer 101 is shown with an array of semiconductor dies 105 formed in rows and columns on a device side surface. The semiconductor dies 105 can be formed using processes typically used in a semiconductor manufacturing facility, including ion implantation, substrate doping, thermal anneals, oxidation, dielectric and metal deposition, sputter, photolithography, pattern, etch, strip, chemical mechanical polishing (CMP), electroplating, and other processes for making semiconductor devices on wafers. Scribe lanes 103 and 104, which are perpendicular to one another and which run in parallel groups across the wafer 101, separate the rows and columns of the completed semiconductor dies 105, and provide areas for dicing the semiconductor wafer 101 so as to separate the semiconductor dies 105 from one another.

FIG. 1B illustrates a single semiconductor die 105 after singulation from the semiconductor wafer 101 (see FIG. 1A), with bond pads 108, which are conductive pads that are electrically coupled to devices (not shown) formed on a device side surface of the semiconductor die 105. The bond pads 108 are configured for connection to leads of a semiconductor device package.

FIG. 2A illustrates in a projection view a quad flat no-lead (QFN) semiconductor device package 200 of an example arrangement. The view in FIG. 2A is shown looking at the board side surface of the semiconductor device package 200. In the illustrated example, the semiconductor device package has sixteen terminals 211 for surface mounting to a board using solder. The terminals 211 have wettable flanks and bottom surfaces exposed from the mold compound 223. Mold compound 223 extends to a package boundary along the side of the terminals 211. Die pad 213 is exposed from the mold compound 223, and can be used as a thermal path to remove excess heat from the semiconductor die mounted within the semiconductor device package 200. Other no-lead semiconductor package types can be used with the arrangements, such as small outline no-lead (SON) packages that have terminals on two opposing sides. In FIG. 2A, the terminals 211 have a center-to-center pitch distance Pd. In an example using the arrangements, this pitch distance can be less than 0.5 millimeters, for example 0.4 millimeters. In sharp contrast, semiconductor device packages formed without use of the arrangements are limited to pitch distances of at least 0.5 millimeters, because the dimple process cannot support smaller pitch between the terminals. As device sizes and package sizes are continually decreasing, use of the arrangements enables smaller pitch between the terminals, which is needed.

FIG. 2B is an end view of the semiconductor device package 200 illustrating the terminals 211 exposed from the mold compound 223. The board side of the semiconductor device package 200 is shown facing upwards as the semiconductor device package 200 is oriented in FIG. 2B, with the bottom surfaces of the terminals 211 at the top. The ends of the terminals 211 show the stepped edge inset from the exterior of the semiconductor device package 200. Note that due to the use of the laser to remove the mold compound 223 only from the terminals 211, the mold compound 223 between the terminals 211 is not inset.

FIG. 3A illustrates, in a projection view taken from a board side surface, a unit leadframe 337 for use with an example arrangement. Terminals 311, which are configured to be surface mounted, are formed from leadframe leads. A die pad 313 is also a part of the leadframe 337. The die pad 313 has a full thickness in the center portion, and the terminals 311 have full thickness in portions and less than full thickness in other portions. The terminals 311 are formed using partial etching of the leadframe 337 to form the stepped edge and inset portions of the terminals. The leadframe 337 can be a bare copper leadframe, or leadframe 337 can be a “pre-plated” leadframe (sometimes referred to as a “PPF”) that is plated with metals to aid in soldering and die mount or wire bonding, such as gold, nickel, palladium, tungsten, silver or tin. In an example arrangement, a pre-plated leadframe has a copper base that is plated in an “ENEPIG” plating process (electroless nickel, electroless palladium, immersion gold) or an “ENIG” plating process (electroless nickel, immersion gold). The term “pre-plated” refers to a leadframe that is plated before semiconductor dies are mounted to it, in contrast some platings are done after molding for soldering terminals. These pre-platings reduce tarnish and corrosion, and prevent copper ion diffusion to the surface, increasing shelf life of the leadframe, and aiding in soldering the packaged devices to a system board. Bondability is enhanced for wire bonding or for flip chip mounting of the semiconductor die by the pre-plating process. In some examples, a bare copper leadframe is used, and after molding and sawing of semiconductor device packages formed with the bare copper leadframe, a post-molding plating, for example with tin, is used on the terminals and exposed die pad prior to surface mounting the devices.

FIG. 3B illustrates, in a plan view, a portion of a leadframe strip 350 for use the arrangements. A unit leadframe 3371, which is the same as 337 in FIG. 3A, is shown in a strip with another replicated unit leadframe 3372 connected together in saw street 338. Although only two unit leadframes are shown for explanation, in a production example the leadframe strip 350 can include several, tens or hundreds of unit leadframes, and as an alternative to the leadframe strip 350, an array or grid of unit leadframes can be used.

In FIG. 3B, a saw street 338 separates the replicated unit leadframes 3371, 3372. The leadframes are joined for die mounting and molding operations, and will be separated from one another in a sawing operation after molding is completed. In an example arrangement the saw street 338 is a spacing labeled D1 that is about 150 microns wide, and the inset distance for the terminals 311 is also about 150 microns, so that the terminals 311 have a spacing labeled D2 between the stepped edges of 450 microns. The die pads 313 are shown in a central portion of the unit leadframes 3371, 3372.

FIG. 3C illustrates, in a cross-sectional view, an individual terminal 311 of leadframe 337 to further describe details of the terminal. The terminal 311 is shown in FIG. 3C oriented with a device side surface 361 facing upwards, and the board side surface 371 facing downwards. When a semiconductor die is later mounted to the leadframe 337, a wire bond, or alternatively a conductive post connect, will contact the device side surface 361 of the terminal 311 to make an electrical connection to the semiconductor die, as shown and described below. When a completed semiconductor device package is then surface mounted to board using surface mount technology, solder will contact the device side surface 371 and form a solder joint between the semiconductor device package terminal 311, and a conductive land on the board. The terminal 311 is formed of the partially etched leadframe 337 and has two layers, an upper layer 353 that includes the device side surface 361, and a lower layer 355 that includes the board side surface 371. The upper layer 353 has a first exterior end 362, and the lower layer 355 has a second exterior end 364 that is inset from the first exterior end 362, forming a stepped edge for the terminal 311. The bottom of the upper layer 353 extending from the first exterior end 362 forms an inset portion 363 that is parallel to the device side surface 361. The inset portion 363 and the second exterior end 364 of the lower layer 355 form a wettable flank for the terminal 311 that, when a packaged device is mounted using a surface mounting process, provide a surface that solder can wet, increasing the volume of solder used in the solder joint that will be formed (when compared to terminals for non-wettable flank no-lead packages). When a semiconductor device package of the arrangements is surface mounted to a board, the solder joint that is then made is more visible from a top side of the mounted devices, improving the ability of visual inspection to confirm the presence and quality of the solder joints (when compared to devices formed without the use of the arrangements and mounted to a board). The corner 374 between the upper layer 353 and the lower layer 355 may be rounded or curved. When the upper layer 353 and the lower layer 355 are formed in two etching processes, even if an anisotropic etch is used, the corner will not be a 90-degree angle due to the nature of metal etching processes.

FIGS. 4A-4I illustrate, in a series of cross-sectional views, steps for forming a semiconductor device package of the arrangements and mounting it to a system board. FIG. 4EE illustrates, in a plan view, a portion of the molded semiconductor packages of FIG. 4E, FIG. 4FF illustrates, in another plan view, a portion of the molded semiconductor packages of FIG. 4F, and FIG. 4HH illustrates in a close-up view a portion of the molded semiconductor package of FIG. 4H.

In FIG. 4A, a leadframe strip 437 is shown in cross section. This leadframe strip is similar to leadframe 337 shown above. In the series of cross-sectional views of FIGS. 4A-4G, two unit leadframes 4371 and 4372 are shown. The two unit leadframes 4371 and 4372 are replicated unit leadframes, spaced by a saw street 438 that is between them. Each of the unit leadframes has terminals 411, which are similar to terminals 311 shown in FIGS. 3A-3C and a die pad 413, which is similar to die pads 313 shown in FIGS. 3A-3C

FIG. 4B illustrates the leadframe 437 of FIG. 4A with unit leadframes 4371 and 4372 spaced by saw street 438, now shown on a support 460. The support 460 is configured for a wire bonding operation in this example, and can include a heater block or heater blocks for the unit leadframes 4371 and 4372. A die attach material 465 such as a die attach film or die attach epoxy is shown deposited on the device side surface of the die pad 413 for each of the unit leadframes 4371 and 4372. The die attach material 465 can be, in an example, an electrically conductive die attach. Alternatively, the die attach material can be an insulator. The die attach can be deposited as a film or tape, by a “drop on demand” or inkjet process, or by a stencil. The die attach material may be cured, if needed.

FIG. 4C illustrates the elements shown in FIG. 4B after an additional pick and place process mounts semiconductor dies 405 on the die attach material 465 for each die pad 413. The semiconductor dies 405 are shown, in the illustrated example, mounted for a wire bonding connection with bond pads 408 facing upwards, as the elements are oriented in FIG. 4C. The semiconductor dies 405 are mounted on the die pad 413 for each unit leadframe 4371, 4372 in the example shown. In a production example, the leadframe 437 can be a strip of unit leadframes and may include tens or hundreds of unit leadframes. In another example, the unit leadframes can be arranged in a grid or matrix, and can include tens, or hundreds of unit leadframes to increase throughput.

FIG. 4D illustrates, in another cross-sectional view, the elements of FIG. 4C after a wire bonding operation forms wire bonds between the bond pads 408 and the terminals 411 of the leadframe 437. The bond wires 419 can be copper, palladium coated copper, gold, or silver bond wires, in an example, copper bond wires are used. In a wire bonding process, a capillary (not shown) of a wire bonding tool has the bond wire extending through a central opening. The capillary can be a ceramic or metallic material. The end of the bond wire is used with an electric arc or flame to form a molten ball. The capillary moves the bond wire with the molten bond over a bond pad and mechanical pressure is applied to push the molten ball onto the bond pad. To increase the bond strength, the process can be performed at an elevated temperature by using a heater block to heat the leadframe and the semiconductor dies for the wire bonding process. Ultrasonic energy can be applied to the capillary during bonding to vibrate the capillary and further increase the bond strength between the ball and the bond pad. After the ball bond is formed, the capillary is moved away from the bond pad while the bond wire is allowed to extend from the ball bond. The capillary is moved over a leadframe lead such as a terminal on the leadframe where the electrical connection is to be made. The capillary again can have ultrasonic energy applied to it to cause it to vibrate. The capillary pushes the wire onto the leadframe and forms a stitch bond. After the stitch bond is formed, the capillary moves upwards a short distance and a cutter cuts or breaks the bond wire, leaving a short tail extending from the stitch bond. This process is then repeated by forming a new molten ball on the end of the bond wire and moving the capillary to a new bond pad. In a wire bonding tool, this process can be automated and many wire bonds can be completed every second. In some wire bonding tools, a heater block is used to increase the temperature of the components, to increase bond strength. In some copper wire bonding processes, the wire bonding tool is in a closed chamber that is filled with an anoxic atmosphere, to reduce oxidation and tarnish of the copper wire when it is heated during the processing.

Note that while this illustrated example shows a face up, wire bonded semiconductor device package, in an alternative arrangement, a flip chip package can be formed with wettable flanks using the arrangements, see FIG. 5, semiconductor device package 500, described below.

FIG. 4D illustrates the semiconductor dies 405 on die attach 465 with bond wires 419 formed by a ball and stitch process between bond pads 408 on the semiconductor dies 405 and a device side surface of terminals 411.

FIG. 4E illustrates the elements of FIG. 4D in another cross-sectional view, after additional processing. In FIG. 4E, a mold compound 423 is shown covering the bond wires 419, the semiconductor dies 405, and portions of the leadframe 437, with the leads 411 partially covered. The mold compound 423 can be formed, in an example process, using a thermoset epoxy resin mold compound, sometimes referred to as “electronic mold compound” or “EMC”. In an example, a transfer mold is used. The leadframe 437 including the unit leadframes 4371, 4372 and the semiconductor dies 405, with bond wires 419, are placed in a mold tool. The mold tool has runners and vents and a pressure ram, so that mold compound can be forced into a mold chase that surrounds the leadframe 437. The mold compound can be provided as a solid pellet or in a powdered form. The mold compound can be heated to a liquid, and then under pressure from a mechanical ram, be pushed into the transfer mold, surrounding the devices and filling the mold chase. The mold compound 423 then can be cured to form a solid package body for the semiconductor device packages. The mold compound 423 has a device side surface 424. The terminals 411 are exposed from the mold compound 423 at the device side surface 424 of the mold compound 423, but most of the surface of the terminals 411 is covered by the mold compound 423 after molding.

FIG. 4EE illustrates a portion of the unit leadframes 4371, 4372 in a partial view looking from the board side surface 424, and showing mold compound 423. Die pads 413 and terminals 411 that have board side surfaces exposed from the mold compound 423. The mold compound covers the saw street 438 between the unit devices 4371, 4372, including portions of the terminals 411.

FIG. 4F illustrates, in another cross-sectional view, the elements of FIGS. 4E-4EE, in a further process. A laser 420 is shown being used to burn or ablate mold compound 423 from the terminals 411 using a laser beam 421. In FIG. 4F, the laser beam 422 is shown being directed to the saw street 438 to expose the terminals 411 from the mold compound 423, the laser beam 422 is directed to the devices at the device side surface 424 of the mold compound 423. The laser 420 will be pulsed and will burn or ablate the mold compound only where the terminals 411 are present, so that after a cleaning step, the outer sides of terminals 411 are exposed from the mold compound 423. The mold compound 423 that lies between the terminals is not impacted by the laser process, and remains unaffected.

FIG. 4FF illustrates a portion of the unit leadframes 4371, 4372 in a partial view looking from the board side surface 424, and showing mold compound 423, and die pads 413 after the laser burning process. FIG. 4FF illustrates the terminals 411 in saw street 438 after the laser beam 422 (see FIG. 4F) was applied to the mold compound. The board side surface at the outer edge of the terminals 411 is exposed from the mold compound 423 by the laser 420 (see FIG. 4F). The mold compound 423 between the terminals is not affected by the laser. Areas 412 show the openings formed by the laser in saw street 438 at the outer edge of the terminals 411.

FIG. 4G illustrates, in an additional cross-sectional view, the elements of FIGS. 4F-4FF in a sawing process. In FIG. 4G, the molded unit leadframes 4371 and 4372 are shown with the board side surface 424 of the mold compound 423 facing upwards. A rotating dicing saw 470 is shown over saw street 438. In the sawing process, devices will be placed on a sawing tape or support 466, and a mechanical blade will be used to saw between the devices along saw street 438. The saw will cut through the mold compound 423 and the leadframe 437, and will separate leads 411 from adjacent unit leadframes 4371, 4372 one from another, leaving a first exterior end of the terminals 411 coextensive with an edge of the mold compound 423. The terminals 411 will be exposed from the mold compound 423 on the board side surface and will have wettable flanks on the outer side surfaces. The saw 470 will separate the molded unit leadframes 4371 and 4372 into individual semiconductor device packages.

FIG. 4H illustrates, in a cross-sectional view, a semiconductor device package 400 formed by the sawing process of FIG. 4G. The illustrated example semiconductor device package 400 in FIG. 4H includes a wire bonded, face up semiconductor die 405 mounted on die attach material 465 to a die pad 413 of leadframe 437. The semiconductor die 405 is coupled to the terminals 411 by bond wires 419, which are mounted using a ball and stitch wire bonding process. Mold compound 423 covers the device side surface of the leadframe 437 including the semiconductor die 405, the bond wires 419, and portions of the terminals 411. The mold compound 423 does not cover the board side surface of the terminals 411, or the external flanks of the terminals 411, but does cover portions of the terminals 411 that are internal to the package. The die pad 413 also has a board side surface that is exposed from the mold compound on the board side surface 424 of the semiconductor device package 400.

A portion of the semiconductor device package 400 is shown in dashed lines in FIG. 4H is illustrated in FIG. 4HH. In FIG. 4HH, the close up illustrates an example terminal 411 formed in the arrangements, with the relationship of the mold compound 423 to the terminal 411 shown. Terminal 411 is similar to terminal 311 shown in FIG. 3C. The terminal 411 is partially covered by the mold compound 423 at device side surface 461, and the mold compound