106aa, 106ba, 106ca, and 106da; the signal divider 112b divides the input signal 104b into divider output signals 106ab, 106bb, 106cb, and 106db; the signal divider 112c divides the input signal 104c into divider output signals 106ac, 106bc, 106cc, and 106dc; and the signal divider 112d divides the input signal 104d into divider output signals 106ad, 106bd, 106cd, and 106dd.

A divided output signal 106 has substantially same characteristics as the corresponding input signal 104, e.g., is substantially a copy of the corresponding input signal 104. For example, the divided output signals 106aa, 106ba, 106ca, and 106da are substantially the same (e.g., substantially same phase and amplitude) as the corresponding input signal 104a; the divided output signals 106ab, 106bb, 106cb, and 106db are substantially the same (e.g., substantially same phase and amplitude) as the corresponding input signal 104b, and so on.

The switch matrix 102 further comprises a plurality of switches 116a, 116b, 116c, 116d. For example, a number of the switches 116a, . . . , 116d corresponds to a number of outputs of the switch matrix 102. For example, the switch matrix 102 has four outputs 108a, . . . , 108d, and hence, has four corresponding switches 116a, 116b, 116c, 116d.

As illustrated in FIG. 1, each switch 116 is configured to receive a corresponding divider output 106 from each of the signal dividers 112. For example, the switch 116a receives divider output 106aa from signal divider 112a, divider output 106ab from signal divider 112b, divider output 106ac from signal divider 112c, and divider output 106ad from signal divider 112d. Similarly, the switch 116b receives divider output 106ba from signal divider 112a, divider output 106bb from signal divider 112b, divider output 106bc from signal divider 112c, and divider output 106bd from signal divider 112d, and so on.

In one embodiment, each switch 116 is configured to output a corresponding output signal 108. For example, switch 116a outputs output signal 108a, switch 116b outputs output signal 108b, and so on. For example, each switch 116 switches one of the multiple divider outputs 106 received by the corresponding switch 116 as its corresponding output 108, based on the corresponding control signal 122. Thus example, the switches 116 are single pole-multiple throw switches, such as single pole—four throw (SP4T) switches in the example of FIG. 1, where each switch 116 has one output and four inputs. A control signal 122a controls the switching of the switch 116a, a control signal 122b controls the switching of the switch 116b, and so on.

For example, the switch 116a receives divider outputs 106aa, 106ab, 106ac, and 106ad, and switches any one of these divider output as its output 108a, e.g., based on the control signal 122a. Similarly, the switch 116b receives divider outputs 106ba, 106bb, 106bc, and 106bd, and switches any one of these divider output as its output 108b, e.g., based on a control signal 122b, and so on. Note that the control signal 122a for the switch 116a is illustrated in FIG. 1, and the control signals 122b, 122c, 122d provided to the switches 116b, 116c, 116d, respectively, are not illustrated in FIG. 1 for purposes of illustrative clarity.

During an operation of the switch matrix 102, and merely as an example, the control signals 122a, . . . , 122d may be configured such that the input signal 104a is to be routed and provided as output signal 108a, input signal 104a is also to be routed and provided as output signal 108b, input signal 104d is to be routed and provided as output signal 108c, and input signal 104c is to be routed and provided as output signal 108d. In such an example, the switch 116a may be controller by the control signal 122a, such that the switch 116a switches the divider output 106aa (which is a copy of the input signal 104a) as the output signal 108a.

Similarly, the switch 116b may be controller by the control signal 122b, such that the switch 116b may switch the divider output 106ba (which is a copy of the input signal 104a) as the output signal 108b. Also, the switch 116c may be controller by the control signal 122c, such that the switch 116c may switch the divider output 106cd (which is a copy of the input signal 104d) as the output signal 108c. Also, the switch 116d may be controller by the control signal 122d, such that the switch 116d may switch the divider output 106dc (which is a copy of the input signal 104c) as the output signal 108d. Thus, the switch matrix 102 may switch any of the input signals 104a, . . . , 104d to any of the output signals 108a, . . . , 108d, e.g., based on the control signals 122a, . . . , 122d.

In one embodiment, each switch 116 receives various low frequency or direct current (DC) signals, such as the control signals 122 described above, power signals 124 for powering or biasing the switch, and so on. For example, the power signal 124 to the switch 116a is illustrated in FIG. 1, and the power signal 124 to various other switches 116b, . . . , 116d are not illustrated for purposes of illustrative clarity.

In an example, the switch matrix 102 is part of a printed circuit board (PCB), or a printed wiring board (PWB), or an integrated circuit structure. For instance, in the context of a PCB or PWB, switch 116 and/or each divider 112 may be implemented as an integrated circuit die or a surface mount component mounted on a corresponding PCB or PWB surface or integrated within a corresponding layer of such a board. In the context of an integrated circuit, switch 116 and/or each divider 112 may be implemented as devices integrated within a corresponding layer of such an integrated circuit. The example of FIG. 1 illustrates the physical locations or physical layout of the switches 116 and the signal dividers 112 within the switch matrix structure, and the routing layout of the signals to and/or from the switches and signal dividers. Thus, in addition to being a circuit diagram, FIG. 1 is also a diagram (such as a plan or top-down view) of a physical routing layout 100 of the switch matrix 102.

For example, the switches 116a, . . . , 116d are arranged as a column 115 of switches (such as a single column 115 of switches). For example, a straight imaginary line may pass through two or more, such as all, the switches 116a, . . . , 116d within the column 115. More generally, the switches 116a, . . . , 116d are located between a first set of dividers (e.g., 112a-b) and a second set of dividers (e.g., 112c-d). By placing inputs (e.g., dividers) on edges or the switch matrix structure, and the outputs (e.g., switches) in the center of the switch matrix structure or otherwise between the inputs, more routing on similar layers without crossing any signal paths can be accomplished. This is in contrast to a scheme where all inputs are located on one side of the switch matrix structure, and all outputs on the other side.

As illustrated in FIG. 1, the column 115 has six sides, such as a first or left side 125a, a second or right side 125b opposite the first side 125a, a third side 125c perpendicular to the first side 125a, a fourth side 125d opposite the third side 125c, a fifth side that is above the plane of the page on which the figure is drawn, and a sixth side that is below the plane of the page on which the figure is drawn (where the fifth and sixth sides are not labelled in FIG. 1).

In one embodiment, in the routing layout 100 of the switch matrix 102, the dividers 112 are arranged on two sides of the column 115, such as on the first (or left) side 125a and the second (or right) side 125b, as illustrated in FIG. 1. Thus, for example, the dividers 112 are arranged on edges or periphery of the routing layout 100 of the switch matrix 102, and the switches 116 are arranged at or near a central section of the switch matrix 102. As illustrated in FIG. 1, there are no dividers on the four other sides (e.g., other than the first and second sides 125a, 125b) of the column 115.

For example, if even number of dividers 112 are included in the switch matrix 102 (such as four dividers in the example of FIG. 1), then half of the dividers 112a, 112b are on the first side 125a of the column 115, and the other half of the dividers 112c, 112d are on the second side 125b of the column 115.

In case odd number of dividers 112 (e.g., N number of dividers, where Nis an odd integer such as 3, 5, 7, or higher) are included in a switch matrix 102, then (N−1)/2 dividers 112 may be on one of the first side 125a or the second side 125b of the column 115, and the remaining (N+1)/2 of the dividers 112c, 112d may be on the other of the first side 125a or the second side 125b of the column 115. Thus, in this example, the number of dividers on the first side 125a and the number of dividers on the second side 125b of the column may differ by at most one. In one embodiment, the number of dividers on the first side 125a and the number of dividers on the second side 125b of the column 115 may differ by at most one, or at most two, or at most three.

There are several advantages of the above described layout of the dividers 116 on the two sides 125a, 125b and the column 115 of the switches 116 on the center, as will be described herein below.

FIG. 1 illustrates a single column 115 of switches 116. However, the switches 116 may be arranged in more than one column. FIG. 3C-3E illustrate various example arrangements of the switches 116 relative to the signal dividers 112 of a switch matrix 102, in accordance with an embodiment of the present disclosure. The routing of various signals is not illustrated in FIGS. 3C-3E, for purposes of illustrative clarity.

For example, FIG. 3C illustrates the switches 116a, . . . , 116d being arranged in a single column, such that a single imaginary line 370 (or a plane) passes through the switches 116a, . . . 116d, as described with respect to FIG. 1. As also illustrated in FIG. 1, in FIG. 3C some of the signal dividers 112 are on a first side of the group of switches 116a, . . . , 116d, and some other of the signal dividers 112 are on a second side of the group of switches 116a, . . . , 116d.

In FIG. 3D, the switches 116a, . . . , 116d are arranged in two columns, such that an imaginary line 380a (or a plane) passes through the switches 116d and 116b, and another imaginary line 380b (or a plane) passes through the switches 116c and 116a. As also illustrated in FIG. 3D, some of the signal dividers 112 are on a first side of the group of switches 116a, . . . , 116d, and some other of the signal dividers 112 are on a second side of the group of switches 116a, . . . , 116d.

In FIG. 3E, the switches 116a, . . . , 116d are arranged in a group or cluster and not in columns, such that each of imaginary lines 390a, 390b, 390c, 390d passes through a corresponding one of the switches 116a, . . . , 116d. As also illustrated in FIG. 3E, some of the signal dividers 112 are on a first side of the group of switches 116a, . . . , 116d, and some other of the signal dividers 112 are on a second side of the group of switches 116a, . . . , 116d.

In one embodiment, the divider output signals 106aa, . . . , 106dd and/or the output signals 108a, . . . , 108d are routed by a plurality of interconnect features, such as conductive vias and conductive lines that are extend through a plurality of routing layers. FIG. 3A illustrates planar circuit structure 300 comprising a plurality of routing layers 304a, 304b including a plurality of interconnect features 312 and 314 (such as conductive vias and conductive lines), wherein the interconnect features 312 and 314 route various signals of the switch matrix 102 of FIGS. 1 and 2, in accordance with an embodiment of the present disclosure. FIG. 3B illustrates another planar circuit structure 350 that is at least in part similar to the planar circuit structure 300 of FIG. 3A, where the planar circuit structure 350 of FIG. 3B has a higher number of routing layers 304a, 304b, 304c, 304d than the planar circuit structure 300 of FIG. 3A, in accordance with an embodiment of the present disclosure.

Thus, FIGS. 3A and 3B illustrate two different example planar circuit structures, each having corresponding number of routing layers. For example, the switch matrix 102 having the four input signals 104a, . . . , 104d and four output signals 108a, . . . , 108d can be implemented using two routing layers, such as routing layers 304a and 304b of FIG. 3A.

Referring to FIGS. 3A and 3B, each routing layer 304 comprises a corresponding dielectric material, and a plurality of conductive lines 314 and a plurality of conductive vias 312 (although only one such via 312 is illustrated in FIG. 3A) extending within the corresponding dielectric material. In one embodiment, the routing layers of FIGS. 3A and 3B may be implemented in a planar circuit board, such as a printed circuit board (PCB) or a printed wiring board (PWB). In another embodiment, the routing layers of FIGS. 3A and 3B may be implemented in an integrated circuit.

The conductive lines 314 extend in the horizon direction, e.g., in the plane of the x and y axis of FIGS. 3A and 3B. Merely as an example, in FIG. 3A, a conductive line 314a is illustrated to extend in the x axis direction, across the width of the paper in which FIG. 3A is drawn. Another a conductive line 314b is illustrated to extend in the y axis direction, in and out of the paper in which FIG. 3A is drawn.

FIGS. 3A and 3B also illustrate conductive vias 312 extending in vertical or z-axis direction. For example, a conductive via 312 couples two conductive lines in two different routing layers. Thus, a via 312 facilitates inter-routing layer transition, also referred to herein as via transition. For example, a via transition results in an interconnect feature extending between two adjacent routing layers.

As discussed, the input signals 104, the divider output signals 106, and the output signals 108 of FIG. 1 are RF signals having relatively high frequency. In an example, to avoid interference of signals among two routing layers and/or to reduce losses, each routing layer 304 is separated from an adjacent routing layer by a corresponding ground plane 308. For example, a single ground plane 308 is illustrated in FIG. 3A, and three ground planes 308a, 308b, 308c are illustrated in FIG. 3B. In an example, each ground plane 308 comprises a plane of conductive material, such as one or more metals and/or alloys thereof. In an example, a ground plane 308 comprises a metal plate or metal divider spanning in a horizontal plane between adjacent routing layers. In an example, a ground plane may, or may not, be on a lower surface of a lowermost routing layer and/or on an upper surface of an uppermost routing layer, although FIGS. 3A and 3B doesn't illustrate such a ground plane.

As illustrated in FIGS. 1 and 2, a conductive via 312 transitioning between two routing layers 304a and 304b has to pass through an opening within the ground plane 308b between the two routing layers 304a and 304b. For example, the ground plane 308b has an opening 310, through which the via 312 passes or extends, without contacting the ground plane 308b, as illustrated in FIGS. 3A and 3B.

In one embodiment, because of the high frequency nature of the signals routed by the interconnect features of the routing layers 304a, 304b, transitions between two routing layers 304a, 304b using a via 312, such as extending the via 312 through a ground plane 308, incurs some loss of signal strength. Thus, via transitions may be lossy in nature, and a higher number of such via transitions results in greater loss. For example, the via transitions are not impedance matched, and each via transition results in some corresponding loss in the signal strength. Also, a switch matrix 102 is likely to include several such via transitions, and a combination of such losses associated with the transition of the vias between adjacent routing layers and through the ground planes 308 can be significant.

As will be described below, in one embodiment, due to the layout of the switch matrix 102 illustrated in FIG. 1 (e.g., by arranging the switches in a column 115, and the signal dividers on two sides of the column of switches), a number of routing layers for implementing the switch matrix 102, as well a number of such via transitions, are minimized or at least reduced. For example, the number of routing layers and/or the number of via transitions used to implement the switch matrix 102 are optimal or sub-optimal, or at least reduced, resulting in relatively less loss of signal strength in the switch matrix 102.

Referring again to FIG. 1, some of the signal lines for routing the divider output signals 106 are illustrated using solid lines, while some other signal lines for routing the divider output signals 106 are illustrated using dotted lines. As indicated in the legends section of FIG. 1, the solid lines extend through a first routing layer, such as the routing layer 304a of FIG. 3A; and the dotted lines extend through a second routing layer, such as the routing layer 304b of FIG. 3A. For example, as described below, the switch matrix 102 of FIG. 1 may be implemented using only two routing layers, such as the routing layers 304a and 304b of FIG. 3.

Also, the dividers 112a and 112d are illustrated using solid lines, and the dividers 112b and 112c are illustrated using dotted lines, to indicate that the dividers 112a and 112d are on or above the routing layer 304a (e.g., mounted on or above the routing layer 304a), and the dividers 112b and 112c are on or below the routing layer 304c (e.g., mounted on or below the routing layer 304b). Similarly, the switches 116a, 116b, 116c, 116d are illustrated using solid lines, indicating that the switches 116a, 116b, 116c, 116d are on or above the routing layer 304a.

For example, the dividers 112a and 112d and the switches 116a, 116b, 116c, 116d may be surface mounted components or integrated circuit dies that are mounted on or above the routing layer 304a of FIG. 3A. Similarly, the dividers 112b and 112c may be surface mounted components or integrated circuit dies that are mounted on or below the routing layer 304b of FIG. 3A. In other examples, the dividers 112a and 112d and/or the switches 116a, 116b, 116c, 116d may be semiconductor devices that are formed on or above the routing layer 304a, and the dividers 112b and 112c may be semiconductor devices that are formed on or below the routing layer 304a of FIG. 3A. In yet other examples, dividers 112a and 112d may comprise passive components.

Because the dividers 112a and 112d are on the routing layer 304a, the input signals 104a and 104d are routed to the dividers 112a and 112d through the routing layer 304a, as illustrated using solid lines in FIG. 1. Also, as the divider 112a and the switches 116a, . . . , 116d are all on the routing layer 304a, the divider output signals 106aa, 106ba, 106ca, and 106da are routed from the divider 112a to the switches 116a, . . . , 116d, respectively, through the routing layer 304a, as illustrated using solid lines in FIG. 1.

Similarly, as the divider 112d and the switches 116a, . . . , 116d are all on the routing layer 304a, the divider output signals 106ad, 106bd, 106cd, and 106dd are routed from the divider 112d to the switches 116a, . . . , 116d, respectively, through the routing layer 304a, as illustrated using solid lines in FIG. 1.

However, the divider 112b is on the routing layer 304b and the switches 116a, . . . , 116d are on a different routing layer 304a. Accordingly, the divider output signals 106ab, 106bb, 106cb, and 106db are initially output in the routing layer 304b. For example, the divider output signals 106ab, 106bb, 106cb, and 106db being output by the divider 112b are illustrated using dotted lines. However, the divider output signals 106ab, 106bb, 106cb, and 106db received by the switches 116a, . . . , 116d, respectively, have to be in the routing layer 304a, as illustrated using solid lines.

Accordingly, for each of the divider output signals 106ab, 106bb, 106cb, and 106db, there is a corresponding via transition 120 from the routing layer 304b to the routing layer 304a. A via transition 120, as described above, implies that a via 312 transitions a signal from one routing layer to an adjacent routing layer. A specific example via transition 120 is labelled as 120a in FIG. 1. Thus, at the via transition 120a, the divider output signals 106db transitions from the routing layer 304b (illustrated using dotted line) to the routing layer 304a (illustrated using solid line), as illustrated in FIG. 1.

Thus, each of the divider output signals 106ab, 106bb, 106cb, and 106db from the divider 112b, and each of the divider output signals 106ad, 106bd, 106cd, and 106dd from the divider 112d undergoes a via transition, as illustrated by a transition of dotted-to-solid line in FIG. 1.

Similarly, output signals 108a, . . . , 108d output by the switches 116a, . . . , 116d, respectively, are initially routed through routing layer 304a (solid line), as the switches 116a, . . . 116d are on the routing layer 304a. However, in the example of FIG. 1, the output signals 108a, . . . 108d may be accessed from routing layer 304b. Accordingly, each of the output signals 108a, . . . 108d also include corresponding via transitions 120, from routing layer 304a (solid line) to routing layer 304b (dotted line).

Note that the routing layout 100 of FIG. 1 is an actual layout of various signal lines and components of the switch matrix 102, in addition to being a circuit diagram of the switch matrix 102. The routing layout 100 also includes crossing of two lines (also referred to herein as cross-overs), generally labelled as cross-overs 121. However, in each cross-over, the two signal lines that cross each other are in different routing layers, and hence, are not electrically shorted (note that the ground plane 308 between the two routing layers prevents, or at least reduces, interference between the two crossed signal lines carrying high frequency signals, see FIGS. 3A and 3B). For example, a specific cross-over labelled as 121a shows a cross-over between a signal line 106cc in the routing layer 304b (dotted line) and a signal line 106ad in the routing layer 304a (dotted line).

In one embodiment, arranging the dividers 112 on two sides of the column 115 of the switches 116 (e.g., arranging the dividers 112 on edges or periphery of the routing layout 100 and the switches 116 at or near a central section of the routing layout 100) reduces a number of routing layers for implementing the switch matrix 102, as well as reduces a number of via transitions 120. This results in relatively less loss of signal strength in the switch matrix 102.

For example, if the dividers 112a, . . . , 112d were arranged on only one side of the column of switches 116a, . . . , 116d, then four routing layers would have been needed to effectively route the divider output signals 106 from the various dividers 112 to the various switches 116. Also, such an arrangement would have resulted in relatively greater number of via transitions. For example, in such a routing layout (e.g., where the dividers are on only one side of the switches), a number of routing layers N_Lmay be equal to a number of outputs N_O, where N_Ois four in the switch matric 102. Thus, in such a routing layout (e.g., where the dividers are on only one side of the switches):

$\begin{matrix} N_{L} = N_{O} & Equation 1 \end{matrix}$

However, in the routing layout 100 illustrated in FIG. 1 and described above, reduced number of routing layers are needed to route the divider output signals from the various dividers 112 to the various switches 116, along with relatively smaller number of via transitions. In an example, in the routing layout of the switch matrix described herein (e.g., where the dividers are divided on two sides of the column of switches), the number of routing layers N_L, the number of output signals N_O, and a number of the input signals N_iare related as follows:

$\begin{matrix} N_{L} = 1, for N_{O} = 1, 2 & Equation 2 \end{matrix}$

$\begin{matrix} N_{L} = ⌈ N_{i} / 2 ⌉, for N_{O} \geq 2 & Equation 3 \end{matrix}$

Note that ┌ . . . ┐ represents the ceiling function.

Thus, for the switch matrix 102, the number of outputs N_Ois four and the number of inputs N_iis also four, and hence, in accordance with equation 3, the number of routing layers N_Lis ┌N_i/2┐, or two. Accordingly, in FIG. 1, two routing layers 304a and 304b are sufficient to route RF signals of the switch matrix 102, such as the divider output signals 106, the input signals 104, and the output signals 108.

Note that the routing layout 100 of FIG. 1 (as well as routing layouts 400, 500, and 600 described below) illustrate routing of the RF signals, such as the divider output signals 106, the input signals 104, and the output signals 108. Although FIG. 1 illustrates non-RF signals, such as control signals 122 and DC power/biasing signals 124, routing of such low frequency or DC signals are not illustrated in the routing layout 100 (as well as subsequent routing layouts 400, 500, and 600 described below). This is because a number of routing layers and/or a number of via transitions are critical for RF signals, as a relatively greater number of routing layers and/or via transitions can result in higher loss for RF signals, but may not significantly affect DC or low frequency signals. Accordingly, the low frequency or DC signals (such as the control signals 122 and/or DC power/biasing signals 124) may be routed using a plurality of routing layers, at least some of which may be same as (or different from) the routing layers used for routing RF signals (e.g., the routing layers of FIGS. 3A and 3B). Because the number of routing layers and/or the number of via transitions are relatively less critical for low frequency or DC signals (e.g., compared to that of the RF signals), the routing of the low frequency or DC signals may be designed using available techniques for designing routing layouts for such low frequency or DC signals.

FIG. 4 illustrates a routing layout 400 of an example switch matrix 402 having eight input signals 404a, . . . , 404h, four output signals 408a, . . . , 408d, and four routing layers, in accordance with an embodiment of the present disclosure. Similar to the routing layout of FIG. 1, in the routing layout 400, the signal dividers 412a, . . . , 412h are arranged on two sides of a column 415 of the switches 416a, . . . , 416d, such that some dividers 412a, . . . , 412d are on a first or left side of the switches 416a, . . . , 416d, and the remaining dividers 412e, . . . , 412h are on a second or right side of the switches 416a, . . . , 416d. Thus, for example, the dividers 412 are arranged on edges or periphery of the routing layout 400 of the switch matrix 402, and the switches 416 are arranged at or near a central section of the switch matrix 402.

In the switch matrix 402, the number of outputs N_Ois four, and the number of inputs N_iis eight. Thus, in accordance with equation 3 described above, the number of routing layers N_Lto be used may be at least ┌8/2┐, or 4. Thus, at least four routing layers may be used for routing the RF signals (such as the divider output signals, the input signals, and the output signals) of the switch matrix 400.

As illustrated in the legends section of FIG. 4, signal lines extending through a first routing layer (such as routing layer 304a of FIG. 3B) are illustrated using solid lines, signal lines extending through a second routing layer (such as routing layer 304b of FIG. 3B) are illustrated using dashed lines, signal lines extending through a third routing layer (such as routing layer 304c of FIG. 3B) are illustrated using thick solid lines, and signal lines extending through a fourth routing layer (such as routing layer 304d of FIG. 3B) is illustrated using dotted lines.

Note that although there are more than two routing layers (such as four routing layers) in the routing layout 400 of FIG. 4, individual ones of the dividers 412 and the switches 416 can be either on an uppermost routing layer or a lowermost routing layer. For example, the dividers 412a, 412b, 412g, 412h and the switches 416a, . . . , 416d are on the uppermost routing layer 304a, and the dividers 412c, 412d, 412e, and 412f are on the lowermost routing layer 304d.

Thus, although the dividers 412a, 412b, 412c, 412d are on the same left side of the column of switches 416, all the dividers 412a, 412b, 412c, 412d are not on the same horizontal plane. For example, the dividers 412a, 412b are on a horizontal plane above the uppermost routing layer, and the dividers 412c, 412d are on another horizontal plane below the uppermost routing layer. The routing layout 400 of FIG. 4 will be apparent, based on the description above with respect to FIGS. 1-3.

FIG. 5 illustrates a routing layout 500 of an example switch matrix 502 having four input signals 504a, . . . , 504d, eight output signals 508a, . . . , 508h, and two routing layers, in accordance with an embodiment of the present disclosure. Similar to the routing layout of FIG. 1, in the routing layout 500, the signal dividers 512a, . . . , 512d are arranged on two sides of a column of the switches 516a, . . . , 516h, such that half the dividers 512a, 512b are on a first side of the switches 516a, . . . 516h and the remaining half the dividers 512c, 512d are on a second side of the switches 516a, . . . 516h. Thus, for example, the dividers 512 are arranged on edges or periphery of the routing layout 500 of the switch matrix 502, and the switches 516 are arranged at or near a central section of the switch matrix 502.

In the switch matrix 502, the number of outputs N_Ois eight, and the number of inputs N_iis four. Thus, in accordance with equation 3, the number of routing layers N_Lto be used for routing RF signals is at least ┌4/2┐, or 2. Thus, at least two routing layers may be used for routing the RF signals (such as the divider output signals, the input signals, and the output signals) of the switch matrix 500. As illustrated in the legends section of FIG. 5, signal lines extending through a first routing layer (such as routing layer 304a of FIG. 3B) are illustrated using solid lines, and signal lines extending through a second routing layer (such as routing layer 304b of FIG. 3B) are illustrated using dotted lines. The routing layout 500 of FIG. 5 will be apparent, based on the description above with respect to FIGS. 1-3.

FIG. 6 illustrates a routing layout 600 of an example switch matrix 602 having six input signals 604a, . . . , 604f, four output signals 608a, . . . , 608d, and three routing layers, in accordance with an embodiment of the present disclosure. Similar to the routing layout 100 of FIG. 1, in the routing layout 600, the signal dividers 612a, . . . , 612f are arranged on two sides of a column of the switches 616a, . . . , 616d, such that some of the dividers 612a, 612b, 612c are on a first side of the switches 616a, . . . , 616d and the remaining dividers 612d, 612e, 612f are on a second side of the switches 616a, . . . , 616d. Thus, for example, the dividers 612 are arranged on edges or periphery of the routing layout 600 of the switch matrix 602, and the switches 616 are arranged at or near a central section of the switch matrix 602.

In the switch matrix 602, the number of outputs N_Ois four, and the number of inputs N_iis six. Thus, in accordance with equation 3, the number of routing layers N_Lto be used may be ┌6/2┐, or 3. Thus, three routing layers may be used for routing the RF signals (such as the divider output signals, the input signals, and the output signals) of the switch matrix 600. As illustrated in the legends section of FIG. 6, signal lines extending through a first routing layer are illustrated using solid lines, signal lines extending through a second routing layer are illustrated using dashed lines, and signal lines extending through a third routing layer are illustrated using dotted lines.

Note that although there are more than two routing layers in the routing layout 600 of FIG. 6, individual ones of the dividers 612 and the switches 616 can be either on an uppermost routing layer or a lowermost routing layer. For example, the dividers 612a, 612b, 612e, 612f and the switches 616a, . . . , 616d are on the first routing layer, and the dividers 612c, 612d are on the second routing layer, where the first routing layer is one of an uppermost or lowermost routing layer, and where the second routing layer is the other of the uppermost the lowermost routing layer. The routing layout 600 of FIG. 6 will be apparent, based on the description above with respect to FIGS. 1-3.

FIG. 7 illustrates a flowchart depicting a method 700 of forming a switch matrix (such as any of the switch matrices 102, 402, 502, or 602 of FIGS. 1 and 4-6), in accordance with an embodiment of the present disclosure.

Referring to FIG. 7, the method 700 includes, at 704, forming a plurality of routing layers (e.g., routing layers illustrated in FIGS. 3A and 3B). In an example, the plurality of routing layers include at least a first routing layer and a second routing layer, such as routing layers