Transistor 401 is coupled between power supply node 306 and node 107, and is controlled by control signal 111. In various embodiments, transistor 401 is configured to adjust a conductance between power supply node 306 and node 107, thereby changing a value of output current 110 which, in turn, adjusts the value of reference voltage 109. For example, as a voltage level of control signal 111 decreases, transistor 401 is configured to increase the conductance between power supply node 306 and node 107, increasing output current 110.

In various embodiments, transistor 401 may be implemented using one or more p-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices.

Turning to FIG. 5, a block diagram of another embodiment of a voltage reference circuit is depicted. As illustrated, voltage reference circuit 500 includes amplifier circuit 501, driver circuit 502, and divider circuit 503.

Driver circuit 502 is configured to generate output current 510 using control signal 511. In various embodiments, driver circuit 502 is configured to source output current 510 to node 514. In various embodiments, driver circuit 502 may correspond to driver circuit 102 as depicted in FIG. 4.

Divider circuit 503 is coupled to node 514 and is configured to generate feedback voltage 512, feedback voltage 513, and reference voltage 509 using output current 510. As described below, divider circuit 503 may be implemented as a resistive voltage divider circuit configured to generate reference voltage 509, feedback voltage 512, and feedback voltage 513 as output current 510 flows through one or more resistors included in the resistive voltage divider circuit. In some embodiments, the use of two feedback voltages, rather than using a single feedback voltage and the reference voltage may allow for additional scaling of the reference voltage to achieve a desired value for the reference voltage.

Amplifier circuit 501 is configured to generate control signal 511 using feedback voltage 512 and feedback voltage 513. In various embodiments, amplifier circuit 501 may be implemented as an asymmetric differential amplifier circuit, where an asymmetry of amplifier circuit 501 is based on a difference between transistor threshold voltage 504 and transistor threshold voltage 505. In some cases, amplifier circuit 501 may correspond to differential amplifier circuit 300 as depicted in FIG. 3.

A block diagram of divider circuit 503 is depicted in FIG. 6. As illustrated, divider circuit 503 includes resistors 601-603. In various embodiments, the increased number of resistors in divider circuit 503 as compared to divider circuit 103 allows for increased scaling of the value of reference voltage 509. Resistor 601 is coupled between node 514 and node 507. In a similar fashion, resistor 602 is coupled between node 507 and node 508, while resistor 603 is coupled between node 508 and ground supply node 203.

As output current 510 flows from driver circuit 502 into ground supply node 203, respective voltage drops are developed across resistors 601-603, generating reference voltage 509, feedback voltage 513, and feedback voltage 512, respectively.

Output node 506 can be coupled to different points within resistor 601 based on trim control 603. In some embodiments, a value for trim control 603 is determined during a post-manufacture test operation and stored in a one-time programmable memory or other suitable non-volatile memory circuit. Based on which of the different points within resistor 601 node 506 is coupled, the value of reference voltage 509 can be adjusted.

Resistors 601-603 may be implemented using metal, polysilicon, or any other suitable material available on a semiconductor manufacturing process. In other embodiments, resistors 601-603 may be implemented using active metal-oxide semiconductor field-effect transistors (MOSFETs), Fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAAFETs), or any other suitable transconductance devices biased to provide a desired amount of resistance.

To summarize, various embodiments of a voltage reference circuit are disclosed. Broadly speaking, a voltage reference circuit includes a driver circuit, a divider circuit, and an asymmetric differential amplifier circuit. The driver circuit is configured to generate an output current using a control signal, and the divider circuit is configured to generate a feedback voltage and a reference voltage using the output current. The asymmetric differential amplifier circuit includes a first transistor with a first threshold voltage and a second transistor with a second threshold voltage different than the first threshold voltage. The asymmetric differential amplifier is configured to generate the control signal using the reference voltage, the feedback voltage, and a difference between a first threshold voltage of a first transistor and a second threshold voltage of a second transistor.

Turning to FIG. 7, a flow diagram depicting an embodiment of a method for operating a voltage reference circuit is illustrated. The method, which may be applied to various voltage reference circuits, e.g., voltage reference circuit 100, begins in block 701.

The method includes generating, by a driver circuit, an output current using a control signal (block 702). In various embodiments, the driver circuit includes a transistor coupled between a power supply node and a reference node. In such cases, the method may further include adjusting a conductance of the transistor using the control signal.

The method further includes generating, by a divider circuit using the output current, a reference voltage and a feedback voltage (block 703). In various embodiments, the divider circuit includes at least a first resistor and a second resistor coupled, in series, between the driver circuit and a ground supply node. In other embodiments, the method may further include adjusting, based on a trim signal, a value of at least one of either the first resistor or the second resistor.

The method also includes asymmetrically amplifying, by a differential amplifier circuit, a difference between the reference voltage and the feedback voltage to generate the control signal (block 704). In various embodiments, the differential amplifier circuit includes a first transistor with a first threshold voltage and a second transistor with a second threshold voltage different than the first threshold voltage.

In some embodiments, the first transistor and the second transistor are metal-oxide semiconductor field-effect transistors. In such cases, asymmetrically amplifying the difference between the reference voltage and the feedback voltage includes operating the first transistor and the second transistor in a sub-threshold region of operation.

In other embodiments, asymmetrically amplifying the difference between the reference voltage and the feedback voltage includes establishing a first current density in the first transistor and a second current density in the second transistor. In such cases, the second current density is different than the first current density. In various embodiments, a first width-to-length ratio of the first transistor is different than a second width-to-length ratio of the second transistor. When employing different width-to-length ratios, establishing the first current density in the first transistor and the second current density in the second transistor includes providing, by a current mirror circuit, a first current to the first transistor and a second current to the second transistor, where a first value of the first current is the same as a second value of the second current.

In other embodiments, a first width-to-length ratio of the first transistor may be the same as a second width-to-length ratio of the second transistor. In such cases, establishing the first current density in the first transistor and the second current density in the second transistor includes providing, by a current mirror circuit, a first current to the first transistor and a second current to the second transistor, where a first value of the first current is different than a second value of the second current. The method concludes in block 705.

A block diagram of a system-on-a-chip (SoC) is illustrated in FIG. 8. In the illustrated embodiment, SoC 800 includes processor circuit 801, memory circuit 802, analog/mixed-signal circuits 803, and input/output circuits 804 each of which is coupled to communication bus 805. In various embodiments, SoC 800 may be configured for use in a desktop computer, server, or in a mobile computing application such as, e.g., a tablet, laptop computer, or wearable computing device.

Processor circuit 801 may, in various embodiments, be representative of a general-purpose processor that performs computational operations. For example, processor circuit 801 may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA).

Memory circuit 802 may, in various embodiments, include any suitable type of memory such as a Dynamic Random-Access Memory (DRAM), a Static Random-Access Memory (SRAM), a Read-Only Memory (ROM), an Electrically Erasable Programmable Read-only Memory (EEPROM), or a non-volatile memory, for example. It is noted that although a single memory circuit is illustrated in FIG. 8, in other embodiments, any suitable number of memory circuits may be employed.

Analog/mixed-signal circuits 803 may include a crystal oscillator circuit, a phase-locked loop (PLL) circuit, an analog-to-digital converter (ADC) circuit, and a digital-to-analog converter (DAC) circuit (all not shown). In other embodiments, analog/mixed-signal circuits 803 may be configured to perform power management tasks with the inclusion of on-chip power supplies and voltage regulators. In some embodiments, analog/mixed-signal circuits 803 may include voltage reference circuit 100 as depicted in FIG. 1.

Input/output circuits 804 may be configured to coordinate data transfer between SoC 800 and one or more peripheral devices. Such peripheral devices may include, without limitation, storage devices (e.g., magnetic or optical media-based storage devices including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral devices. In some embodiments, input/output circuits 804 may be configured to implement a version of Universal Serial Bus (USB) protocol or IEEE 1394 (Firewire®) protocol.

Input/output circuits 804 may also be configured to coordinate data transfer between SoC 800 and one or more devices (e.g., other computing systems or integrated circuits) coupled to SoC 800 via a network. In one embodiment, input/output circuits 804 may be configured to perform the data processing necessary to implement an Ethernet (IEEE 802.3) networking standard such as Gigabit Ethernet or 10-Gigabit Ethernet, for example, although it is contemplated that any suitable networking standard may be implemented. In some embodiments, input/output circuits 804 may be configured to implement multiple discrete network interface ports.

Turning now to FIG. 9, various types of systems that may include any of the circuits, devices, or systems discussed above are illustrated. System or device 900, which may incorporate or otherwise utilize one or more of the techniques described herein, may be utilized in a wide range of areas. For example, system or device 900 may be utilized as part of the hardware of systems such as a desktop computer 910, laptop computer 920, tablet computer 930, cellular or mobile phone 940, or television 950 (or set-top box coupled to a television).

Similarly, disclosed elements may be utilized in a wearable device 960, such as a smartwatch or a health-monitoring device. Smartwatches, in many embodiments, may implement a variety of different functions for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device may also be designed solely to perform health-monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to an emergency medical service, etc. Other types of devices are also contemplated, including devices worn on the neck, devices implantable in the human body, glasses or a helmet designed to provide computer-generated reality experiences such as those based on augmented and/or virtual reality, etc.

System or device 900 may also be used in various other contexts. For example, system or device 900 may be utilized in the context of a server computer system, such as a dedicated server or on shared hardware that implements a cloud-based service 970. Still further, system or device 900 may be implemented in a wide range of specialized everyday devices, including devices 980 commonly found in the home such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Elements may also be implemented in various modes of transportation. For example, system or device 900 could be employed in the control systems, guidance systems, entertainment systems, etc. of various types of vehicles 990.

The applications illustrated in FIG. 9 are merely exemplary and are not intended to limit the potential future applications of disclosed systems or devices. Other example applications include, without limitation: portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.

FIG. 10 is a block diagram illustrating an example of a non-transitory computer-readable storage medium that stores circuit design information, according to some embodiments. In the illustrated embodiment, semiconductor fabrication system 1020 is configured to process design information 1015 stored on non-transitory computer-readable storage medium 1010 and fabricate integrated circuit 1030 based on design information 1015.

Non-transitory computer-readable storage medium 1010 may comprise any of various appropriate types of memory devices or storage devices. Non-transitory computer-readable storage medium 1010 may be an installation medium, e.g., a CD-ROM, floppy disks, or tape device; a computer system memory or random-access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory such as a Flash or magnetic media (e.g., a hard drive), or optical storage; registers, or other similar types of memory elements, etc. Non-transitory computer-readable storage medium 1010 may include other types of non-transitory memory as well as combinations thereof. Non-transitory computer-readable storage medium 1010 may include two or more memory mediums, which may reside in different locations, e.g., in different computer systems that are connected over a network.

Design information 1015 may be specified using any of various appropriate computer languages, including hardware description languages such as, without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 1015 may be usable by semiconductor fabrication system 1020 to fabricate at least a portion of integrated circuit 1030. The format of design information 1015 may be recognized by at least one semiconductor fabrication system, such as semiconductor fabrication system 1020, for example. In some embodiments, design information 1015 may include a netlist that specifies elements of a cell library, as well as their connectivity. One or more cell libraries used during logic synthesis of circuits included in integrated circuit 1030 may also be included in design information 1015. Such cell libraries may include information indicative of device or transistor level netlists, mask design data, characterization data, and the like, of cells included in the cell library.

Integrated circuit 1030 may, in various embodiments, include one or more custom macrocells, such as memories, analog or mixed-signal circuits, and the like. In such cases, design information 1015 may include information related to included macrocells. Such information may include, without limitation, schematics capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to graphic data system (GDSII), or any other suitable format.

Semiconductor fabrication system 1020 may include any of various appropriate elements configured to fabricate integrated circuits. This may include, for example, elements for depositing semiconductor materials (e.g., on a wafer, which may include masking), removing materials, altering the shape of deposited materials, modifying materials (e.g., by doping materials or modifying dielectric constants using ultraviolet processing), etc. Semiconductor fabrication system 1020 may also be configured to perform various testing of fabricated circuits for correct operation.

In various embodiments, integrated circuit 1030 is configured to operate according to a circuit design specified by design information 1015, which may include performing any of the functionality described herein. For example, integrated circuit 1030 may include any of various elements shown or described herein. Further, integrated circuit 1030 may be configured to perform various functions described herein in conjunction with other components. Further, the functionality described herein may be performed by multiple connected integrated circuits.

As used herein, a phrase of the form “design information that specifies a design of a circuit configured to . . . ” does not imply that the circuit in question must be fabricated in order for the element to be met. Rather, this phrase indicates that the design information describes a circuit that, upon being fabricated, will be configured to perform the indicated actions or will include the specified components.

The present disclosure includes references to “an “embodiment” or groups of “embodiments” (e.g., “some embodiments” or “various embodiments”). Embodiments are different implementations or instances of the disclosed concepts. References to “an embodiment,” “one embodiment,” “a particular embodiment,” and the like do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the disclosure.

This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all implementations of these embodiments will necessarily manifest any or all of the potential advantages. Whether an advantage is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are a number of reasons why an implementation that falls within the scope of the claims might not exhibit some or all of any disclosed advantages. For example, a particular implementation might include other circuitry outside the scope of the disclosure that, in conjunction with one of the disclosed embodiments, negates or diminishes one or more the disclosed advantages. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation techniques or tools) could also negate or diminish disclosed advantages. Even assuming a skilled implementation, realization of advantages may still depend upon other factors such as the environmental circumstances in which the implementation is deployed. For example, inputs supplied to a particular implementation may prevent one or more problems addressed in this disclosure from arising on a particular occasion, with the result that the benefit of its solution may not be realized. Given the existence of possible factors external to this disclosure, it is expressly intended that any potential advantages described herein are not to be construed as claim limitations that must be met to demonstrate infringement. Rather, identification of such potential advantages is intended to illustrate the type(s) of improvement available to designers having the benefit of this disclosure. That such advantages are described permissively (e.g., stating that a particular advantage “may arise”) is not intended to convey doubt about whether such advantages can in fact be realized, but rather to recognize the technical reality that realization of such advantages often depends on additional factors.

Unless stated otherwise, embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of claims that are drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative rather than restrictive, absent any statements in the disclosure to the contrary. The application is thus intended to permit claims covering disclosed embodiments, as well as such alternatives, modifications, and equivalents that would be apparent to a person skilled in the art having the benefit of this disclosure.

For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of other dependent claims where appropriate, including claims that depend from other independent claims. Similarly, features from respective independent claims may be combined where appropriate.

Accordingly, while the appended dependent claims may be drafted such that each depends on a single other claim, additional dependencies are also contemplated. Any combinations of features in the dependent claims that are consistent with this disclosure are contemplated and may be claimed in this or another application. In short, combinations are not limited to those specifically enumerated in the appended claims.

Where appropriate, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims of another format or statutory type (e.g., method).

Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. Public notice is hereby given that the following paragraphs, as well as definitions provided throughout the disclosure, are to be used in determining how to interpret claims that are drafted based on this disclosure.