11 and F12 is greater than a width W12 of a trench T12 between the fin structures F12 and F13, and the width W11 is substantially the same as a width W13 of a trench T13 between the fin structures F13 and F14. In some embodiments, the four fin structures F11, F12, F13 and F14 as a unit are repeatedly arranged over the substrate 100, and a trench formed between the fin structure F14 and the adjacent fin structure F11 has a width, which is substantially the same as the width W12.

Cross-referencing FIGS. 1 and 4, the method M10 further includes: (O14) forming isolation 120 around the fin structures F10 and over the unetched portion 102 of the substrate 100. It is noted that FIG. 4, and subsequent FIGS. 5-13, provide a cross-sectional view of a portion (three fin structures F12, F13, and F14) of the device 200 of FIG. 3 along a Y-Z plane for clarity and ease of description.

In exemplary embodiments, the isolation 120 may be considered to be shallow trench isolation (STI) features in trenches adjacent to each fin structures F10. The STI features 120 may be formed by first filling the trenches around each fin structures F10 with a dielectric material layer to cover top surfaces and sidewalls of the fin structures F10 (not shown). The dielectric material layer may include one or more dielectric materials. Suitable dielectric materials for the dielectric layer may include silicon oxides, silicon nitrides, silicon carbides, fluorosilicate glass (FSG), low-K dielectric materials, and/or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique including thermal growth, flowable CVD (FCVD), HDP-CVD, PVD, ALD, and/or spin-on techniques. The dielectric material layer is then planarized by using, for example, chemical mechanical planarization (CMP), until top surfaces of the mask layer (not shown) are revealed, and the dielectric material layer is recessed to form the shallow trench isolation (STI) features 120, as shown in FIG. 4. In the illustrated embodiment, the STI features 120 are formed on the substrate 100. Any suitable etching technique may be used to recess the isolation features 120 including dry etching, wet etching, RIE, and/or other etching methods, and in an exemplary embodiment, an anisotropic dry etching is used to selectively remove the dielectric material of the isolation features 120 without etching the fin structures F10. The mask layer may also be removed before, during, and/or after the recessing of the isolation features 120. In some embodiments, the mask layer is removed by the CMP process performed prior to the recessing of the isolation features 120. In some embodiments, the mask layer is removed by an etchant used to recess the isolation features 120.

Cross-referencing FIGS. 1 and 5, the method M10 further includes: (O15) selectively growing a semiconductor liner 130 over the fin structures F10. In exemplary embodiments, the semiconductor liner 130 may be SiGe.

Further, the method M10 includes: (O16) conformally depositing a spacer layer 140 over the fin structures F10 and STI features 120. In exemplary embodiments, the spacer layer 140 may include spacer material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN films, silicon oxycarbide, SiOCN films, and/or combinations thereof. In some embodiments, the spacer layer 140 includes multiple layers, such as a liner layer and a main spacer layer. By way of example, the spacer layer 140 may be formed by depositing spacer material using processes such as a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process respectively.

Cross-referencing FIGS. 1 and 6, the method M10 further includes: (O17) depositing a dielectric material 150 over the fin structures F10. In exemplary embodiments, the dielectric material may be silicon oxide. In exemplary embodiments, the dielectric material 150 is blanket deposited.

Further, method M10 includes (O18) recessing the dielectric material 150 and spacer layer 140 over the fin structures F10, as shown in FIG. 6. As a result, gaps 155 are formed between and laterally adjacent the upper portions of the fin structures F10. The gaps 155 are formed with a vertical height H1, in the Z-direction. In exemplary embodiments, height H1 is substantially equal to the sum of the vertical thickness of the top layer 115 and the semiconductor liner 130.

Cross-referencing FIGS. 1 and 7, method M10 continues at operation O19 with depositing a high dielectric constant material 160, i.e., a high-k or high-k material, over the fin structures F10. Specifically, the high-k material 160 may be deposited on the dielectric material 150, spacer layer 140, and semiconductor liner 130. As used herein, high dielectric constant material has a dielectric constant greater than 3.9. In exemplary embodiments, the dielectric constant of the high-k material 160 is greater than 7. In exemplary embodiments, the high-k material 160 comprises a metal oxide, such as hafnium oxide (HfO2).

In exemplary embodiments, the high-k material 160 may be deposited by atomic layer deposition (ALD). Other deposition processes may be used, such as plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), plasma enhanced atomic layer deposition method (PEALD), or similar deposition processes.

In exemplary embodiments, the high-k material 160 is conformally deposited. Thus, the high-k material 160 may be formed with a substantially level or planar surface 161 in high pattern density regions of the device 200, such as over fin structure F12, trench T12, and fin structure F13. Further, the high-k material 160 may be formed with a dip or recess 162 over low pattern density regions of the device 200, such as over trench T13 between fin structure F13 and fin structure F14.

As shown, lower portions 165 of the high-k material 160 are located laterally adjacent to and/or between adjacent fin structures F10 and an upper portion 168 of the high-k material 160 is located above, i.e., at a greater height over the substrate 100 than, the fin structures F10.

Cross-referencing FIGS. 1 and 8, method M10 continues at operation O20 with forming a capping layer 170 over the high-k material 160. In exemplary embodiments, the capping layer 170 is dielectric layer, such as a silicon oxide (SiO2) layer. In exemplary embodiments, the capping layer 170 is provided to improve topography of the high-k material 160. In exemplary embodiments, the capping layer 170 is conformally deposited. For example, the capping layer 170 may be deposited by plasma enhanced chemical vapor deposition (PECVD) of another suitable process.

Cross-referencing FIGS. 1 and 9-11, method M10 further includes at operation O21 performing a chemical mechanical planarization (CMP) process. Specifically, the exemplary CMP process includes three stages. In a first stage and as shown in FIG. 9, the CMP process selectively etches the capping layer 170 and lands on the high-k material 160. A portion of the capping layer 170 may remain in the recess 162. In exemplary embodiments, the first stage of the CMP process may be performed with a chemistry that provides for a removal rate of the silicon oxide capping layer 170 of about 1000 Angstrom per minute and a selectivity of 50. Further, the amount of high-k material removed by the first stage of the CMP process may be limited to less than 1 nanometer. In exemplary embodiments, silicon oxide dishing is 4 nanometers, with a space of 0.3 micrometers.

As shown in FIG. 10, a second stage of the CMP process is highly selective to etching the capping layer 170 and the high-k material 160 and lands on the semiconductor material of the fin structure F10, i.e., either on the semiconductor liner 130 (as shown) or on the top layer 115.

In exemplary embodiment, the second stage of the CMP process is performed with a slurry formula comprising silica (SiO2) abrasive. Further, in exemplary embodiments, the silica-based slurry is used with HNO3. In exemplary embodiments, the pH of the slurry formula is from 1 to 5, such as from 2 to 4, for example from 2.5 to 3.5, such as a pH of 3. In exemplary embodiments, the second stage of the CMP process provides a controlled pH to increase a removal rate of the high-k material while suppressing a removal rate of the fin structures. As a result, the second stage of the CMP process is highly selective to etching the high-k material.

As shown in FIG. 11, a third stage of the CMP process is then performed to provide for selective height control of the high-k material 160. In exemplary embodiments, the third stage is non-selective to etch the high-k material 160 or semiconductor material of the fin structures F10.

Cross-referencing FIGS. 1 and 12, method M10 continues at operation O22 with removing the top layer 115 of semiconductor material, including the laterally adjacent portion of semiconductor liner 130. For example, the top layer 115 and the laterally adjacent portion of the semiconductor liner 130 may be removed by an etch process selective to the material, such as SiGe, of the top layer 115 and liner 130.

As a result, the partially fabricated semiconductor device 200 of FIG. 12 has high-k isolation regions 180 separated in a lateral direction along the Y-direction by openings 185. Further, each high-k isolation region 180 is formed with an uppermost or top surface 181 located at a vertical height H2 over the uppermost surface 1171 of the top layer 117 of fins structures F10.

It is noted that in FIG. 12, the top surface of the top layer 117 and the bottom surface of the high-k isolation region 180 are substantially co-planar, i.e., the height H2 of the high-k isolation region 180 is equal to the height H3 of the opening 185 or of the removed top layer 115. However, it is contemplated that height H2 and height H3 be different. In certain embodiments, the height H3 of the opening 185 is less than the height H2 of the high-k isolation region 180.

Cross-referencing FIGS. 1 and 13, method M10 continues at operation O23 with further processing for fabricating the semiconductor device 200. For example, the further processing may include depositing polysilicon, patterning the polysilicon to define polysilicon gates, depositing an interlayer dielectric (ILD) 190 around the polysilicon gates, performing a CMP process to open the polysilicon gates, removing the polysilicon gates, removing the semiconductor layers 114 and defining the remaining semiconductor layers 116 as spaced apart nanosheets, depositing metal 210 between and over the remaining semiconductor layers 116 to form metal gates G10 over the fin structures F10, forming an interlayer dielectric 220 over the metal gates G10, and forming contacts 230 to metal gates G10. This further processing results in the structure of the partially fabricated semiconductor device 200 of FIG. 13.

As shown, when the metal gate material 210 is deposited over the fin structures F10, the high-k isolation regions 180 are already present and isolate adjacent metal gates G10 from one another. Thus, method M10 does not include etching trenches laterally adjacent to the metal gates G10 after the metal gate material 210 is deposited.

FIGS. 14-21 illustrate further embodiments of the high-k isolation regions 180 formed from high-k material 160 such as hafnium oxide (HfO2). FIG. 14 provides a perspective view of a partially fabricated device 200 at a stage similar to the fabrication stage of FIG. 12. FIG. 15, provides a cross-sectional view, such as along a Y-Z plane, of a high-k isolation region 180 of the device 200 of FIG. 14. It is noted that spacer layer 140 is not shown in FIGS. 14 and 15 may be considered to be part of the dielectric material 150 in FIGS. 14 and 15.

Cross-referencing FIGS. 14 and 15, each high-k isolation region 180 is formed with a vertical height H2 from a bottom surface 182 to a top surface 181. As shown, the top surface 181 of each high-k isolation region 180 is located at a vertical height H4 from the top surface 1171 of the fin structure F10. In the illustrated embodiment, vertical height H2 is greater than vertical height H4. Thus, the high-k isolation region 180 includes a lower portion 188 located below the surface 1171 of the fin structure F10 and an upper portion 189 located above the surface 1171 of the fin structure F10. The lower portion 188 has a vertical height H5 from the bottom surface 182 to the surface 1171. The upper portion 189 has a vertical height H4 from the top surface 181 to the surface 1171. The total height H2 is equal to the sum of height H4 and height H5.

In exemplary embodiments, vertical height H4 is from 5 nanometers (nm) to 100 nanometers (nm). For example, vertical height H4 may be at least 5 nm, at least 10 nm, at least 15 nm, at least 20 nm, at least 25 nm, at least 30 nm, at least 35 nm, at least 40 nm, at least 45 nm, at least 50 nm, at least 60 nm, at least 70 nm, at least 80 nm, or at least 90 nm. Further, vertical height H4 may be at most 10 nm, at most 15 nm, at most 20 nm, at most 25 nm, at most 30 nm, at most 35 nm, at most 40 nm, at most 45 nm, at most 50 nm, at most 60 nm, at most 70 nm, at most 80 nm, at most 90 nm, or at most 100 nm.

In exemplary embodiments, vertical height H5 is from 0 nanometers (nm) to 20 nanometers (nm). For example, vertical height H5 may be at least 1 nm, at least 5 nm, at least 10 nm, or at least 15 nm, and may be at most 20 nm, at most 15 nm, at most 10 nm, or at most 5 nm. It is further contemplated that the bottom surface 182 may be located at a vertical height above the surface 1171 of the fin structure F10. In such embodiments, the vertical height H5 may be considered to be negative, and may be between 0 nanometers (nm) and −20 nanometers (nm). In such embodiments, the vertical height H2 from the bottom surface 182 to the top surface 181 is less than the vertical height H4 from the surface 1171 to the top surface 181.

In certain embodiments, the ratio of height H4:height H5 is from 1:10 to 10:1. For example, the H4:H5 ratio may be at least 1:10, at least 2:10, at least 3:10, at least 4:10, at least 5:10; at least 6:10; at least 7:10; at least 8:10; at least 9:10; at least 10:10; at least 10:9; at least 10:8; at least 10:7; at least 10:6; at least 10:5; at least 10:4; at least 10:3; or at least 10:2. Further, the H4:H5 ratio may be at most 2:10, at most 3:10, at most 4:10, at most 5:10; at most 6:10; at most 7:10; at most 8:10; at most 9:10; at most 10:10; at most 10:9; at most 10:8; at most 10:7; at most 10:6; at most 10:5; at most 10:4; at most 10:3; or at most 10:2, or at most 10:1.

As shown, each high-k isolation region 180 is formed with a longitudinal length L1 in the X-direction and a lateral width W1 in the Y-direction. Further, the high-k isolation regions 180 are separated by a lateral distance D1 in the Y-direction.

In exemplary embodiments, the high-k isolation regions 180 independently have a length L1 in the X-direction of from 10 to 500 nanometers (nm). For example, length L1 may be at least 10 nm, at least 15 nm, at least 20 nm, at least 25 nm, at least 30 nm, at least 35 nm, at least 40 nm, at least 45 nm, at least 50 nm, at least 60 nm, at least 70 nm, at least 80 nm, at least 90 nm, at least 100 nm, at least 120 nm, at least 140 nm, at least 160 nm, at least 180 nm, at least 200 nm, at least 250 nm, at least 300 nm, at least 350 nm, at least 400 nm, or at least 450 nm. Further, length L1 may be at most 15 nm, at most 20 nm, at most 25 nm, at most 30 nm, at most 35 nm, at most 40 nm, at most 45 nm, at most 50 nm, at most 60 nm, at most 70 nm, at most 80 nm, at most 90 nm, at most 100 nm, at most 120 nm, at most 140 nm, at most 160 nm, at most 180 nm, at most 200 nm, at most 250 nm, at most 300 nm, at most 350 nm, at most 400 nm, at most 450 nm, or at most 500 nm.

In exemplary embodiments, the high-k isolation regions 180 independently have a width W1 in the Y-direction of from 10 to 500 nanometers (nm). For example, width W1 may be at least 10 nm, at least 15 nm, at least 20 nm, at least 25 nm, at least 30 nm, at least 35 nm, at least 40 nm, at least 45 nm, at least 50 nm, at least 60 nm, at least 70 nm, at least 80 nm, at least 90 nm, at least 100 nm, at least 120 nm, at least 140 nm, at least 160 nm, at least 180 nm, at least 200 nm, at least 250 nm, at least 300 nm, at least 350 nm, at least 400 nm, or at least 450 nm. Further, width W1 may be at most 15 nm, at most 20 nm, at most 25 nm, at most 30 nm, at most 35 nm, at most 40 nm, at most 45 nm, at most 50 nm, at most 60 nm, at most 70 nm, at most 80 nm, at most 90 nm, at most 100 nm, at most 120 nm, at most 140 nm, at most 160 nm, at most 180 nm, at most 200 nm, at most 250 nm, at most 300 nm, at most 350 nm, at most 400 nm, at most 450 nm, or at most 500 nm.

In exemplary embodiments, the high-k isolation regions 180 are distanced from one another by a distance D1 in the Y-direction of from 5 to 100 nanometers (nm). For example, distance D1 may be at least 5 nm, at least 10 nm, at least 15 nm, at least 20 nm, at least 25 nm, at least 30 nm, at least 35 nm, at least 40 nm, at least 45 nm, at least 50 nm, at least 60 nm, at least 70 nm, at least 80 nm, or at least 90 nm. Further, distance D1 may be at most 10 nm, at most 15 nm, at most 20 nm, at most 25 nm, at most 30 nm, at most 35 nm, at most 40 nm, at most 45 nm, at most 50 nm, at most 60 nm, at most 70 nm, at most 80 nm, at most 90 nm, or at most 100 nm.

The dielectric material 150 underlying the high-k isolation region 180 may be formed with a non-planar or angled surface 152 as shown. Such a surface 152 may result from the etching process used to recess the dielectric material 150 during operation O18. As shown, the high-k isolation region 180 may be formed with a reciprocal non-planar or angled bottom surface 182. Specifically, the bottom surface 182 may have a central planar portion 1821 and angled portions 1822 interconnecting the central planar portion 1821 to respective sidewalls 186 of the high-k isolation region 180.

As shown, the central planar portion 1821 of the bottom surface 182 has a lateral width W2 in the Y-direction. In exemplary embodiments, lateral width W2 is from 1 to 400 nanometers (nm). For example, width W2 may be at least 1 nm, at least 5 nm, at least 10 nm, at least 15 nm, at least 20 nm, at least 25 nm, at least 30 nm, at least 35 nm, at least 40 nm, at least 45 nm, at least 50 nm, at least 60 nm, at least 70 nm, at least 80 nm, at least 90 nm, at least 100 nm, at least 120 nm, at least 140 nm, at least 160 nm, at least 180 nm, at least 200 nm, at least 250 nm, at least 300 nm, or at least 350 nm. Further, width W2 may be at most 5 nm, at most 10 nm, at most 15 nm, at most 20 nm, at most 25 nm, at most 30 nm, at most 35 nm, at most 40 nm, at most 45 nm, at most 50 nm, at most 60 nm, at most 70 nm, at most 80 nm, at most 90 nm, at most 100 nm, at most 120 nm, at most 140 nm, at most 160 nm, at most 180 nm, at most 200 nm, at most 250 nm, at most 300 nm, at most 350 nm, or at most 400 nm.

As shown, the angled portion 1822 of the bottom surface 182 forms an internal angle A1 with the sidewall 186. In exemplary embodiments, the angle A1 is from 60 to 180 degrees. For example, angle A1 may be at least 60 degrees, at least 65 degrees, at least 70 degrees, at least 75 degrees, at least 80 degrees, at least 85 degrees, at least 90 degrees, at least 95 degrees, at least 100 degrees, at least 105 degrees, at least 110 degrees, at least 115 degrees, at least 120 degrees, at least 125 degrees, at least 130 degrees, at least 135 degrees, at least 140 degrees, at least 145 degrees, at least 150 degrees, at least 155 degrees, at least 160 degrees, at least 165 degrees, at least 170 degrees, or at least 175 degrees. Further, angle A1 may be at most 65 degrees, at most 70 degrees, at most 75 degrees, at most 80 degrees, at most 85 degrees, at most 90 degrees, at most 95 degrees, at most 100 degrees, at most 105 degrees, at most 110 degrees, at most 115 degrees, at most 120 degrees, at most 125 degrees, at most 130 degrees, at most 135 degrees, at most 140 degrees, at most 145 degrees, at most 150 degrees, at most 155 degrees, at most 160 degrees, at most 165 degrees, at most 170 degrees, at most 175 degrees, or at most 180 degrees.

In exemplary embodiments, the top surface 181 of the high-k isolation region 180 is planar and horizontal, i.e., is in an X-Y plane with a constant Z value. The top surface 181 forms an internal angle A2 with each respective sidewall 186. In exemplary embodiments, top surface 181 is horizontal, sidewall 186 is vertical, and angle A2 is 90 degrees. In other exemplary embodiments, angle A2 is from 60 to 120 degrees. For example, angle A1 may be at least 60 degrees, at least 65 degrees, at least 70 degrees, at least 75 degrees, at least 80 degrees, at least 85 degrees, at least 90 degrees, at least 95 degrees, at least 100 degrees, at least 105 degrees, at least 110 degrees, or at least 115 degrees. Further, angle A1 may be at most 65 degrees, at most 70 degrees, at most 75 degrees, at most 80 degrees, at most 85 degrees, at most 90 degrees, at most 95 degrees, at most 100 degrees, at most 105 degrees, at most 110 degrees, at most 115 degrees, or at most 120 degrees.

As shown in FIG. 15, the high-k isolation region 180 is a multi-layer structure formed from layers, such as layer 1601 and layer 1602. As shown, an interface 1603 is formed between layers 1601 and 1602. In FIG. 15, the high-k isolation region 180 includes three layers; however, it is contemplated that the high-k isolation region 180 include from one to twenty layers. Each layer may have a thickness T1 of from 3 to 20 nanometers (nm). For example, each layer may independently have a thickness T1 of at least 3 nm, at least 4 nm, at least 5 nm, at least 6 nm, at least 7 nm, at least 8 nm, at least 9 nm, at least 10 nm, at least 11 nm, at least 12 nm, at least 13 nm, at least 14 nm, at least 15 nm, at least 16 nm, at least 17 nm, at least 18 nm, or at least 19 nm. Further, each layer may independently have a thickness T1 of at most 4 nm, at most 5 nm, at most 6 nm, at most 7 nm, at most 8 nm, at most 9 nm, at most 10 nm, at most 11 nm, at most 12 nm, at most 13 nm, at most 14 nm, at most 15 nm, at most 16 nm, at most 17 nm, at most 18 nm, at most 19 nm, or at most 20 nm.

In exemplary embodiments, the layers 1601 and 1602 are formed from a same material, such as high-k material 160, for example hafnium oxide. In other exemplary embodiments, the layers 1601 and 1602 are formed from different materials. For example, one layer may be formed from a high-k material 160 and the other layer may be an insertion layer formed from another type of material, such as a material configured to improve the crystal uniformity of the material of the other layer.

FIGS. 16-18 provide three schematic views of exemplary high-k isolation regions 180 as multi-layer structures formed from layers and located over a dielectric material 150. In FIG. 16, two layers 1601 are formed from a high-k material such as hafnium oxide. Further, two layers 1602 are formed from a uniformity-improving material. An exemplary uniformity-improving material in layer 1602 reduces crystal non-uniformity in layer 1601. For example, layer 1602 may be formed from silicon dioxide (SiO2). In the exemplary embodiment of FIG. 16, layers 1601 may each have a thickness of 14 nanometers (nm) and layers 1602 may each have a thickness of 6 nanometers (nm). Thus, high-k isolation region 180 has a thickness of 40 nanometers (nm).

In FIG. 17, four layers 1601 are formed from a high-k material such as hafnium oxide. Further, two layers 1602 are formed from a uniformity-improving material. An exemplary uniformity-improving material in layer 1602 reduces crystal non-uniformity in layer 1601. For example, layer 1602 may be formed from silicon dioxide (SiO2). In the exemplary embodiment of FIG. 17, layers 1601 may each have a thickness of 9 nanometers (nm) and layers 1602 may each have a thickness of 4 nanometers (nm). Thus, high-k isolation region 180 has a thickness of 44 nanometers (nm).

In FIG. 18, three layers 1601 are formed from a high-k material such as hafnium oxide. Further, two layers 1602 are formed from a uniformity-improving material. An exemplary uniformity-improving material in layer 1602 reduces crystal non-uniformity in layer 1601. For example, layer 1602 may be formed from silicon dioxide (SiO2). In the exemplary embodiment of FIG. 17, layers 1601 may each have a thickness of 12 nanometers (nm) and layers 1602 may each have a thickness of 4 nanometers (nm). Thus, high-k isolation region 180 has a thickness of 44 nanometers (nm).

While FIGS. 16-18 provide suitable multi-layer structures for a high-k isolation region 180, other suitable structures are envisioned and may be selected to provide the desired isolation and processing properties. It is noted that the high-k material layer may be formed only as internal layers, as in FIGS. 17 and 18, or as an exterior layer as in FIG. 16.

Cross-referencing FIGS. 15-18, it may be seen that the top surface 181 of the high-k isolation region 180 may be formed from layer 1601 and 1602, such that the top surface 181 may be formed from layers of hafnium oxide and layers of silicon oxide.

In exemplary embodiments, the insertion layer 1602 improves the quality of the high-k material layer 1601, and of the multi-layer isolation region 180. Specifically, devices 200 formed with multi-layer isolation regions 180 may have reduced within-die “WiD” variation, i.e., increased WiD uniformity, as compared to devices 200 formed with single material isolation regions.

While FIGS. 11-13 illustrate a semi-square high-k isolation region 180 having a planar bottom surface 182, and FIGS. 14-15 illustrate a semi-octagon high-isolation region 180 having a bottom surface 182 formed with a central planar portion 1821 and angled portions 1822, other high-k isolation regions 180 are contemplated.

For example, FIG. 19 provides an illustration of a semi-circular high-k isolation region 180 having a semi-circular bottom surface 182. Further, FIG. 20 provides an illustration of a semi-hexagon high-k isolation region 180 having a bottom surface 182 formed by angled portions 1822 that intersect at an interface 1823. FIG. 21 provides an illustration of an inverted semi-hexagon high-k isolation region 180 having a bottom surface 182 formed by inverted angled portions 1824 that intersect at an interface 1825. While these shapes are illustrated and described, the high-k isolation region 180 may be formed with a bottom surface 182 having another shape.

Further, the high-k isolation regions 180 may be formed with a desired layout shape. FIGS. 22-25 provide simplified top-down layout views of partially fabricated devices 200, such as at the stage of fabrication of