1 according to the first embodiment.

The manufacturing process of the device layer 21 of the second substrate 2 and the device layer 31 of the first substrate 3 are the same as those of a general semiconductor device. Also, the process of forming the second connection wiring layer 22 on the side of the second substrate 2 and the process of forming the first connection wiring layer 32 on the side of the first substrate 3 are similarly described.

For example, when manufacturing the first substrate 3 shown in FIGS. 1 and 2, first, a silicon oxide layer (first interlayer insulating film) 45 is formed on the surface of the device layer 31 by, for example, CVD (Chemical Vapor Deposition), as shown in FIG. 6A. Then, on the surface of the silicon oxide layer 45, a wiring (lower wiring layer) 36 mainly composed of Cu, for example, is formed by the damascene method.

Thereafter, for example, by CVD, a SiCN film 46 and a silicon oxide layer 47 are sequentially stacked on the silicon oxide layer 45 in which the wiring 36 is embedded, thereby forming a second interlayer insulating film (FIG. 6A).

Subsequently, as shown in FIG. 6B, a first trench M1 having the same shape as the upper wiring layer 33 is formed at the position where the upper wiring layer 33 (see FIG. 3) is to be formed. In this step, first, a resist (not shown) is formed on the silicon oxide layer 47, and an opening having a diameter smaller than the width of the wiring 36 is formed in the resist at the position where the upper wiring layer 33 is to be formed.

Then, by using the resist with the openings as a mask and performing RIE (Reactive Ion Etching), the via hole Ma reaching from the surface of the silicon oxide layer 47 to the surface of the SiCN film 46 is formed.

After that, the diameter of the opening formed in the resist is expanded, for example, to the same extent as the width of the lower wiring layer 36, then a trench Mb for wiring or a pad electrode is formed by enlarging the diameter of the via hole Ma, from the surface of the silicon oxide film 47 to about the center of the thickness direction of the silicon oxide layer 47, by performing RIE again. The via hole Ma reaches the surface of the wiring 36 when forming the trench Mb. As a result, the first trench M1 having the shape shown in FIG. 6B is formed.

Thus, the second interlayer insulating film (SiCN film 46, silicon oxide film 47) with the first trench M1 formed therein is formed on the first interlayer insulating film 45.

Subsequently, as shown in FIG. 6C, for example, by a PVD (Physical Vapor Deposition) method or a sputtering method, the inner peripheral surface of the first trench M1 and the surface of the silicon oxide layer 47 are covered with a Ta thin film, in order to form the first barrier metal film 34a containing Ta. Furthermore, by coating the first barrier metal film 34a with a thin Ti film by PVD or sputtering, a second barrier metal film 34b containing Ti as a main component is formed.

More preferably, the first barrier metal film 34a and the second barrier metal film 34b are formed in the same apparatus under continuous high vacuum.

Also, for example, as described above, the first barrier metal film 34a is formed to have a film thickness of 10 nm or more, and the second barrier metal film 34b is formed to have a film thickness of 5 nm or less. In this case, the first barrier metal film 34a and the second barrier metal film 34b are amorphous.

Subsequently, a seed film 35X is formed by forming a Cu film on the surface of the second barrier metal film 34b by, e.g., PVD or sputtering (FIG. 6C).

More preferably, the seed film 35X is formed in the same apparatus and under a continuous high vacuum as in the case of forming the first barrier metal film 34a and the second barrier metal film 34b.

After that, as shown in FIG. 7A, Cu is deposited on the surface of the seed film 35X shown in FIG. 6C, for example, by electrolytic plating. Thus, a first conductive film 35 containing Cu is formed (FIG. 7A).

After that, as shown in FIG. 7B, after Cu is deposited, an annealing treatment is performed to diffuse Ti atoms of the second barrier metal film 34b into the first conductive film 34 containing Cu.

Thus, the upper wiring layer 33 is formed so as to include a first barrier metal film 34a provided in the first trench M1 and containing Ta as a main component, a second barrier metal film 34b formed in the first trench M1 via the first barrier metal film 34a and containing Ti as a main component, and a first conductive film 35 provided in the first trench M1 via a first barrier metal film 34a and a second barrier metal film 34b and containing a first metal (Cu) as a main component. In particular, Ti of the second barrier metal film 34b diffuses into the first conductive film 35 due to the annealing treatment.

Subsequently, by polishing the surface of the first substrate 3 whose surface is coated with Cu, for example, by a CMP (Chemical Mechanical Polishing) method, as shown FIG. 7C, the upper portion of the first conductive film 35 containing unnecessary Cu and Ti on the silicon oxide film 47 is removed.

Thus, the upper wiring layer 33 electrically connected to the lower wiring layer 36 via the first and second barrier metal films 34a and 34b is formed in the first trench M1 of the second interlayer insulating film 47.

That is, the configuration of the semiconductor device 1 as shown in FIG. 3 is completed by the above steps. Therefore, in the semiconductor device 1 according to this embodiment, the upper wiring layer 3 includes: a first barrier metal film 34a provided in the first trench M1 and containing Ta as a main component, a second barrier metal film 34b formed in the first trench M1 via the first barrier metal film 34a and containing Ti as a main component, and a first conductive film 35 provided in the first trench M1 via a first barrier metal film 34a and a second barrier metal film 34b and containing a first metal as a main component.

In particular, Ti contained in the second barrier metal film 34b is diffused into the first conductive film 35. Thereby, occurrence of migration of Cu constituting the first conductive film 35 can be suppressed.