295 to emit light while performing the user authentication on the secure data associated with the secure data exchange operation. When the processor 240 determines that the user's input fingerprint does not match the user's original fingerprint, the processor 240 may indicate that the input fingerprint does not match the user's original fingerprint through the LEDs 295.

FIG. 3 illustrates an example of the rectifier 210 in the smart card chip in FIG. 2 according to example embodiments. Here, the rectifier 210 may include a first diode 211 and a second diode 212.

The first diode 211 may have an anode connected to the first power terminal L1 and a cathode connected to an output node 213. The second diode 212 may have an anode connected to the second power terminal L2 and a cathode connected to the output node 213. The first and second diode 211 and 212 may rectify a contact voltage VDDC provided through the contact terminal 63 in FIG. 2 to provide the rectified voltage VREC to the internal voltage generator 300 in the contact mode. The first and second diode 211 and 212 may collectively rectify a contactless voltage VDDU provided through the resonance unit 70 n FIG. 2 to provide the rectified voltage VREC to the internal voltage generator 300 in the contactless mode.

FIG. 4 illustrates an example of the mode detector 260 in the smart card chip in FIG. 2 according to example embodiments. The mode detector 260 may include a comparator 261 and a switch control signal generator (SCSG) 263.

The comparator 261 “compares the contact voltage VDDC and the contactless voltage VDDU” by comparing a voltage applied to its positive input terminal (connected to the terminal L1) with a reference voltage VREFC applied to its negative input terminal. The comparator 261 outputs the mode signal MDS indicating one of the contact mode and the contactless mode based on a result of the comparison. When the smart card 100 is connected in the contactless manner, a voltage level of the contactless voltage VDDU is greater than the reference voltage VREFC and the comparator 261 may output the mode signal MDS with a first logic level (e.g. logic high level). When the smart card 100 is connected in the contact manner, a voltage level of the contact voltage VDDC is smaller than the reference voltage VREFC and the comparator 261 may output the mode signal MDS with a second logic level (e.g. logic low level).

The switch control signal generator 263 may determine logic levels of the power switch control signals PCS including a first power switch control signal PCS1 and a second power switch control signal PCS2 based on the mode signal MDS and may provide the first power switch control signal PCS1 and the second power switch control signal PCS2 to the internal voltage generator 300. The switch control signal generator 263 may generate the first power switch control signal PCS1 and the second power switch control signal PCS2 based on the mode signal MDS such that the first power switch control signal PCS1 and the second power switch control signal PCS2 have complementary logic levels with respect to each other.

FIG. 5 is a block diagram illustrating an example of the internal voltage generator in the smart card chip in FIG. 2 according to example embodiments.

Referring to FIG. 5, the internal voltage generator 300 may include a switched capacitor circuit 305, a low-drop out (LDO) regulator 330 and a voltage regulator 380. The switched capacitor circuit 305 may include a first switched capacitor (SC) converter 310 and a second switched capacitor (SC) converter 320.

The switched capacitor circuit 305 may receive the rectified voltage VREC and may generate a first driving voltage VDD1 and a second driving voltage VDD2 by converting the rectified voltage VREC. The first switched capacitor converter 310 may convert the rectified voltage VREC to the first driving voltage VDD1 based on the switch control signals SCS and the second switched capacitor converter 320 may convert the first driving voltage VDD1 to the second driving voltage VDD2 based on the switch control signals SCS. The switched capacitor circuit 305 may provide the first driving voltage VDD1 and the second driving voltage VDD2 to the LDO regulator 330 and may provide the first driving voltage VDD1 to the voltage regulator 380.

The rectified voltage VRET may have a first voltage level, the first driving voltage VDD1 may have a second voltage level smaller than the first voltage level, and the second driving voltage VDD2 may have a third voltage level smaller than the second voltage level. In embodiments, the second voltage level may correspond to a half of the first voltage level and the third voltage level may correspond to a half of the second voltage level.

The LDO regulator 330 may include an error amplifier. The LDO regulator 330, based on the mode signal MDS and the power switch control signals PCS, may drive the error amplifier with the second driving voltage VDD2 to generate an error voltage, and may regulate the second driving voltage VDD2 based on the error voltage to generate a first output voltage VOUT1 in the contact mode. The LDO regulator 330, based on the mode signal MDS and the power switch control signals PCS, may drive the error amplifier with the first driving voltage VDD1 to generate the error voltage, and may regulate the second driving voltage VDD2 based on the error voltage to generate the first output voltage VOUT1 in the contactless mode.

The voltage regulator 380 may regulate the second driving voltage VDD2 to generate a second output voltage VDD1 independently of the mode signal MDS.

In embodiments, the internal voltage generator 300 may further include the mode detector 260. The mode detector 260 may generate the mode signal MDS and the power switch control signals PCS based on the input voltage VIN as described with reference to FIG. 4.

FIG. 6 is a circuit diagram illustrating an example of the first switched capacitor in the internal voltage generator of FIG. 5 according to example embodiments.

Referring to FIG. 6, a first switched capacitor converter 310a may include first, second, third and fourth switches 311, 312, 313 and 314 and a capacitor 315.

The first switch 311 is connected between a first node N11 receiving the rectified voltage VREC and a second node N12, and is switched in response to a first switch control signal SCS1. The capacitor 315 is coupled between the second node N12 and a third node N13. The second switch 312 is connected between the second node N12 and a fourth node N14 providing the first driving voltage VDD, and is switched in response to a second switch control signal SCS2.

The third switch 313 is connected between the third node N13 and a ground voltage VSS, and is switched in response to the second switch control signal SCS2. The fourth switch 314 is connected between the third node N13 and the fourth node N14, and is switched in response to the first switch control signal SCS1.

The first switch control signal SCS1 and the second switch control signal SCS2 may have a same logic level. The first switch 311 and the fourth switch 314 may be turned-on in response to the first switch control signal SCS1 having a low level and may be turned-off in response to the first switch control signal SCS1 having a high level. The second switch 312 and the third switch 313 may be turned-off in response to the second switch control signal SCS2 having a low level and may be turned-on in response to the second switch control signal SCS2 having a high level.

FIG. 7 is a circuit diagram illustrating another example of the first switched capacitor in the internal voltage generator of FIG. 5 according to example embodiments.

Referring to FIG. 7, a first switched capacitor converter 310b may include p-channel metal-oxide semiconductor (PMOS) transistors 316 and 319, n-channel metal-oxide semiconductor (NMOS) transistors 317 and 318 and a capacitor 315.

The PMOS transistor 316 is connected between the first node N11 receiving the rectified voltage VREC and the second node N12, and is turned-on/off in response to the first switch control signal SCS1. The NMOS transistor 317 is connected between the second node N12 and the fourth node N14 providing the first driving voltage VDD, and is turned-on/off in response to the second switch control signal SCS2. The capacitor 315 is coupled between the second node N12 and the third node N13.

The NMOS transistor 318 is connected between the third node N13 and the ground voltage VSS, and is turned-on/off in response to the second switch control signal SCS2. The PMOS transistor 319 is connected between the third node N13 and the fourth node N14, and is turned-on/off in response to the first switch control signal SCS1.

FIGS. 6 and 7 illustrate examples of the first switched capacitor converter 310 in FIG. 5, respectively, and a configuration of the second switched capacitor converter 320 may be the same as a configuration of the first switched capacitor converter 310.

FIG. 8 illustrates an example operation of the first switched capacitor converter in FIG. 6.

An operation of the first switched capacitor converter 310b in FIG. 7 may be the same as operation of the first switched capacitor converter 310a in FIG. 6.

Referring to FIG. 8, when the first switch 311 and the fourth switch 314 are turned-on and the second switch 312 and the third switch 313 are turned-off during a first phase, a voltage VCAP is stored in the capacitor 315 based on the rectified voltage VREC, and the first driving voltage VDD1 is provided at the fourth node N14 based on the voltage VCAP stored in the capacitor 315.

FIG. 9 illustrates an example operation of the first switched capacitor converter in FIG. 6.

An operation of the first switched capacitor converter 310b in FIG. 7 may be the same as operation of the first switched capacitor converter 310a in FIG. 6.

Referring to FIG. 9, when the first switch 311 and the fourth switch 314 are turned-off and the second switch 312 and the third switch 313 are turned-on during a second phase, a voltage VCAP stored in the capacitor 315 during the first phase linearly decreases and the first driving voltage VDD1 is provided at the fourth node N14 based on the voltage VCAP stored in the capacitor 315.

FIG. 10 is a circuit diagram illustrating an example of the LDO regulator in the internal voltage generator of FIG. 5 according to example embodiments.

Referring to FIG. 10, the LDO regulator 330 may include a voltage selector 331, a polarity selector 340, an error amplifier 350, a first power switch 361, a first power transistor (PT1) 365, a second power switch 363, a second power transistor (PT2) 367 and a feedback circuit 370.

The voltage selector 360 may provide a power terminal 360 of the error amplifier 350 with one of the first driving voltage VDD1 and the second driving voltage VDD2 in response to the mode signal MDS as an error amplifier power supply voltage VEA.

The polarity selector c340 may provide a reference voltage VREF and a feedback voltage VFB1 to either a negative input terminal and a positive input terminal of the error amplifier 350 or the positive input terminal and the negative input terminal of the error amplifier 350, respectively, based on the mode signal MDS.

The error amplifier 350, connected between the power terminal 360 and the ground voltage VSS, may amplify a difference between a feedback voltage VFB1 and the reference voltage VREF to output a first error voltage EV1 to a first node N21. The first node N21 may correspond to an output terminal of the error amplifier 350. The power terminal 360 may receive one of the first driving voltage VDD1 and the second driving voltage VDD2. The first error voltage EV1 may be also referred to as an error voltage. The feedback voltage VFB1 may be also referred to as a first feedback voltage.

The first power switch 361 may be connected between the first node N21 and the first power transistor 365, and may be switched in response to the first power switch control signal PCS1. The first power transistor 365 may be connected between the second driving voltage VDD2 and an output node NO providing the first output voltage VOUT1.

The second power switch 363 may be connected between the first node N21 and the second power transistor 367, and may be switched in response to the second power switch control signal PCS2. The second power transistor 367 may be connected between the second driving voltage VDD2 and the output node NO in parallel with the first power transistor 365. The second power transistor 367 may have a type different from a type of the first power transistor 365.

The feedback circuit 370 is connected between the output node NO and the ground voltage VSS, and may divide the first output voltage VOUT1 to provide the feedback voltage VFB1. The feedback circuit 370 includes a first feedback resistor RF1 and a second feedback resistor RF2 connected in series between the output node NO and the ground voltage VSS. The first feedback resistor RF1 and the second feedback resistor RF2 are connected to each other at a feedback node FN1, and the feedback circuit 370 provides a voltage of the feedback node FN1 as the feedback voltage VFB1.

FIG. 11 is a circuit diagram illustrating the LDO regulator 330 of FIG. 10 in detail according to example embodiments. Here, the voltage selector 331 may include a multiplexer 332. The multiplexer 332 may select the first driving voltage VDD1 among the first driving voltage VDD1 and the second driving voltage VDD2 to provide the error amplifier power supply voltage VEA based on the mode signal MDS in the contactless mode. The multiplexer 332 may select the second driving voltage VDD2 among the first driving voltage VDD1 and the second driving voltage VDD2 to provide the error amplifier power supply voltage VEA based on the mode signal MDS in the contact mode.

The polarity selector 340 may be implemented with a crossbar switch, may provide the reference voltage VREF and the feedback voltage VFB1 to the negative input terminal and the positive input terminal of the error amplifier 350, respectively, based on the mode signal MDS in the contact mode and may provide the reference voltage VREF and the feedback voltage VFB1 to the positive input terminal and the negative input terminal of the error amplifier 350, respectively, based on the mode signal MDS in the contactless mode.

The first power transistor 365 may be a PMOS transistor 366 having a source coupled to the second driving voltage VDD2, a gate coupled to the first power switch 361 and a drain coupled to the output node NO. The second power transistor 367 may be an NMOS transistor 368 having a source coupled to the second driving voltage VDD2, a gate coupled to the second power switch 363 and a source coupled to the output node NO.

In the contact mode, the first power switch 361 is turned-on in response to the first power switch control signal PCS1 to apply the first error voltage EV1 to the gate of the first power transistor 365 and the second power switch 363 is turned-off in response to the second power switch control signal PCS2 to disconnect the output terminal of the error amplifier 350 from the gate of the second power transistor 367.

In the contactless mode, the first power switch 361 is turned-off in response to the first power switch control signal PCS1 to disconnect the output terminal of the error amplifier 350 from the gate of the first power transistor 365 and the second power switch 363 is turned-on in response to the second power switch control signal PCS2 to apply the first error voltage EV1 to the gate of the second power transistor 367.

FIG. 12 illustrates an example operation of the LDO regulator of FIG. 11 in the contact mode according to example embodiments.

Referring to FIG. 12, the mode signal MDS has a second logic level (a low level) in the contact mode. The multiplexer 332 selects the second driving voltage VDD2 of the first driving voltage VDD1 and the second driving voltage VDD2 to provide the second driving voltage VDD2 to the power terminal 360 of the error amplifier 350 based on the mode signal MDS. The polarity selector 340 provides the reference voltage VREF and the feedback voltage VFB1 to the negative input terminal and the positive input terminal of the error amplifier 350, respectively, based on the mode signal MDS. The first power switch 361 is turned-on and the second power switch 363 is turned-off.

The error amplifier 350 is driven with the second driving voltage VDD2, amplifies a difference between the reference voltage VREF and the first feedback voltage VFB1 to applies the first error voltage EV1 to the gate of the first power transistor 365. The first power transistor 365 regulates the second driving voltage VDD2 based on the first error voltage EV1 to provide the first output voltage VOUT1 to the processor 240 and the logic circuit block 295 in FIG. 2.

When a voltage level of the first output voltage VOUT1 decreases in the contact mode, a voltage level of the first feedback voltage VFB1 decreases. A voltage level of the first error voltage EV1 decreases in response to the decrease of voltage level of the first feedback voltage VFB1. A current flowing from the first power transistor 365 to the output node NO increases in response to the decrease of the voltage level of the first error voltage EV1 and thus, the voltage level of the first output voltage VOUT1 increases.

When the voltage level of the first output voltage VOUT1 increases in the contact mode, the voltage level of the first feedback voltage VFB1 increases. The voltage level of the first error voltage EV1 increases in response to the increase of voltage level of the first feedback voltage VFB1. A current flowing from the first power transistor 365 to the output node NO decreases in response to the increase of the voltage level of the first error voltage EV1 and thus, the voltage level of the first output voltage VOUT1 decreases.

Therefore, in the contact mode, the first output voltage VOUT1 follows the reference voltage VREF by regulation operation of the first power transistor 365 which is implemented with the PMOS transistor 366.

FIG. 13 illustrates an example operation of the LDO regulator of FIG. 11 in the contactless mode according to example embodiments.

Referring to FIG. 13, the mode signal MDS has a first logic level (a high level) in the contact mode. The multiplexer 332 selects the first driving voltage VDD1 of the first driving voltage VDD1 and the second driving voltage VDD2 to provide the first driving voltage VDD1 to the power terminal 360 of the error amplifier 350 based on the mode signal MDS. The polarity selector 340 provides the reference voltage VREF and the feedback voltage VFB1 to the positive input terminal and the negative input terminal of the error amplifier 350, respectively, based on the mode signal MDS. The first power switch 361 is turned-off and the second power switch 363 is turned-on.

The error amplifier 350 is driven with the first driving voltage VDD1, amplifies a difference between the reference voltage VREF and the first feedback voltage VFB1 to applies the first error voltage EV1 to the gate of the second power transistor 367. The second power transistor 367 regulates the second driving voltage VDD2 based on the first error voltage EV1 to provide the first output voltage VOUT1 to the processor 240 and the logic circuit block 295 in FIG. 2.

When the voltage level of the first output voltage VOUT1 decreases in the contactless mode, the voltage level of the first feedback voltage VFB1 decreases. The voltage level of the first error voltage EV1 increases in response to the decrease of voltage level of the first feedback voltage VFB1. A current flowing from the first power transistor 365 to the output node NO increases in response to the decrease of the voltage level of the first error voltage EV1 and thus, the voltage level of the first output voltage VOUT1 increases.

When the voltage level of the first output voltage VOUT1 increases in the contactless mode, the voltage level of the first feedback voltage VFB1 increases. The voltage level of the first error voltage EV1 decreases in response to the increase of voltage level of the first feedback voltage VFB1. A current flowing from the first power transistor 365 to the output node NO decreases in response to the decrease of the voltage level of the first error voltage EV1 and thus, the voltage level of the first output voltage VOUT1 decreases.

Therefore, in the contactless mode, the first output voltage VOUT1 follows the reference voltage VREF by regulation operation of the second power transistor 367 which is implemented with the NMOS transistor 368.

That is, the error amplifier 350 is driven with the second driving voltage VDD2 to apply the first error voltage EV1 to the gate of the PMOS transistor 366 in the contact mode and the error amplifier 350 is driven with the first driving voltage VDD1 to apply the first error voltage EV1 to the gate of the NMOS transistor 368 in the contactless mode. Therefore, a gate-drain voltage of the PMOS transistor 366 is different from a gate-source voltage of the NMOS transistor 368.

In a conventional internal voltage generator, an error amplifier is driven with a second driving voltage VDD2 and a PMOS type power transistor regulates the second driving voltage VDD2 to provide the first output voltage VOUT2 to the logic circuit block 295. Therefore, since a difference between the second driving voltage VDD2 and the first output voltage VOUT1 is small and a drain-source voltage of the PMOS transistor is too small, the first output voltage VOUT1 may not have a stable level.

The LDO regulator 330 according to example embodiments, drives the error amplifier 350 with the first driving voltage VDD1 which is larger than the second driving voltage VDD2, and the second power transistor 367 implemented with the NMOS transistor 368 regulates the second driving voltage VDD2 based on the first error voltage EV1 to provide the first output voltage VOUT1. Therefore, a gate-source voltage of the NMOS transistor 368 is enough, and thus the first output voltage VOUT1 may have a stable level.

FIG. 14 is a circuit diagram illustrating an example of the voltage regulator in the internal voltage generator of FIG. 5 according to example embodiments.

Referring to FIG. 14, the voltage regulator 380 may include an error amplifier 381, a power transistor 382 and a feedback circuit 383.

The error amplifier 381 may have a negative (−) input terminal to receive the reference voltage VREF and a positive (+) input terminal to receive a second feedback voltage VFB2. The error amplifier 381 may amplify a difference between the second feedback voltage VFB2 and the reference voltage VREF to output a second error voltage EV2 to a gate of the power transistor 382.

The power transistor 382 may be a PMOS transistor having a source coupled to the first driving voltage VDD1, a gate to receive the second error voltage EV2 and a drain coupled to an output node NO2, and may regulate the first driving voltage VDD1 based on the second error voltage EV2 to provide the second output voltage VOUT2 at the output node NO2.

The feedback circuit 383 is connected between the output node NO2 and the ground voltage VSS, and may divide the second output voltage VOUT2 to provide the second feedback voltage VFB2. The feedback circuit 383 includes a feedback resistor RF3 and a feedback resistor RF4 connected in series between the output node NO2 and the ground voltage VSS. The feedback resistor RF3 and the feedback resistor RF4 are connected to each other at a feedback node FN2, and the feedback circuit 383 provides a voltage of the feedback node FN2 as the second feedback voltage VFB2.

In the voltage regulator 380, the power transistor 382 implemented with the PMOS transistor regulates the first driving voltage VDD1 to provide the second output voltage VOUT2, and thus a voltage level of the second output voltage VOUT2 is equal to or greater than the first output voltage VOUT1. The voltage regulator 380 may provide the second output voltage VOUT2 to the fingerprint recognition sensor 270 and the LEDs 290 in FIG. 2. Since the fingerprint recognition sensor 270 and the LEDs 290 are used for performing fingerprint authentication on the payment data in the contactless mode, and thus a power consumption in the smart card 50 increases. The fingerprint recognition sensor 270 and the LEDs 290 operate based on the second output voltage VOUT2 having a relatively high voltage level, and thus the fingerprint recognition sensor 270 and the LEDs 290 operate stably.

FIG. 15 is a circuit diagram illustrating an example of the error amplifier in the LDO regulator of FIG. 10 in detail according to example embodiments. In this example, the error amplifier 350 may include a folded cascode amplifier 350a and a source follower 350b.

The folded cascode amplifier 350a may include PMOS transistors MP1˜MP7, NMOS transistors MN1˜MN4, a resistor R11 and a capacitor C11.

The PMOS transistor MP1 is connected between the power voltage EVA and a node N23 and has a gate receiving a first bias voltage VB1. Therefore, the PMOS transistor MP1 may operate as a current source. The PMOS transistor MP2 is connected between a node N23 and a node N28 and has a gate coupled to a negative input terminal 351. The PMOS transistor MP3 is connected between the node N23 and a node N29 and has a gate coupled to a positive input terminal 352.

The PMOS transistor MP4 is connected between the power voltage EVA and a node N25 and has a gate receiving the first bias voltage VB1. The PMOS transistor MP5 is connected between the power voltage EVA and a node N26 and has a gate receiving the first bias voltage VB1. The resistor R11 and the capacitor C11 are connected in series between the node N25 and the node N26. The PMOS transistor MP6 is connected between the node N25 and a node N24 and has a gate receiving a second bias voltage VB2. The PMOS transistor MP6 is connected between the node N26 and a node N27 and has a gate receiving the second bias voltage VB2.

The NMOS transistor MN1 is connected between the node N24 and a node N28 and has a gate receiving a third bias voltage VB3. The NMOS transistor MN2 is connected between the node N27 and a node N29 and has a gate receiving the third bias voltage VB3. The NMOS transistor MN3 is connected between the node N28 and the ground voltage VSS and has a gate receiving a fourth bias voltage VB4. The NMOS transistor MN4 is connected between the node N2 and the ground voltage VSS and has a gate receiving a fourth bias voltage VB4.

The source follower 350b may include PMOS transistors 353 and 354, NMOS transistors 355 and 356 and a resistor R22.

The PMOS transistor 353 is connected between the power voltage EVA and a node N21 and has a gate receiving the first bias voltage VB1. The PMOS transistor 354 is connected between the node N21 and a node N22 and has a gate coupled to the node N27. The resistor R22 is connected between the node N21 and the NMOS transistor 356. The NMOS transistor 355 is connected between the node N22 and the ground voltage VSS and has a gate receiving the fourth bias voltage VB4. The NMOS transistor 356 is connected between the resistor R22 and the ground voltage VSS and has a gate coupled to the node N22.

In FIG. 15, it is assumed that a current driving capability of the PMOS transistors MP1, MP4, MP5 and 353 may be same with respect to each other, a current driving capability of the PMOS transistors MP2 and MP3 may be same with respect to each other, a current driving capability of the PMOS transistors MP6, MP7 and 354 may be same with respect to each other, a current driving capability of the NMOS transistors MN1, MN2 and 356 may be the same with respect to each other, and current driving capability of the NMOS transistors MN1, MN2 and 356 may be the same with respect to each other.

The first bias voltage VB1 is applied to each gate of the PMOS transistors MP1 and 353 and thus, a current having a same magnitude flows into the nodes N23 and N21. A difference between the reference voltage applied to the negative input terminal 351 and the first feedback voltage VFB1 applied to the positive input terminal 352 makes a voltage difference at the nodes N27 and N24, and the first error voltage EV1 corresponding to the voltage difference at the nodes N27 and N24 is provided at the node N21.

In general, the smart cards or the IC cards are of a shape such that a thin semiconductor device is attached to a plastic card of the same size as a credit card. The smart cards can be roughly classified as a contact IC card, a contactless IC Card (CICC), and a Remote Coupling Communication Card (RCCC). In connection with the CICC, ISO (the International Organization for Standardization) and IEC (the International Electrotechnical Commission) have formed a specialized system for worldwide standardization.

In particular, international standard ISO/IEC 14443 specifies the physical characteristics of proximity cards, radio frequency power and signal interface, initialization and anti-collision, and transmission protocol. Under ISO/IEC 14443, the contactless IC cards incorporate an integrated circuit (IC) that performs data processing and/or memory functionality. The possibility of contactless card technology is a result of the achievement of signal exchange via inductive coupling with a proximity coupling device (that is, a card reader) and to ability to supply power to the card without the use of galvanic elements (i.e., the absence of an ohmic path from the external interfacing equipment to the integrated circuit(s) contained within the card). A card reader produces an energizing radio frequency (RF) field which is coupled to the card to transfer power and which is modulated for communication. The carrier frequency fc of the RF operating field is 13.56 MHz+7 kHZ.

FIGS. 16 and 17 are diagrams illustrating examples of communication signals for a type A interface of ISO/IEC 14442 standards, and FIG. 18 is a diagram illustrating an example of frames and pauses of the type A interface of ISO/IEC 14442 standards.

FIG. 16 illustrates a signal transferred from a card reader to a contactless IC card and FIG. 17 illustrates a signal transferred from the contactless IC card to the card reader.

The ISO/IEC 14443 protocol describes two communication signal interfaces, Type A and Type B. Under the communication signal interface Type A, communication from a card reader to a contactless smart card utilizes the modulation principle of ASK 100% of the RF operating field and a Modified Miller code principle. The bit rate for the transmission from the card reader to the contactless smart card is fc/128, that is, 106 kbps (kb/s). Transmission from the contactless smart card to the card reader is coded by the Manchester code principle and then modulated by the On-Off Key (OOK) principle. Presently, cards that are managed by the communication signal interface of Type A in subways and buses, generate timing of a constant interval of time using an ASK-modulated signal received from a card reader, and receive and transmit data one bit at a time.

When data is transferred from a smart card to a card reader, power is stably provided to the smart card from the card reader.

FIG. 18 illustrates Type A data frames of ISO/IEC 14443 standards. FIG. 18 shows a short frame including a start bit S, data bits b1˜B7 and an end bit E.

FIG. 19 illustrates an example of the fingerprint recognition sensor in the smart card chip in FIG. 2 according to example embodiments.

Referring to FIG. 19, the fingerprint recognition sensor 270 may include a lens 271 and a an image sensor 272, and the image sensor 272 may include a pixel array 273.

The lens 271 may concentrate reflected light from a user's finger 80 on the pixel array 272 of the image sensor 272. The image sensor 272 may generate a fingerprint image signal based on the reflected light and may provide the fingerprint image signal to the processor 240 in FIG. 2.

The processor 240 may compare the fingerprint image signal with the user's original fingerprint and may determine whether the user's input fingerprint is faked based on a result of the comparison. When the processor 240 determines that the user's input fingerprint matches the user's original fingerprint, the processor 240 may indicate that the user authentication is passed by controlling the LEDs 295 to emit light while performing the user authentication on the payment data associated with the payment operation.

FIG. 20 is a flow chart illustrating a method of operating a smart card according to example embodiments.

Referring to FIG. 1 through 20, the switched capacitor circuit 305 in the internal voltage generator 300 of the smart card 50 generates the first driving voltage VDD1 and the second driving voltage VDD2, where VDD2 is smaller than VDD1, based on the input voltage VDD1 (operation S510). The switched capacitor circuit 305 may receive a rectified voltage VREC obtained by rectifying the input voltage and may generate the first driving voltage VDD1 and the second driving voltage VDD2 by converting the rectified voltage VREC.

The mode detector 260 in the smart card 50 determines whether the smart card 50 receives the input voltage VIN in the contact mode (operation S520), and generates the mode signal MDS indicating one of the contact mode and the contactless mode.

When the smart card 50 receives the input voltage VIN in the contact mode (YES in S520), the LDO regulator 330 drives the error amplifier 350 with the second driving voltage VDD2 to generate the first error voltage EV1 (operation S530). The first power transistor 365 implemented with the PMOS transistor 366 regulates the second driving voltage VDD2 based on the first error voltage EV1 to provide the first output voltage VOUT1 (operation S540).

When the smart card 50 receives the input voltage VIN in the contactless mode (NO in S520), the LDO regulator 330 drives the error amplifier 350 with the first driving voltage VDD1 to generate the first error voltage EV1 (operation S550). The second power transistor 367 implemented with the NMOS transistor 368 regulates the second driving voltage VDD2 based on the first error voltage EV1 to provide the first output voltage VOUT1 (operation S560).

Therefore, in a method of operating the smart card according to example embodiments, the LDO regulator 330 drives the error amplifier 350 with the second driving voltage VDD2 and the first driving voltage VDD1 having different voltage levels, respectively in the contact mode and the contactless mode, the first power transistor 365 implemented with the PMOS transistor 366 regulates the second driving voltage VDD2 based on the first error voltage EV1 to provide the first output voltage VOUT1 in the contact mode and the second power transistor 367 implemented with the NMOS transistor 368 regulates the second driving voltage VDD2 based on the first error voltage EV1 to provide the first output voltage VOUT1 in the contactless mode. Accordingly, the LDO regulator 330 may provide the first output voltage VOUT1 to the logic circuit block 290 stably in both the contact mode and the contactless mode.

FIG. 21 illustrates an example of the smart card according to example embodiments. In this example, the smart card 50 may include an integrated circuit 85, an antenna 61, the fingerprint recognition sensor 270 and the LEDs 290 formed in a substrate 101.

The antenna 61 may be coupled to the integrated circuit 85. The integrated circuit 85 may include components among from components of the smart card chip 100 in FIG. 2 except the fingerprint recognition sensor 270 and the LEDs 290, and the contact terminal 63 in FIG. 1 may be included in the integrated circuit 85.

FIG. 22 is a cross-sectional view illustrating an example of a structure of the smart card according to example embodiments. The smart card 50 may include substrate 101, a plurality of trench capacitors TC arranged in the substrate 101, a circuit layer 120 disposed at a front side FS of the substrate 101 and a protection layer 130 disposed on an upper portion of the circuit layer 120. In example embodiments, the protection layer 130 may be provided as an active shield. The protection layer 130 may include a plurality of wires arranged on the circuit layer 120 and an insulating layer on the plurality of wires.

FIG. 23 is a block diagram illustrating an example of the circuit layer in the smart card in FIG. 22 according to example embodiments. The circuit layer 120 may include a sensor 121, a frequency detector (FD) 122, a processor 123, a cryptography module (ENC_M) 124, a random number generator (RNG) 125, a communication module (COMM) 126, a memory (MEM) 127, a fingerprint recognition sensor (FSR) 128 and an internal voltage generator (IVGC) 129.

The processor 123, the memory 127, the fingerprint recognition sensor 128 and the internal voltage generator 129 may respectively correspond the processor 240, the memory 250, the fingerprint recognition sensor 270 and the internal voltage generator 300 in FIG. 2 and the cryptography module 124, the random number generator 125, and the communication module 126 may correspond to the logic circuit block 295 in FIG. 2.

Referring to FIGS. 22 and 23, the sensor 121 may include a plurality of trench capacitors TC. When a lower area of a trench capacitors TC is removed, in the course of back side polishing, the capacitance of the affected trench capacitor TC may change. (Back side polishing is a malicious attack in which the back side of a chip is polished to access a target transistor(s).)

The frequency detector 122 may be connected to an output terminal of the sensor 121 and detect a frequency of an output signal of the sensor 121. When the detected frequency of the output signal is outside a predetermined range, the frequency detector 122 may activate an alarm signal, by generating a logic “high” control signal, for example, and provide the generated control signal to the processor 123.

For example, if a logic “high” control signal is received from the frequency detector 122, the processor 123 may nullify data stored in the memory 127 in the smart card 50, or initialize functions of the cryptography module 124 or the random number generator 125 in the smart card 50. In this manner, the smart card 50 may be reset, and security information may be protected from a back side attack.

FIG. 24 is a circuit diagram illustrating an example of a protection device, 135, according to example embodiments. The protection device