210 asserts the weak (W) control signal (e.g., setting it to a logic low voltage). As discussed, the weak (W) control signal propagates through the set of power switch cells SW₁to SW₃₂sequentially and progressively coupling the global power rail Vdd to the local power rail Vdd2. At time t₂, the weak (W) control signal arrives at the R_Winput of the control circuit 210; thereby, ending the weak (W) power rail coupling phase. As illustrated, during the weak (W) coupling phase, the current I₂drawn by the core coupled to the local power rail Vdd2 gradually increases to minimize or reduce the impact on the supply voltage Vdd1 at the other local power rail. As a result, the supply voltage Vdd1 decreases slightly, but not below the safe threshold voltage Vth.

At time t₂, in response to receiving the weak (W) control signal at the R_Winput, the control circuit 210 asserts the strong (S) control signal (e.g., setting it to a logic low voltage). As discussed, the strong (S) control signal propagates through the set of power switch cells SW₁to SW₃₂sequentially and progressively coupling the global power rail Vdd to the local power rail Vdd2. At time t₃, the strong (S) control signal arrives at the R_Sinput of the control circuit 210; thereby, ending the strong (S) power rail coupling phase. As illustrated, during the strong (S) coupling phase, the slope of the current I₂drawn by the core coupled to the local power rail Vdd2 increases significantly, and may include an overshoot and oscillation towards a steady-state current. As a consequence of the strong (S) coupling, a speeding up of the full coupling of the global power rail Vdd to the local power rail Vdd2 occurs. As the core coupled to the local power rail Vdd2 is already drawing current I₂due to the weak (W) coupling phrase, the rate in which current I₂is drawn after time t₂does not significantly impact the supply voltage Vdd1. As a result, the supply voltage Vdd1 stays above the safe threshold voltage Vth.

FIG. 3 illustrates a schematic diagram of an example power switch cell 300 in accordance with another aspect of the disclosure. The power switch cell 300 may be an example implementation of each of the power switch cells SW₁to SW₃₂of power gating circuit 200.

With regard to the weak (W) control signal propagation path, the power switch cell 300 includes a first input buffer or inverter 310, a first FET M1 (which could be implemented as an n-channel metal oxide semiconductor (NMOS) FET or a p-channel metal oxide semiconductor (PMOS) FET), and a first output buffer or inverter 320. The first input buffer or inverter 310 includes an input serving as the weak (W) control signal input W_inof the power switch cell 300. The first FET M1 is coupled between the global power rail Vdd (via drain/source terminal) and the local power rail Vdd2 (via source/drain terminal), and includes a gate coupled to an output of the first input buffer or inverter 310. The first output buffer or inverter 320 includes an input coupled to the gate of the first FET M1, and an output serving as the weak (W) control signal output W_outof the power switch cell 300.

With regard to the strong (S) control signal propagation path, the power switch cell 300 includes a second input buffer or inverter 330, a second FET M2 (which could be implemented as an NMOS FET or PMOS FET), and a second output buffer or inverter 340. The second input buffer or inverter 330 includes an input serving as the strong (S) control signal input S_inof the power switch cell 300. The second FET M2 is coupled between the global power rail Vdd (via drain/source terminal) and the local power rail Vdd2 (via source/drain terminal), and includes a gate coupled to an output of the second input buffer or inverter 330. The second output buffer or inverter 340 includes an input coupled to the gate of the second FET M2, and an output serving as the strong (S) control signal output Sour of the power switch cell 300. As discussed, the second FET M2 may be larger than the first FET M1.

In operation, when the asserted weak (W) control signal (e.g., at a logic low voltage) propagates to the weak input W_inof the power switch cell 300, the first input inverter 310 inverts the weak (W) control signal to generate a logic high voltage. The logic high voltage is applied to the gate of the first NMOS FET M1; thereby, turning of the first FET M1, and coupling the global power rail Vdd to the local power rail Vdd2. The first output inverter 320 inverts the logic high voltage at the gate of the first NMOS FET M1 to output the asserted logic low weak (W) control signal for the following power switch cell or the input R_Wof the control circuit 210.

Similarly, when the asserted strong (S) control signal (e.g., at a logic low voltage) propagates to the strong input S_inof the power switch cell 300, the second input inverter 330 inverts the strong (S) control signal to generate a logic high voltage. The logic high voltage is applied to the gate of the second NMOS FET M2; thereby, turning of the second NMOS FET M2, and coupling the global power rail Vdd to the local power rail Vdd2. The second output inverter 340 inverts the logic high voltage at the gate of the second NMOS FET M2 to output the asserted logic low strong (S) control signal for the following power switch cell or the input R_Sof the control circuit 210.

Although the power gating circuit 200 provides an effective method of turning on the core coupled to the local power rail Vdd2 without significantly affecting the supply voltage Vdd1 at another local power rail (e.g., maintaining Vdd1 above the safe threshold voltage Vth), the power gating circuit 200 may consume significant amount of time to fully couple the global power rail Vdd to the local power rail Vdd2 due to the cascaded arrangement of the set of power switch cells (e.g., the wake-up time may be relatively large). Further, because each power switch cell includes two (2) input buffers or inverters and two (2) output buffers or inverters, there may be significant current leakage associated with the set of power switch cells; thereby, reducing the power efficiency of the power gating circuit 200. The buffers or inverters may also occupy significant IC footprint.

FIG. 4 illustrates a block diagram of another example power gating circuit 400 in accordance with another aspect of the disclosure. The power gating circuit 400 may be configured to provide a faster wake-up time to fully couple a global power rail Vdd to a local power rail Vdd2 compared to that of power gating circuit 200, while maintaining the supply voltage Vdd1 at another local power rail coupled to the global power rail Vdd above the safe threshold voltage Vth. Additionally, the power gating circuit 400 may also be configured to have less current leakage compared to that of power gating circuit 200 to reduce power consumption or operate the power gating circuit 400 in a more power efficient manner. Furthermore, the power gating circuit 400 may occupy significantly less IC footprint as compared to power gating circuit 200. As discussed further herein the power gating circuit 400 may have a “binary” power switch tree structure.

In particular, the power gating circuit 400 includes a first set of power switch cells SW₁₁to SW₁₄to SW₂₄to SW₈₄cascaded from I_Wand I_Soutputs of a control circuit 410 to R_Wand R_Sinputs of the control circuit 410, respectively. The power gating circuit 400 further includes sets of cascaded power switch cells SW₂₁to SW₈₁, SW₂₂to SW₈₂, and SW₂₃to SW₈₃coupled to or extending from nodes between distinct pairs SW₁₁/SW₁₂, SW₁₂/SW₁₃, and SW₁₃/SW₁₄of power switch cells of the first set, respectively. In this example, the sets of power switch cells SW₂₁to SW₈₁, SW₂₂to SW₈₂, and SW₂₃to SW₈₃do not terminate at the control circuit 410. As discussed in more detail herein, the sets of power switch cells SW₂₁to SW₈₁, SW₂₂to SW₈₂, and SW₂₃to SW₈₃include respective non-driving or end power switch cells SW₈₁to SW₈₃, which are depicted with a dark shading as they may not include output buffers or inverters because they do not drive a following power switch cell.

Note that a first subset SW₁₁to SW₁₄of the first set of power switch cells extend substantially orthogonal to the direction towards which the sets of power switch cells SW₂₁to SW₈₁, SW₂₂to SW₈₂, and SW₂₃to SW₈₃extend. Also note that a second subset SW₂₄to SW₈₄of the first set of power switch cells extend substantially parallel with the direction towards which the sets of power switch cells SW₂₁to SW₈₁, SW₂₂to SW₈₂, and SW₂₃to SW₈₃extend.

The power gating circuit 400 further includes non-driving or end power switch cells SW₃₁to SW₇₁(indicated with the dark shading) coupled to distinct pairs SW₂₁/SW₄₁, SW₄₁/SW₆₁, and SW₆₁/SW₈₁of the set of cascaded power switch cells SW₂₁to SW₈₁, respectively. The power gating circuit 400 also includes non-driving or end power switch cells SW₃₂to SW₇₂(indicated with the dark shading) coupled to distinct pairs SW₂₂/SW₄₂, SW₄₂/SW₆₂, and SW₆₂/SW₈₂of the set of cascaded power switch cells SW₂₂to SW₈₂, respectively. Additionally, the power gating circuit 400 also includes non-driving or end power switch cells SW₃₃to SW₇₃(indicated with the dark shading) coupled to distinct pairs SW₂₃/SW₄₃, SW₄₃/SW₆₃, and SW₆₃/SW₈₃of the set of cascaded power switch cells SW₂₃to SW₈₃, respectively. And, in this example, the power gating circuit 400 also includes non-driving or end power switch cells SW₃₄to SW₇₄(indicated with the dark shading) coupled to distinct pairs SW₂₄/SW₄₄, SW₄₄/SW₆₄, and SW₆₄/SW₈₄of the set of cascaded power switch cells SW₂₄to SW₈₄, respectively. All of the power switch cells of the power gating circuit 400 are coupled between a global power rail Vdd and a local power rail Vdd2.

The power gating circuit 400 may provide a faster wake-up time than the power gating circuit 200 because in power gating circuit 400, multiple power switch cells are turned on at substantially the same time. Assuming each of the power switch cells have substantially the same signal delay (D), after propagating through power switch cell SW₁₁, the control signal (weak or strong) turns on power switch cells SW₁₂and SW₂₁substantially simultaneously; then turns on power switch cells SW₁₃, SW₂₂, SW₄₁, and SW₃₁substantially simultaneously; then turns on power switch cells SW₁₄, SW₂₃, SW₄₂, SW₃₂, SW₆₁, and SW₅₁substantially simultaneously; and so on. With this tree structure (which may be referred to as a “binary” tree structure because the number of cells simultaneously activated increases and decreases in a manner similar to how binary numbers increase and decrease by one (1)), the turn-on progression is as follows: 1 cell, 2 cells, 4 cells, 6 cells, 7 cells, 6 cells, 4 cells, and 2 cells with an 8-cell delay (D). Whereas the power gating circuit 200 requires a 32-cell delay (D) to complete the propagation of a single control signal. Thus, the wake-up time may be decreased significantly using the power gating circuit 400.

FIG. 5 illustrates a schematic diagram of another example power switch cell 500 in accordance with another aspect of the disclosure. The power switch cell 500 may be an example implementation of any of the non-driving or end power switch cells SW₃₁to SW₇₁, SW₈₁, SW₃₂to SW₇₂, SW₈₂, SW₃₃to SW₇₃, SW₈₃, SW₃₄to SW₇₄, and SW₈₄of power gating circuit 400.

With regard to the weak (W) control signal path, the power switch cell 500 includes a first input buffer or inverter 510 and a first FET M1 (which could be implemented as an NMOS FET or PMOS FET). The first input buffer or inverter 510 includes an input serving as the weak (W) control signal input W_inof the power switch cell 500. The first FET M1 is coupled between the global power rail Vdd and the local power rail Vdd2, and includes a gate coupled to an output of the first input buffer or inverter 510. As the non-driving or end power switch cell 500 does not precede another power switch cell, it need not include an output buffer or inverter in the weak (W) control signal path. Thus, the power switch cell 500 may be described as having a floating weak (W) control signal output W_out.

With regard to the strong (S) control signal path, the power switch cell 500 includes a second input buffer or inverter 530 and a second FET M2 (which could be implemented as an NMOS FET or PMOS FET). The second input buffer or inverter 530 includes an input serving as the strong (S) control signal input S_inof the power switch cell 500. The second FET M2 is coupled between the global power rail Vdd and the local power rail Vdd2, and includes a gate coupled to an output of the second input buffer or inverter 530. As discussed, the second FET M2 may be larger than the first FET M1. As the non-driving or end power switch cell 500 does not precede another power switch cell, it need not include an output buffer or inverter in the strong (S) control signal path. Thus, the power switch cell 500 may be described as also having a floating strong (S) control signal output S_out.

Output buffers or inverters in a power switch cell are potential sources of current leakage. Accordingly, the power switch cell 500 may have less current leakage than the power switch cell 300 that includes output buffers or inverters 320 and 340. Comparing the power gating circuit 400 to power gating circuit 200, all of the power switch cells SW₁to SW₃₂in power gating circuit 200 include output buffers or inverters, whereas, in power gating circuit 400, only 17 out of 32 power switch cells have output buffers or inverters. Thus, the power gating circuit 400 may be about 50 percent greater in power efficiency compared to power gating circuit 200. Furthermore, output buffers or inverters also occupy IC footprint. By having non-driving or end power switch cells, the power gating circuit 400 may also have a smaller IC footprint compared to that of power gating circuit 200.

FIG. 6 illustrates a block diagram of another example power gating circuit 600 in accordance with another aspect of the disclosure. The power gating circuit 600 may also be configured to provide a faster wake-up time to fully couple a global power rail Vdd to a local power rail Vdd2 compared to that of power gating circuit 200, while maintaining the supply voltage Vdd1 at another local power rail (coupled to the global power rail Vdd) above the safe threshold voltage Vth. Additionally, the power gating circuit 600 may also be configured to have less current leakage compared to that of power gating circuit 200 to reduce power consumption or operate the power gating circuit 600 in a more power efficient manner. Additionally, the power gating circuit 600 may be implemented using a smaller IC footprint compared to power gating circuit 200.

As discussed in more detail herein, the power gating circuit 600 includes a power switch cell tree structure, which may be referred to as a “dangling” tree structure, because it includes power switching cells coupled in parallel with each power switch cell of a cascaded set. That is, from a top view of the tree structure, the parallel power switching cells appear to be “dangling” off of the corresponding cascaded power switching cell.

In particular, the power gating circuit 600 includes a first set of power switch cells SW₁to SW₁₂cascaded from I_Wand I_Soutputs of a control circuit 610 to R_Wand R_Sinputs of the control circuit 610, respectively. The first set of power switch cells SW₁to SW₁₂are coupled between a global power rail Vdd and a local power rail Vdd2, as previously discussed.

The power gating circuit 600 may further include a set of power switch cells coupled in parallel with each of the power switch cells SW₁to SW₁₂of the first set. For example, a first set of power switch cells SW₁₁to SW_1Kis coupled in parallel with power switch cell SW₁of the first set. A second set of power switch cells SW₂₁to SW_2Kis coupled in parallel with power switch cell SW₂of the first set. A third set of power switch cells SW₃₁to SW_3Kis coupled in parallel with power switch cell SW₃of the first set; and so on, with sets of power switch cells SW₄₁-SW_4Kto SW₁₂₁-SW_12Kcoupled in parallel with power switch cells SW₄to SW₁₂of the first set, respectively. The parallel power switching cells are also coupled between the global power rail Vdd and the local power rail Vdd2.

As each power switch cell of the sets of parallel power switch cells SW₁₁-SW_1Kto SW₁₂₁-SW_12Kdo not precede or drive another power switch cell, each power switch cell may be implemented as a non-driving or end power switch cell, such as power switch cell 500. As the power switch cell 500 does not include output buffers or inverters as previously discussed, the power switch cell 500 is less prone to current leakage and may have a smaller IC footprint compared to power switch cell 300 that includes output buffers or inverters. As an example, if K is equal to two (2), the power gating circuit 600 includes 36 power switch cells, where only 12 out of 36 include output buffers or inverters, whereas the power gating circuit 200 has 32 power switch cells, each having output buffers or inverters. Thus, the power gating circuit 600 may be about 67 percent greater in power efficiency and 3 percent smaller in IC footprint compared to power gating circuit 200.

In terms of wake-up time, each of the sets of parallel power switch cells SW₁-SW_1Kto SW₁₂-SW_12Kare woken up at substantially the same time by a corresponding control signal (weak (W) or strong (S)). As there are 12 power switch cells SW1 to SW12 cascaded from I_Wand I_Soutputs to R_Wand R_Sinputs of the control circuit 610, the wake-up time for the power gating circuit 600 is 2*12*D or 24D, where D is the control signal delay of each power switch cell (assuming the delay D is substantially the same for all power switch cells). Compared to power gating circuit 200, it includes 32 power switch cells SW₁to SW₃₂cascaded from I_Wand I_Soutputs to R_Wand R_Sinputs of the control circuit 210. Thus, the wake-up time for power gating circuit 200 is 2*32*D or 64D, which is much greater than the wake-up time of 24D of power gating circuit 600.

FIG. 7A illustrates a block diagram of another example power gating circuit 700 (weak (W) signal routing) in accordance with another aspect of the disclosure. In the power gating circuits 200, 400, and 600 previously discussed, the routing or cell-to-cell interconnection between power switch cells are the same for both the weak (W) and strong (S) control signals, albeit in parallel. However, it shall be understood that the routing or cell-to-cell interconnection between the power switch cells may be different for the weak (W) and strong (S) signals. The power gating circuit 700 is an example of such an implementation. FIG. 7A illustrates the routing or interconnection of power switch cells for the weak (W) control signal; whereas FIG. 7B, discussed further herein, illustrates the routing or interconnection of power switch cells for the strong (S) control signal.

More specifically, the power gating circuit 700 includes a first set of power switch cells SW₁to SW₈cascaded from an I_Woutput of a control circuit 710, similar to the cascaded implementation of power gating circuit 200. The power gating circuit 700 further includes a second set of power switch cells SW₉to SW₂₀cascaded from a weak (W) control signal output W_outof power switch cell SW₈to an R_Winput of the control circuit 710. Similar to the “dangling” tree structure of power gating circuit 600, the power gating circuit 700 further includes sets of power switch cells SW₉₁-SW_9Kto SW₂₀₁-SW_20Kcoupled in parallel with power switch cells SW₉to SW₂₀, respectively. Similar to the other power gating circuits, all of the power switch cells of power gating circuit 700 are coupled between a global power rail Vdd and a local power rail Vdd2. As the power switch cells SW₉₁-SW_9Kto SW₂₀₁-SW_20Kdo not precede or drive a following power switch cell, they each may be implemented as a non-driving or end power switch cell, such as power switch cell 500.

In operation, in response to receiving a PWR_ON signal instructing the power gating circuit 700 to turn on a core coupled to local power rail Vdd2, the control circuit 710 generates (asserts) the weak (W) control signal. The weak (W) control signal propagates first through the first set of power switch cells SW₁to SW₈causing them to sequentially couple the global power rail Vdd to the local power rail Vdd2. Then the weak (W) control signal propagates through the second set of power switch cells SW₉to SW₂₀, and to the sets of parallel power switch cells SW₉₁-SW_9Kto SW₂₀₁-SW_20K, sequentially causing them to couple the global power rail Vdd to the local power rail Vdd2 until the weak (W) control signal is received at the R_Winput of the control circuit 710.

FIG. 7B illustrates a block diagram of the power gating circuit 700 with the strong (S) control signal routing or cell-to-cell interconnection in accordance with another aspect of the disclosure. The routing or cell-to-cell interconnection for the strong (S) control signal is based on a binary tree structure similar to the tree structure of power gating circuit 400 previously discussed.

More specifically, the control circuit 710 includes a strong (S) control signal output I_Scoupled to a strong (S) control signal input of power switch cell SW₅. The strong (S) control signal is routed via a portion of the first set of power switch cells, namely power switch cells SW₅to SW₉. The strong (S) control signal is then routed from the strong (S) control signal output S_outof power switch cell SW₈to the strong (S) control signal input R_Sof the control circuit 710 via a second set of power switch cells SW₉, SW₁₆, and SW₁₇.

The strong (S) control signal is also routed from the strong (S) control signal output S_outof the power switch cell SW₅via a set of cascaded power switch cells SW₁₂, SW₁₃, SW₂₀, and SW₂₀₁. As indicated by its dark shading, the power switch cell SW₂₀₁may be a non-driving or end power switch cell, similar to power switch cell 500 previously discussed. Additionally, the strong (S) control signal is routed from the strong (S) control signal output S_outof power switch cell SW₆via a set of cascaded power switch cells SW₁₁, SW₁₄, SW₁₉, and SW₁₉₁. As indicated by its dark shading, the power switch cell SW₁₉₁may be a non-driving or end power switch cell, similar to power switch cell 500 previously discussed. Further, the strong (S) control signal is routed from the strong (S) control signal output S_outof power switch cell SW₇via a set of cascaded power switch cells SW₁₀, SW₁₅, SW₁₈, and SW₁₈₁. As indicated by its dark shading, the power switch cell SW₁₈₁may be a non-driving or end power switch cell, similar to power switch cell 500 previously discussed.

The strong (S) control signal is also routed from the strong (S) control signal outputs Sour of power switch cells SW₉to SW₁₃to power switch cells SW₉₁, SW₁₀₁, SW₁₁₁, SW₁₂₁, SW₁₃₁, SW₁₄₁, SW₁₅₁, and SW₁₆₁, respectively. As indicated by its dark shading, the power switch cells SW₉₁, SW₁₀₁, SW₁₁₁, SW₁₂₁, SW₁₃₁, SW₁₄₁, SW₁₅₁, and SW₁₆₁may be non-driving or end power switch cells, similar to power switch cell 500 previously discussed.

In operation, in response to receiving the weak (W) control signal at the R_Winput, the control circuit 710 generates (asserts) the strong (S) control signal. The strong (S) control signal propagates through the set of power switch cells SW₅to SW₉, SW₁₆, and SW₁₇to the R_Sinput of the control circuit 710, causing the power switch cells to sequentially couple the global power rail Vdd to the local power rail Vdd2. The strong (S) control signal also propagates along the sets of power switch cells SW₁₂, SW₁₃, SW₂₀, and SW₂₀₁, SW₁₁, SW₁₄, SW₁₉, and SW₁₉₁, and SW₁₀, SW₁₅, SW₁₈, and SW₁₈₁sequentially coupling the global power rail Vdd to the local power rail Vdd2, respectively. The strong (S) control signal also propagates to non-driving or end power switch cells SW₉₁, SW₁₀₁, SW₁₁₁, SW₁₂₁, SW₁₃₁, SW₁₄₁, SW₁₅₁, and SW₁₆₁further coupling the global power rail Vdd to the local power rail Vdd2, respectively.

FIG. 8 illustrates a schematic diagram of another example power switch cell 800 in accordance with another aspect of the disclosure. In the case of a power gating circuit where the weak (W) control signal has a cell-to-cell routing different than the strong (S) control signal (as in the case of power gating circuit 700), there may be one or more power switch cells that precedes or is driving a following power switch cell with respect to the weak (W) control signal, but not with respect to the strong (S) control signal. Such one or more power switch cells need not include an output buffer or inverter for the strong (S) control signal. The power switch cell 800 is an example detailed implementation of such one or more power switch cells.

In particular, with regard to the weak (W) control signal propagation path, the power switch cell 500 includes a first input buffer or inverter 810, a first FET M1 (which could be implemented as an NMOS FET or PMOS FET), and an output buffer or inverter 820. The first input buffer or inverter 810 includes an input serving as the weak (W) control signal input W_inof the power switch cell 800. The first FET M1 is coupled between the global power rail Vdd and the local power rail Vdd2, and includes a gate coupled to an output of the first input buffer or inverter 810. The output buffer or inverter 820 includes an input coupled to the gate of the first FET M1, and an output serving as the weak (W) control signal output W_outof the power switch cell 800.

With regard to the strong (S) control signal path, the power switch cell 800 includes a second input buffer or inverter 830 and a second FET M2 (which could be implemented as an NMOS FET or PMOS FET. The second input buffer or inverter 830 includes an input serving as the strong (S) control signal input S_inof the power switch cell 800. The second FET M2 is coupled between the global power rail Vdd and the local power rail Vdd2, and includes a gate coupled to an output of the second input buffer or inverter 830. As discussed, the second FET M2 may be larger than the first FET M1. As the power switch cell 800 does not precede another power switch cell with regard to the strong (S) control signal, it need not include an output buffer or inverter in the strong (S) control signal path. Thus, the power switch cell 800 may be described as also having a floating strong (S) control signal output Sour.

FIG. 9 illustrates a schematic diagram of another example power switch cell 900 in accordance with another aspect of the disclosure. Similarly, in the case of a power gating circuit where the weak (W) control signal has a cell-to-cell routing different than the strong (S) control signal, there may be one or more power switch cells that precedes or is driving a following power switch cell with respect to the strong (S) control signal, but not with respect to the weak (W) control signal. Such one or more power switch cells need not include an output buffer or inverter for the weak (W) control signal. The power switch cell 900 is an example detailed implementation of such one or more power switch cells.

In particular, with regard to the weak (W) control signal path, the power switch cell 900 includes a first input buffer or inverter 910 and a first FET M1 (which could be implemented as an NMOS FET or PMOS FET). The first input buffer or inverter 910 includes an input serving as the weak (W) control signal input W_inof the power switch cell 900. The first FET M1 is coupled between the global power rail Vdd and the local power rail Vdd2, and includes a gate coupled to an output of the first input buffer or inverter 910. As the power switch cell 900 does not precede another power switch cell with regard to the weak (W) control signal, it need not include an output buffer or inverter in the weak (W) control signal path. Thus, the power switch cell 500 may be described as having a floating weak (W) control signal output W_out.

With regard to the strong (S) control signal path, the power switch cell 900 includes a second input buffer or inverter 930, a second FET M2 (which could be implemented as an NMOS FET or PMOS FET, and an output buffer or inverter 940. The second input buffer or inverter 930 includes an input serving as the strong (S) control signal input S_inof the power switch cell 900. The second FET M2 is coupled between the global power rail Vdd and the local power rail Vdd2, and includes a gate coupled to an output of the second input buffer or inverter 930. As discussed, the second FET M2 may be larger than the first FET M1. The output buffer or inverter 940 includes an input coupled to the gate of the second FET M2, and an output serving as the strong (S) control signal output Sour of the power switch cell 900.

FIG. 10 illustrates a flow diagram of an example method 1000 of supplying power to a circuit (core) in accordance with another aspect of the disclosure. The method 1000 includes propagating a first control signal via a first set of cascaded power switch cells to sequentially couple a first power rail to a second power rail, wherein the second power rail is coupled to a circuit (block 1010). Examples of means for propagating a first control signal via a first set of cascaded power switch cells to sequentially couple a first power rail to a second power rail include any of the first sets of power switch cells SW₁₁to SW₈₄of power gating circuit 400, SW₁to SW₁₂of power gating circuit 600, SW₁to SW₂₀of power gating circuit 700 for the weak (W) control signal, and SW₅to SW₉, SW₁₆, and SW₁₇of power gating circuit 700 for the strong (S) control signal.

The method 1000 further includes propagating the first control signal via a second set of at least one power switch cell coupled between a first pair of power switch cells of the first set to couple the first power rail to the second power rail (block 1020). Examples of means for propagating the first control signal via a second set of at least one power switch cell coupled between a first pair of power switch cells of the first set include any of the sets of power switch cells, such as SW₂₁to SW₈₁, SW₂₂to SW₈₂, and SW₂₃to SW₈₃of power gating circuit 400, SW₁₁-SW_1Kto SW₁₂₁-SW_12Kof power gating circuit 600, SW₉₁-SW_9Kto SW₂₀₁-SW_20Kfor the weak (W) control signal of power gating circuit 700, and SW₁₂, SW₁₃, and SW₂₀, SW₁₁, SW₁₄, and SW₁₉, and SW₁₀, SW₁₅, and SW₁₈for the strong (S) control signal of power gating circuit 700.

According to the method 1000, the propagating of the first control signal may include propagating the first control signal from a first output of a control circuit to a first input of the control circuit. Examples of means for propagating the first control signal from a first output of a control circuit to a first input of the control circuit include any of the sets of power switch cells that are cascaded from an output (e.g., I_Wand/or I_S) to an input (e.g., R_Wand/or R_S) any of the control circuits described herein. The method 1000 may further include propagating a second control signal from a second output to a second input of the control circuit via the first set of cascaded power switch cells to sequentially couple the first power rail to the second power rail. Examples of means for propagating a second control signal from a second output to a second input of the control circuit via the first set of cascaded power switch cells to sequentially couple the first power rail to the second power rail include any of the sets of power switch cells that are cascaded from outputs (e.g., I_Wand I_S) to input (e.g., R_Wand R_S) any of the control circuits described herein.

According to the method 1000, the propagating the first control signal via the second set of at least one power switch cell includes propagating the first control signal via the second set of cascaded power switch cells to sequentially couple the first power rail to the second power rail. Examples of means for propagating the first control signal via the second set of cascaded power switch cells to sequentially couple the first power rail to the second power rail include any of the sets of cascaded power switch cells coupled between a pair of power switch cells of the first set. Additionally, the method 1000 may include propagating the first control signal via the second set of parallel power switch cells to couple the first power rail to the second power rail. Examples of means for propagating the first control signal via the second set of parallel power switch cells to couple the first power rail to the second power rail include any of the parallel power switch cells of power gating circuits 600 and 700.

FIG. 11 illustrates a block diagram of an example wireless communication device 1100 in accordance with another aspect of the disclosure. The wireless communication device 1100 includes an integrated circuit (IC) 1110, which may be configured as a system on chip (SOC). The SOC 1110 includes a first core 1130, a power gating circuit 1120, and a second core 1140. The power gating circuit 1120 may be implemented per any of the power gating circuits 400, 600, and 700 previously described. Accordingly, the power gating circuit 1120 is coupled to a global power rail Vdd, a first local power rail Vdd1, and a second local power rail Vdd2.

The first and second local power rails Vdd1 and Vdd2 are coupled to the first and second cores 1130 and 1140, respectively. The power gating circuit 1120 is configured to receive a power on signal (PWR_ON) for selectively coupling the global power rail Vdd to one or both of the local power rails Vdd1 and Vdd2 to selectively enable the first and/or second cores 1130 and 1140, respectively. As an example, the first core 1130 may be implemented as a central processing unit (CPU) core, and the second core 1140 may be implemented as modem core. Accordingly, the second core 1140 may include one or more signal processing cores configured to process a baseband (BB) signal.

The wireless communication device 1100 further includes a transceiver 1150 and at least one antenna 1160 (e.g., an antenna array). Pursuant to a signal transmission operation, the one or more digital signal processing cores 1140 generate and provide a BB transmit signal to the transceiver 1150. The transceiver 1150 is configured to generate a radio frequency (RF) transmit signal based on the BB transmit signal (e.g., frequency up-conversion, RF filtering, pre-amplifying, phase shifting, power amplifying, etc.). The transceiver 1150 provides the RF transmit signal to the at least one antenna 1160 for wireless transmission to one or more remote wireless communication devices.

Pursuant to a signal reception operation, the at least one antenna 1160 receives an RF signal from one or more remote wireless communication devices. The transceiver 1150 is configured to generate a BB receive signal based on the RF receive signal (e.g., RF filtering, low noise amplifying (LNA), frequency down-converting, phase shifting, IF and/or BB amplifying, etc.). The one or more digital signal processing cores 1140 then process the BB receive signal to recover data therefrom.

The following provides an overview of aspect of the present disclosure:

Aspect 1: An apparatus, including: a first power rail; a second power rail; a control circuit including a first input and a first output; a first set of power switch cells coupled to the first and second power rails, wherein the first set of power switch cells are cascaded from the first output to the first input of the control circuit; and a second set of at least one power switch cell coupled to the first and second power rails, wherein the second set of at least one power switch cell is coupled to one of a first node between a first pair of power switch cells of the first set, the first output of the control circuit, and the first input of the control circuit.

Aspect 2: The apparatus of aspect 1, wherein the second set of at least one power switch cell includes a second set of cascaded power switch cells extending from one of the first node, the first output of the control circuit, and the first input of the control circuit.

Aspect 3: The apparatus of aspect 2, wherein a first subset of the first set of cascaded power switch cells extends in a direction substantially orthogonal to a direction towards which the second set of cascaded power switch cells extend.

Aspect 4: The apparatus of aspect 3, wherein a second subset of the first set of cascaded power switch cells extends in a direction substantially parallel with the direction towards which the second set of cascaded power switch cells extend.

Aspect 5: The apparatus of any one of aspects 1-4, further including a third set of at least one power switch cell coupled to the first and second power rails, wherein the third set of at least one power switch cell is coupled to a second node between a second pair of power switch cells of the first set.

Aspect 6: The apparatus of aspect 5, wherein the third set of at least one power switch cell includes a third set of cascaded power switch cells extending from the second node.

Aspect 7: The apparatus of any one of aspects 2-6, further including a third (or fourth) set of at least one power switch cell coupled to the first and second power rails, wherein the third (or fourth) set of at least one power switch cell is coupled to a second node between a second pair of power switch cells of the second set.

Aspect 8: The apparatus of aspect 7, wherein the third (or fourth) set of at least one power switch cell does not precede another power switch cell.

Aspect 9: The apparatus of aspect 8, wherein the third set of at least one power switch cell includes: a first buffer or inverter including a first input coupled to a first output of one of the second set of cascaded power switch cells; a first field effect transistor (FET) coupled between the first and second power rails, wherein the first FET includes a first gate coupled to a first output of the first buffer or inverter; a second buffer or inverter including a second input coupled to a second output of the one of the second set of cascaded power switch cells; and a second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to a second output of the second buffer or inverter, and wherein the second FET is larger than the first FET.

Aspect 10: The apparatus of any one of aspects 2-9, wherein the second set of cascaded power switch cells includes a power switch cell that does not precede another power switch cell.

Aspect 11: The apparatus of any one of aspects 1-10, wherein each of the first set of cascaded power switch cells includes: a first buffer or inverter including a first input coupled to one of a first output of a preceding one of the first set of cascaded power switch cells and the first output of the control circuit; a first field effect transistor (FET) coupled between the first and second power rails, wherein the first FET includes a first gate coupled to a first output of the first buffer or inverter; a second buffer or inverter including a second input coupled to a second output of one of the preceding one of the first set of cascaded power switch cells and a second output of the control circuit; a second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to a second output of the second buffer or inverter, and wherein the second FET is larger than the first FET; a third buffer or inverter including a third input coupled to the first gate of the first FET, and a third output coupled to one of a first input of a following one of the first set of cascaded power switch cells or the first input of the control circuit; and a fourth buffer or inverter including a fourth input coupled to the second gate of the second FET, and a fourth output coupled to one of a second input of the following one of the first set of cascaded power switch cells and a second input of the control circuit.

Aspect 12: The apparatus of any one of aspects 1-10, wherein at least one of the first set of cascaded power switch cells or at least one of the second set of at least one power switch cell, includes: a first buffer or inverter including a first input coupled to one of a first output of a preceding power switch cell and the first output of the control circuit; a first field effect transistor (FET) coupled between the first and second power rails, wherein the first FET includes a first gate coupled to a first output of the first buffer or inverter; a second buffer or inverter including a second input coupled to one of a second output of the or another preceding power switch cell and a second output of the control circuit; a second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to a second output of the second buffer or inverter, and wherein the second FET is larger than the first FET; and a third buffer or inverter including a third input coupled to the first gate of the first FET, and a third output coupled to one of a first input of the following power switch cell and the first input of the control circuit, wherein the second gate is coupled to a floating output.