>The second bias voltage generation circuit M2 may generate the second bias voltage VB2 corresponding to the bias current IB. For example, the second bias voltage generation circuit M2 may include an NMOS transistor having a source terminal and a drain terminal connected between the first bias voltage generation circuit M1 and the supply terminal of the low voltage and a gate terminal, the drain terminal and gate terminal being connected to an output terminal of the second bias voltage VB2.

The first buffer BFF1 may receive the first bias voltage VB1, the second bias voltage VB2 and the source control signal LP, which are global signals. The first buffer BFF1 may be designed as an isolation buffer to prevent a coupling effect with the other buffers BFF2 to BFFn (refer to FIG. 2). For example, the buffer circuit included in the first buffer BFF1 may include a first driver M3, a second driver M4, a first inverter INV1, a second inverter INV2, a third driver M5 and a fourth driver M6. However, this is merely an embodiment, and the present disclosure may not be limited thereto. The configuration of the buffer circuit may vary as necessary.

The first driver M3 may be connected between a supply terminal of a high voltage, for example, VDD, and an output terminal of the first bias signal VB<1>. The first driver M3 may receive the first bias voltage VB1, and drive the output terminal of the first bias signal VB<1> with the high voltage according to the first bias voltage VB1.

The second driver M4 may be connected between the output terminal of the first bias signal VB<1> and the supply terminal of the low voltage, for example, VSS. The second driver M4 may receive the second bias voltage VB2, and drive the output terminal of the first bias signal VB<1> with the low voltage according to the second bias voltage VB2.

The first inverter INV1 may invert the source control signal LP and generate the first suppression control signal SC<1>.

The second inverter INV2 may invert the first suppression control signal SC<1> and generate a first driving control signal CC<1>.

The third driver M5 may be connected between the output terminal of the first bias signal VB<1> and the fourth driver M6. The third driver M5 may receive the first driving control signal CC<1>, and adjust a voltage level of the first bias signal VB<1> according to the first driving control signal CC<1>. When the first driving control signal CC<1> has a logic high level, i.e., “1”, the third driver M5 may increase a current flowing through the first driver M3, and decrease the voltage level of the first bias signal VB<1>. Accordingly, the operating current flowing through a current sinking element M11 of the first comparison circuit AMP1 may decrease. Conversely, when the first driving control signal CC<1> has a logic low level, i.e., “0”, the third driver M5 may decrease the current flowing through the first driver M3, and increase the voltage level of the first bias signal VB<1>. Accordingly, the operating current flowing through the current sinking element M11 of the first comparison circuit AMP1 may increase.

The fourth driver M6 may be connected between the third driver M5 and the supply terminal of the low voltage. The fourth driver M6 may receive the second bias voltage VB2.

Although an embodiment of the present disclosure has been described as an example that the buffer circuit includes one third driver M5 and one fourth driver M6, the present disclosure is not necessarily limited thereto, and the buffer circuit may include a plurality of third drivers M5 and a plurality of fourth drivers M6. In this case, the operating current may be finely and variously adjusted in an embodiment of the present disclosure. The source control signal LP may be designed to have a plurality of bits to control the plurality of third drivers M5.

The first comparison circuit AMP1 may include a first current source element M7, a second current source element M8, a first input element M9, a second input element M10, a first switch element TSW1, a second switch element TSW2 and the current sinking element M11.

The first current source element M7 may be connected between the supply terminal of the high voltage and an output terminal O1 of the first comparison signal C1<1>. For example, the first current source element M7 may include a PMOS transistor having a gate terminal connected to an inverting output terminal O2 and a source terminal and a drain terminal connected between the supply terminal of the high voltage and the output terminal O1 of the first comparison signal C1<1>.

The second current source element M8 may be connected between the supply terminal of the high voltage and the inverting output terminal O2. For example, the second current source element M8 may include a PMOS transistor having a gate terminal connected to the inverting output terminal O2 and a source terminal and a drain terminal connected between the supply terminal of the high voltage and the inverting output terminal O2.

The first input element M9 may be connected between the output terminal O1 and a common node CC. For example, the first input element M9 may include an NMOS transistor a gate terminal receiving the first pixel signal P<1> and a source terminal and a drain terminal connected between the output terminal O1 and the common node CC.

The second input element M10 may be connected between the inverting output terminal O2 and the common node CC. For example, the second input element M10 may include an NMOS transistor having a gate terminal receiving the ramp signal VR and a source terminal and a drain terminal connected between the inverting output terminal O2 and the common node CC.

The first switch element TSW1 may be connected between an input terminal of the first pixel signal P<1> and the output terminal O1. For example, the first switch element TSW1 may be shorted during an auto-zero period, and be open during the settling period and the comparison period.

The second switch element TSW2 may be connected between an input terminal of the ramp signal VR and the inverting output terminal O2. For example, the second switch element TSW2 may be shorted during the auto-zero period, and be open during the settling period and the comparison period.

The current sinking element M11 may be connected between the common node CC and the supply terminal of the low voltage. The current sinking element M11 may receive the first bias signal VB<1>, and generate the operating current corresponding to the first bias signal VB<1>. For example, the current sinking element M11 may include an NMOS transistor having a gate terminal connected to the output terminal of the first bias signal VB<1> and a source terminal and a drain terminal connected between the common node CC and the supply terminal of the low voltage.

FIG. 5 is a circuit diagram illustrating another example of the bias generator 140 illustrated in FIG. 1, the first buffer BFF1 illustrated in FIG. 2 and the first comparison circuit AMP1 illustrated in FIG. 3 in accordance with an embodiment of the present disclosure.

The bias generator 140 may include a first bias voltage generation circuit M19.

The first bias voltage generation circuit M19 may generate the first bias voltage VB1 corresponding to a bias current IB. For example, the first bias voltage generation circuit M19 may include an NMOS transistor having a source terminal and a drain terminal connected between an input node of the bias current IB and the supply terminal of the low voltage and a gate terminal, the drain terminal and gate terminal being connected to an output terminal of the first bias voltage VB1.

Since the first buffer BFF1 receives the first bias voltage VB1, a switching control signal SWEN and a source control signal LP, which are global signals, the first buffer BFF1 may be designed as an isolation buffer to prevent a coupling effect with the other buffers BFF2 to BFFn. For example, the first buffer BFF1 may include a switch VSW and an inverter INV.

The switch VSW may selectively transfer the first bias voltage VB1 as the first bias signal VB<1> on the basis of the switching control signal SWEN. For example, the switching control signal SWEN may be activated during the auto-zero period, and be deactivated during the settling period and the comparison period. Accordingly, the switch VSW may isolate the first buffer BFF1 from the other buffers BFF2 to BFFn at least during the comparison period. The first bias signal VB<1> may be held by a parasitic capacitor (not illustrated), which is connected to an output terminal of the first bias signal VB<1>, during the settling period and the comparison period.

The inverter INV may invert the source control signal LP and output the first suppression control signal SC<1>.

The first comparison circuit AMP1 may include a first current source element M12, a second current source element M13, a first input element M14, a second input element M15, a first switch element TSW11, a second switch element TSW12, a first current sinking element M16, a second current sinking element M17 and a third current sinking element M18.

The first current source element M12 may be connected between the supply terminal of the high voltage and an output terminal O11 of the first comparison signal C1<1>. For example, the first current source element M12 may include a PMOS transistor having a gate terminal connected to an inverting output terminal O12 and a source terminal and a drain terminal connected between the supply terminal of the high voltage and the output terminal O11 of the first comparison signal C1<1>.

The second current source element M13 may be connected between the supply terminal of the high voltage and the inverting output terminal O12. For example, the second current source element M13 may include a PMOS transistor having a gate terminal connected to the inverting output terminal O12 and a source terminal and a drain terminal connected between the supply terminal of the high voltage and the inverting output terminal O12.

The first input element M14 may be connected between the output terminal O11 and a common node CC1. For example, the first input element M14 may include an NMOS transistor having a gate terminal receiving the first pixel signal P<1> and a source terminal and a drain terminal connected between the output terminal O11 and the common node CC1.

The second input element M15 may be connected between the inverting output terminal O12 and the common node CC1. For example, the second input element M15 may include an NMOS transistor having a gate terminal receiving the ramp signal VR and a source terminal and a drain terminal connected between the inverting output terminal O12 and the common node CC1.

The first switch element TSW11 may be connected between an input terminal of the first pixel signal P<1> and the output terminal O11. For example, the first switch element TSW11 may be shorted during an auto-zero period, and be open during the settling period and the comparison period.

The second switch element TSW12 may be connected between an input terminal of the ramp signal VR and the inverting output terminal O12. For example, the second switch element TSW12 may be shorted during the auto-zero period, and be open during the settling period and the comparison period.

The first current sinking element M16 may be connected between the common node CC1 and the supply terminal of the low voltage. The first current sinking element M16 may receive the first bias signal VB<1>, and generate the operating current having the low level corresponding to the first bias signal VB<1>. For example, the first current sinking element M16 may include an NMOS transistor having a gate terminal connected to the output terminal of the first bias signal VB<1> and a source terminal and a drain terminal connected between the common node CC1 and the supply terminal of the low voltage.

The second current sinking element M17 may be connected between the third current sinking element M18 and the supply terminal of the low voltage. The second current sinking element M17 may receive the first bias signal VB<1>. For example, the second current sinking element M17 may include an NMOS transistor having a gate terminal connected to the output terminal of the first bias signal VB<1> and a source terminal and a drain terminal connected between the third current sinking element M18 and the supply terminal of the low voltage.

The third current sinking element M18 may be connected between the common node CC1 and the second current sinking element M17. The third current sinking element M18 may receive the first suppression control signal SC<1>, and generate the operating current having the high level according to the first suppression control signal SC<1>. When the first suppression control signal SC<1> is activated, the operating current may increase while an additional current path is formed through the second and third current sinking elements M17 and M18. For example, the third current sinking element M18 may include an NMOS transistor having a gate terminal connected to an output terminal of the first suppression control signal SC<1> and a source terminal and a drain terminal connected between the common node CC1 and the second current sinking element M17.

Hereinafter, an operation of the image sensor 100 in accordance with an embodiment of the present disclosure, which has the above-described configuration, is described with reference to FIGS. 6 and 7.

FIG. 6 is a timing diagram illustrating the operation of the image sensor 100 illustrated in FIG. 1 in accordance with an embodiment of the present disclosure. For example,