Reactive ion etching (RIE) is an etching process in which etching takes place by means of reactive ions that are produced in a gas discharge. In RIE, a physical component, namely removal through ejection of particles, and also a chemical component, namely removal through chemical reaction, work together in the removal process.

In wet chemical etching, etching solutions such as potassium hydroxide solution (KOH) are used in order to achieve a removal process through chemical reaction. The etching process can be direction-dependent, by which means different structures can be achieved.

In connection with step c)—implementation of the acoustically sensitive element—provision is made according to another improvement of the disclosure, per an embodiment, that step c) comprises an implementation on the front side of the wafer of a microphone in which the target gas is contained. This is preferably a condenser microphone in microsystems technology (MEMS microphone), in which the micromembrane that changes the electrical capacitance is implemented directly on the wafer.

Likewise in connection with step c), provision is made in accordance with another improvement of the disclosure, per an embodiment, that the wafer on the front side includes the second insulation layer, and step c) comprises the following steps:

- Partial removal of the second insulation layer by means of chemical and/or physical etching processes,
- Application of a cover plate to the front side of the wafer by means of photolithographic processes, wherein the cover plate has a perforated structure in the region of the removed second insulation layer,
- Creation of the second cavity between the cover plate and the buried insulation layer in the region of the perforated structure by means of chemical etching processes, and
- Sealing of the second cavity under target gas atmosphere by the application of a sealing layer to the cover plate under target gas atmosphere.

In an embodiment, the second insulation layer is removed on the front side in a region that corresponds to the applied heating structure and/or to the suspended thermal emitter on the back side. In other words, therefore, the second insulation layer preferably is removed opposite the heating structure and/or opposite the thermal emitter. In this way, the acoustically sensitive element is implemented directly opposite the first cavity, and, consequently, it is ensured that the first cavity and the second cavity are separated from one another solely by the buried insulation layer. During implementation of the acoustically sensitive element, the second insulation layer and the partially exposed silicon of the wafer preferably serve initially as supports for the cover plate, which has a perforated structure in the region of the removed second insulation layer and preferably forms the microphone diaphragm in this way.

After that, the silicon of the wafer that serves as a support under the perforated structure is preferably etched away, producing the second cavity. In order to introduce the target gas into the second cavity, the sealing layer is applied to the cover plate and thus also to the second cavity, preferably under target gas atmosphere.

In an embodiment, provision is made that the buried insulation layer functions as an etch stop during creation of the second cavity by means of chemical etching processes, in particular wet chemical etching. In this way, it can be ensured in a simple manner that the second cavity is separated from the first cavity by the insulation layer.

As already mentioned, the disclosure, per an embodiment, also relates to the photoacoustic gas sensor. The photoacoustic gas sensor for the target gas comprises the thermal emitter, the measuring volume designed as a first cavity, and the acoustically sensitive element, wherein the gas to be analyzed can flow through the measuring volume, wherein the acoustically sensitive element includes the second cavity in which the target gas is contained, and wherein the first cavity and the second cavity are separated from one another solely by the buried insulation layer of the silicon wafer used for production.

In contrast to gas sensors that are produced by the joining of multiple wafers, the photoacoustic gas sensor according to the disclosure, per an embodiment, is a gas sensor in monolithic construction. In this design, the photoacoustic gas sensor has only the buried insulation layer between the first cavity and the second cavity.

In addition, provision is made according to an improvement, per an embodiment, that no adhesive layer is present between the first cavity and the second cavity. Instead, on the one hand, the buried insulation layer forms the separator structure between the first cavity and the second cavity, and, at the same time, as an inherent component of the wafer, it provides the monolithic structure of the photoacoustic gas sensor.

BRIEF DESCRIPTION OF THE FIGURES

The disclosure is explained in further detail below on the basis of a preferred exemplary embodiment of the disclosure with reference to the drawings.

The drawings show:

FIGS. 1 and 2 schematic representations of the steps of a method for producing a photoacoustic gas sensor according to an exemplary embodiment of the disclosure.

DETAILED DESCRIPTION

The steps for producing a photoacoustic gas sensor 10 are shown schematically in FIGS. 1 and 2. In the present exemplary embodiment, the sensor is a CO2 microsensor 10 with a monolithic construction.

In the first step of the method, a wafer 12 made of silicon is provided, which is depicted at the very top in FIG. 1. The wafer 12 has a front side 14 and a back side 16. In addition, the wafer 12 has a buried insulation layer 18 within the silicon. The wafer 12 provided in this exemplary embodiment is an SOI wafer 12 that additionally has yet another insulation layer 20, 22 on each of its surfaces, which is to say the front side 14 and the back side 16. In the present case, the wafer 12 provided thus has the first insulation layer 20 on the back side 16, and the second insulation layer 22 on the front side 14, as well as the buried insulation layer 18 between the first insulation layer 20 and the second insulation layer 22 and within the silicon. Moreover, the wafer 12 provided in the present exemplary embodiment is a {100}Si wafer, which means that the front side 14 and back side 16 of the wafer 12 are formed by the crystal plane {100}.

The insulation layers 18, 20, and 22 of the wafer 12 are all made of silicon dioxide in the present case. Furthermore, a distance 24 between the first insulation layer 20 and the buried insulation layer 22 is 1000 μm in the present case. The first insulation layer 20 in the present case is 1.5 μm thick and the second insulation layer in the present case is 5 μm thick, while the buried insulation layer