In one embodiment of the present invention, fine patterning of an EL layer is performed without a shadow mask such as a metal mask. This allows fabrication of a display device with a high resolution and a high aperture ratio that has been difficult to achieve. Moreover, EL layers can be formed separately, enabling the display device to perform extremely clear display with high contrast and high display quality.

In the display device of one embodiment of the present invention, an island-shaped EL layer is formed by processing an EL layer deposited on the entire surface, not by using a pattern of a metal mask; thus, the island-shaped EL layer can have a uniform thickness. In addition, a high-resolution display device or a display device with a high aperture ratio, which has been difficult to achieve, can be fabricated. Moreover, EL layers can be formed separately for the respective colors, enabling the display device to perform extremely clear display with high contrast and high display quality. In addition, a sacrificial layer provided over an EL layer can reduce damage to the EL layer in the manufacturing process of the display device, increasing the reliability of the light-emitting element.

The display device of one embodiment of the present invention has a structure including an OS transistor and the light-emitting element having the MML (metal mask less) structure. With this structure, the leakage current that might flow through the transistor and the leakage current that might flow between adjacent light-emitting elements (also referred to as a lateral leakage current, a side leakage current, or the like) can become extremely low. With the structure, a viewer can notice any one or more of the image crispness, the image sharpness, a high chroma, and a high contrast ratio in an image displayed on the display device. With the structure where the leakage current that might flow through the transistor and the lateral leakage current that might flow between light-emitting elements are extremely low, display with little leakage of light at the time of black display (i.e., with few phenomena in which the black image looks whitish) (such display is also referred to as deep black display) can be achieved.

Here, if a single crystal silicon transistor provided in a single crystal silicon substrate is used as a driving transistor controlling current flowing through a light-emitting element, for example, the leakage current flowing through the transistor and the substrate between adjacent light-emitting elements might cause crosstalk between the light-emitting elements. However, since the display device of one embodiment of the present invention has the structure including an OS transistor, the leakage current that might flow through the transistor and the lateral leakage current between light-emitting elements can be extremely low, whereby crosstalk between the light-emitting elements can be inhibited.

The display device of one embodiment of the present invention can have a structure in which an insulator covering the end portion of the pixel electrode is not provided. In other words, an insulator is not provided between the pixel electrode and the EL layer in the structure. With such a structure, light can be efficiently extracted from the EL layer, leading to extremely low viewing angle dependence. For example, in the display device of one embodiment of the present invention, the viewing angle (the maximum angle with a certain contrast ratio maintained when the screen is seen from an oblique direction) can be greater than or equal to 100° and less than 180°, preferably greater than or equal to 150° and less than or equal to 170°. Note that the viewing angle refers to that in both the vertical direction and the horizontal direction. The display device of one embodiment of the present invention can have improved viewing angle dependence and high image visibility.

In the case where a display device is formed using the fine metal mask (FMM) structure, the pixel arrangement structure or the like is limited in some cases. Here, the FMM structure will be described below.

In the FMM structure, a metal mask provided with an opening portion (also referred to as an FMM) is set to be opposed to a substrate so that an EL can be deposited to a desired region at the time of EL evaporation. Then, the EL is deposited to the desired region by EL evaporation through the FMM. When the size of the substrate at the time of EL evaporation is larger, the size of the FMM is increased and accordingly the weight thereof is also increased. In addition, heat or the like is applied to the FMM at the time of EL evaporation and may change the shape of the FMM. Furthermore, there is a method in which EL evaporation is performed while a certain level of tension is applied to the FMM. Therefore, the weight and strength of the FMM are important parameters.

The pixel arrangement structure with an FMM needs to be designed under certain restrictions; for example, the above-described parameters and the like need to be considered. By contrast, in the display device of one embodiment of the present invention manufactured using an MML structure, an excellent effect such as higher flexibility in the pixel arrangement structure or the like than the FMM structure can be exhibited. This structure is highly compatible with a flexible device or the like, for example, and thus one or both of a pixel and a driver circuit can have a variety of circuit arrangements.

Here, description is made on the case where EL layers in light-emitting elements of two colors are separately formed, for simplicity. First, a stack of a first EL film and a first sacrificial film is formed to cover pixel electrodes. Next, a resist mask is formed over the first sacrificial film. Then, part of the first sacrificial film and part of the first EL film are etched using the resist mask, so that a first EL layer and a first sacrificial layer over the first EL layer are formed.

Next, a stack of a second EL film and a second sacrificial film is formed. Then, part of the second sacrificial film and part of the second EL film are etched using the resist mask, so that a second EL layer and a second sacrificial layer over the second EL layer are formed. Next, the pixel electrode is processed using the first sacrificial layer and the second sacrificial layer as a mask, so that a first pixel electrode overlapping with the first EL layer and a second pixel electrode overlapping with the second EL layer are formed. In this manner, the first EL layer and the second EL layer can be formed separately. Finally, the first sacrificial layer and the second sacrificial layer are removed, and a common electrode is formed, whereby light-emitting elements of two colors can be formed separately.

Furthermore, by repeating the above-described steps, EL layers in light-emitting elements of three or more colors can be separately formed; thus, a display device including light-emitting elements of three colors or four or more colors can be achieved.

At an end portion of the EL layer, a step is generated owing to a region where the pixel electrode and the EL layer are provided and a region where the pixel electrode and the EL layer are not provided. At the time of forming the common electrode over the EL layer, coverage with the common electrode is degraded owing to the step at the end portion of the EL layer, which might cause disconnection of the common electrode. Furthermore, the common electrode becomes thinner, whereby electric resistance might be increased.

In the case where an end portion of the pixel electrode is substantially aligned with the end portion of the EL layer and the case where the end portion of the pixel electrode is positioned outside the end portion of the EL layer, the common electrode and the pixel electrode are sometimes short-circuited when the common electrode is formed over the EL layer.

In one embodiment of the present invention, an insulating layer is provided between the first EL layer and the second EL layer, whereby unevenness on the surface where the common electrode is provided can be reduced. Thus, the coverage with the common electrode can be increased at the end portion of the first EL layer and the end portion of the second EL layer, which allows favorable conductivity of the common electrode. In addition, a short circuit between the common electrode and the pixel electrode can be inhibited.

In the case where EL layers for different colors are adjacent to each other, it is difficult to set the distance between the EL layers adjacent to each other to less than 10 μm with a formation method using a metal mask, for example; however, with the use of the above method, the distance can be decreased to less than or equal to 3 μm, less than or equal to 2 μm, or less than or equal to 1 μm. For example, with the use of an exposure apparatus for LSI, the distance can be decreased to less than or equal to 500 nm, less than or equal to 200 nm, less than or equal to 100 nm, or less than or equal to 50 nm. Accordingly, the area of a non-light-emitting region that may exist between two light-emitting elements can be significantly reduced, and the aperture ratio can be close to 100%. For example, the aperture ratio higher than or equal to 50%, higher than or equal to 60%, higher than or equal to 70%, higher than or equal to 80%, or higher than or equal to 90% and lower than 100% can be achieved.

Furthermore, a pattern of the EL layer itself can be made extremely smaller than that in the case of using a metal mask. For example, in the case of using a metal mask for forming EL layers separately, a variation in the thickness of the pattern occurs between the center and the edge of the pattern, which causes a reduction in an effective area that can be used as a light-emitting region with respect to the entire pattern area. By contrast, in the above fabrication method, a pattern is formed by processing a film formed to have a uniform thickness, which enables a uniform thickness in the pattern; thus, even with a fine pattern, almost the entire area can be used as a light-emitting region. Therefore, the above fabrication method makes it possible to achieve both a high resolution and a high aperture ratio.

As described above, with the above fabrication method, a display device in which minute light-emitting elements are integrated can be obtained, and it is not necessary to conduct a pseudo improvement in resolution by employing a unique pixel arrangement such as a PenTile arrangement; thus, the display device can achieve a resolution higher than or equal to 500 ppi, higher than or equal to 1000 ppi, higher than or equal to 2000 ppi, higher than or equal to 3000 ppi, or higher than or equal to 5000 ppi while having what is called a stripe pattern where R, G, and B are arranged in one direction.

More specific structure examples and fabrication method examples of a display device of one embodiment of the present invention will be described below with reference to drawings.

Structure Example 1

FIG. 1A is a schematic top view of a display device 100 of one embodiment of the present invention. The display device 100 includes a plurality of light-emitting elements 110R exhibiting red, a plurality of light-emitting elements 110G exhibiting green, and a plurality of light-emitting elements 110B exhibiting blue. In FIG. 1A, light-emitting regions of the light-emitting elements are denoted by R, G, and B to easily differentiate the light-emitting elements.

The light-emitting elements 110R, the light-emitting elements 110G, and the light-emitting elements 110B are arranged in a matrix. A pixel 103 illustrated in FIG. 1A employs what is called a stripe arrangement, in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light-emitting elements is not limited thereto; another arrangement method such as delta arrangement or zigzag arrangement may be used, or PenTile arrangement can be used.

As the light-emitting elements 110R, the light-emitting elements 110G, and the light-emitting elements 110B, EL elements such as OLEDs (Organic Light Emitting Diodes) or QLEDs (Quantum-dot Light Emitting Diodes) are preferably used. As examples of a light-emitting substance contained in the EL element, a substance that emits fluorescent light (a fluorescent material), a substance that emits phosphorescent light (a phosphorescent material), an inorganic compound (e.g., a quantum dot material), a substance exhibiting thermally activated delayed fluorescence (a thermally activated delayed fluorescence (TADF) material), and the like can be given.

FIG. 1B is a schematic cross-sectional view taken along a dashed-dotted line A1-A2 and a dashed-dotted line C1-C2 in FIG. 1A, and FIG. 1C is a schematic cross-sectional view taken along a dashed-dotted line B1-B2.

FIG. 1B illustrates cross sections of the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B. The light-emitting element 110R includes a pixel electrode 111R, an EL layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G includes a pixel electrode 111G, an EL layer 112G, the common layer 114, and the common electrode 113. The light-emitting element 110B includes a pixel electrode 111B, an EL layer 112B, the common layer 114, and the common electrode 113. Hereafter, the term “light-emitting element 110” is sometimes used to describe matters common to the light-emitting elements 110R, 110G, and 110B. In the description common to the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B, the term “pixel electrode 111” is used in some cases. In the description common to the EL layer 112R, the EL layer 112G, and the EL layer 112B, the alphabets are omitted from the reference numerals and the term “EL layer 112” is used in some cases.

FIG. 2A illustrates an enlarged view of a region surrounded by a squared dashed-dotted line in FIG. 1B. FIG. 2B illustrates an enlarged view of a region surrounded by the dashed-dotted square in FIG. 1C.

In this specification and the like, the thicknesses of a layer and a film are sometimes drawn to be larger for easy viewing in a drawing that is not enlarged. In an enlarged drawing, the distance between components included in a display device or the like may be differ. For example, the distance between end portions of the pixel electrode 111R and end portions of the EL layer 112R and the distance between end portions of the pixel electrode 111B and end portions of the EL layer 112B are drawn to be wide in FIG. 2A and the like. In addition, the interval between components of the light-emitting element 110B and components of the light-emitting element 110R is widely drawn.

The light-emitting element 110R includes the EL layer 112R between the pixel electrode 111R and the common electrode 113. The EL layer 112R contains at least a light-emitting organic compound that emits light with intensity in a red wavelength range. The light-emitting element 110G includes the EL layer 112G between the pixel electrode 111G and the common electrode 113. The EL layer 112G contains at least a light-emitting organic compound that emits light with intensity in the green wavelength range. The light-emitting element 110B includes the EL layer 112B between the pixel electrode 111B and the common electrode 113. The EL layer 112B contains at least a light-emitting organic compound that emits light with intensity in the blue wavelength range.

In FIG. 1B and FIG. 1C, the common layer 114 is provided between the pixel electrode 111 and the common electrode 113 of the light-emitting element 110. The common layer is provided as a continuous layer shared by the light-emitting elements. Note that the light-emitting element 110 does not necessarily include the common layer 114.

FIG. 1A also illustrates a connection electrode 111C that is electrically connected to the common electrode 113. The connection electrode 111C is supplied with a potential (e.g., an anode potential or a cathode potential) that is to be supplied to the common electrode 113. The connection electrode 111C is provided outside a display region where the light-emitting elements 110R and the like are arranged. In FIG. 1A, the common electrode 113 is denoted by a dashed line.

The connection electrode 111C can be provided along the outer periphery of the display region. For example, the connection electrode 111C may be provided along one side of the outer periphery of the display region or may be provided along two or more sides of the outer periphery of the display region. That is, in the case where the display region has a rectangular top surface, the top surface of the connection electrode 111C can have a belt-like shape, an L-like shape, a U-like shape (a square bracket shape), a quadrangular shape, or the like.

FIG. 1B illustrates a cross section corresponding to the dashed-dotted line C1-C2 shown in FIG. 1A. In the cross section taken along the C1-C2, a region 130 in which the connection electrode 111C and the common electrode 113 are electrically connected to each other is provided. Note that although FIG. 1B illustrates an example where the common layer 114 is provided between the connection electrode 111C and the common electrode 113, the common layer 114 is not necessarily provided in the region 130 as illustrated in FIG. 1D. In FIG. 1D, a structure in which the connection electrode 111C is in contact with the common electrode 113 can be provided, so that resistance such as contact resistance can be further reduced.

In the region 130, the common electrode 113 is provided over the connection electrode 111C and a protective layer 121 is provided to cover the common electrode 113.

The EL layer 112R, the EL layer 112G, and the EL layer 112B each include a layer containing a light-emitting organic compound (a light-emitting layer). The light-emitting layer may contain one or more kinds of compounds (e.g., a host material and an assist material) in addition to the light-emitting substance (a guest material). As the host material and the assist material, one or more kinds of substances whose energy gap is larger than the energy gap of the light-emitting substance (the guest material) can be selected and used. As the host material and the assist material, compounds that form an exciplex are preferably used in combination. In order to form an exciplex efficiently, it is particularly preferable to combine a compound that easily accepts holes (a hole-transport material) and a compound that easily accepts electrons (an electron-transport material).

Either a low molecular compound or a high molecular compound can be used for the light-emitting element, and an inorganic compound (e.g., a quantum dot material) may also be contained.

The EL layer 112R, the EL layer 112G, and the EL layer 112B may each include one or more of an electron-injection layer, an electron-transport layer, a hole-injection layer, and a hole-transport layer in addition to the light-emitting layer.

The pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B are provided for the respective light-emitting elements. The common electrode 113 is provided as a continuous layer shared by the light-emitting elements. A conductive film that has a property of transmitting visible light is used for either the respective pixel electrodes or the common electrode 113, and a reflective conductive film is used for the other. When the pixel electrodes have light-transmitting properties and the common electrode 113 has a reflective property, a bottom-emission display device can be obtained; by contrast, when the pixel electrodes have reflective properties and the common electrode 113 has a light-transmitting property, a top-emission display device can be obtained. Note that when both the pixel electrodes and the common electrode 113 have light-transmitting properties, a dual-emission display device can be obtained.

In the case where a conductive film having a property of reflecting visible light is used as the pixel electrode 111, silver, aluminum, titanium, tantalum, molybdenum, platinum, gold, titanium nitride, tantalum nitride, or the like can be used, for example. Alternatively, an alloy can be used for the pixel electrode 111. For example, an alloy containing silver can be used. As the alloy containing silver, an alloy containing silver, palladium, and copper can be used, for example. Alternatively, an alloy containing aluminum can be used, for example. Alternatively, a stack including two or more of these materials may be used.

As the pixel electrode 111, a conductive film having a property of reflecting visible light and a conductive film thereover having a property of transmitting visible light can be used. As a conductive material having a property of transmitting visible light, a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide containing gallium, indium-tin oxide containing silicon, or an indium-zinc oxide containing silicon can be used. Alternatively, an oxide of a conductive material having a property of reflecting visible light may be used, and the oxide may be formed by oxidation of a surface of the conductive material having a property of reflecting visible light. Specifically, titanium oxide may be used, for example. The titanium oxide may be formed by oxidation of a surface of titanium, for example.

Provision of an oxide over the surface of the pixel electrode 111 can inhibit, for example, an oxidation reaction with the pixel electrode 111 in formation of the EL layer 112.

When a stack of a conductive film having a property of reflecting visible light and a conductive film thereover having a property of transmitting visible light is provided as the pixel electrode 111, the conductive film having a property of transmitting visible light can function as an optical adjustment layer.

When the pixel electrode 111 includes an optical adjustment layer, an optical path length can be adjusted. The optical path length of the light-emitting element corresponds to, for example, the sum of the thickness of the optical adjustment layer and the thicknesses of the layers provided below the film including a light-emitting compound in the EL layer 112.

The optical path length is set different among the light-emitting elements using a microcavity structure, whereby light of a specific wavelength can be intensified. This can achieve a display device having a high color purity.

For example, the thickness of the EL layer 112 is set different among the light-emitting elements, whereby a microcavity structure can be achieved. For example, the EL layer 112R of the light-emitting element 110R emitting light whose wavelength is the longest can be made to have the largest thickness, and the EL layer 112B of the light-emitting element 110B emitting light whose wavelength is the shortest can be made to have the smallest thickness. Without limitation to this, the thickness of the EL layer can be adjusted in consideration of the wavelength of light emitted by the light-emitting element, the optical characteristics of the layer included in the light-emitting element, the electrical characteristics of the light-emitting element, and the like.

The top surface and end portions of the pixel electrode 111 are covered with the EL layer 112. End portions of the EL layer 112 are preferably positioned outside the end portions of the pixel electrode 111.

The EL layer 112 covering the top and end portion of the pixel electrode 111 makes it possible to perform a step for forming the EL layer 112, a step for forming the insulating layer 131, and the like without the pixel electrode 111 being exposed.

In the case where the end portions of the pixel electrode 111 and the like are exposed in an etching step at the formation of the EL layer 112 or the formation of the insulating layer 131, corrosion is generated in a region where the pixel electrode 111 is exposed in some cases. A product generated by corrosion of the pixel electrode 111 might be unstable; for example, the product might be dissolved in a solution in wet etching and might be diffused in an atmosphere in dry etching. With the dissolution in the solution of the product and scattering in the atmosphere, for example, the product might be attached to a side surface of the EL layer 112, a surface of the substrate 101, and the like, whereby a leakage path or the like may be formed between the plurality of the light-emitting elements 110.

The adhesion of a film to be the EL layer 112, a film to be the insulating layer 131, and the like may be reduced over the region where the pixel electrode 111 is exposed, and film separation or the like may occur.

When the top surface and the end portions of the pixel electrode 111 are covered with the EL layer 112, the yield of the light-emitting elements 110 can be improved, so that the display quality of the light-emitting elements 110 can be improved.

An insulating layer 131 is provided between adjacent light-emitting elements 110. The insulating layer 131 is positioned between the EL layers 112 included in the light-emitting elements 110. The common electrode 113 is provided over the insulating layer 131.

The insulating layer 131 is provided, for example, between two EL layers 112 exhibiting different colors. Alternatively, the insulating layer 131 is provided, for example, between two EL layers 112 exhibiting the same color. Alternatively, the following structure may be employed: the insulating layer 131 is provided between two EL layers 112 exhibiting different colors and is not provided between two EL layers 112 exhibiting the same color.

The insulating layer 131 is provided, for example, between two EL layers 112 in a top view.

It is preferable that the EL layer 112R, the EL layer 112G, and the EL layer 112B each include a region in contact with the top surface of the pixel electrode and a region in contact with the side surface of the insulating layer 131. The end portions of the EL layer 112R, the EL layer 112G, and the EL layer 112B are preferably in contact with the side surface of the insulating layer 131.

When the insulating layer 131 is provided between the light-emitting elements of different colors, the EL layer 112R, the EL layer 112G, and the EL layer 112G can be inhibited from being in contact with each other. This can suitably prevent unintentional light emission due to a current flowing through the two adjacent EL layers. As a result, the contrast can be increased to achieve a display device with high display quality.

The insulating layer 131 includes an insulating layer 131a and an insulating layer 131b. The insulating layer 131b is provided so as to be in contact with the side surfaces of the EL layers 112 included in the light-emitting elements 110. Furthermore, the insulating layer 131a is provided over and in contact with the insulating layer 131b so as to fill a depressed portion of the insulating layer 131b in a cross-sectional view.

In the top view of FIG. 1, the insulating layer 131 is placed between the EL layers 112 of adjacent pixels so as to have a mesh (also referred to as grid or matrix) shape.

The insulating layer 131 is provided, for example, between two EL layers 112 exhibiting different colors. Alternatively, the insulating layer 131 is provided, for example, between two EL layers 112 exhibiting the same color. Alternatively, the following structure may be employed: the insulating layer 131 is provided between two EL layers 112 exhibiting different colors and is not provided between two EL layers 112 exhibiting the same color.

The insulating layer 131 is provided, for example, between two EL layers 112 in a top view.

The end portion of the EL layer 112 preferably includes a region in contact with the insulating layer 131b.

When the insulating layer 131 is provided between the light-emitting elements of different colors, the EL layer 112R, the EL layer 112G, and the EL layer 112G can be inhibited from being in contact with each other. This can suitably prevent unintentional light emission due to a current flowing through the two adjacent EL layers. As a result, the contrast can be increased to achieve a display device with high display quality.

The insulating layer 131 may be provided not between adjacent pixels exhibiting the same color but only between pixels exhibiting different colors. In this case, the insulating layer 131 can have a stripe shape in a top view. When the insulating layer 131 has a stripe shape, the space necessary to form the insulating layer 131 becomes unnecessary and a high aperture ratio can be achieved compared with the case where the insulating layer 131 has a grid shape. In the case where the insulating layer 131 has a stripe shape, the adjacent EL layers of the same color may be processed in a band shape so as to be continuous in a column direction.

The common layer 114 is preferably provided in contact with the top surface of the EL layer 112, the top surface of the insulating layer 131a, and the top surface of the insulating layer 131b. The common electrode 113 is preferably provided in contact with the top surface of the common layer 114. In the case where the light-emitting elements 110 do not include the common layer 114, the common electrode 113 is preferably provided in contact with the top surface of the EL layer 112, the top surface of the insulating layer 131a, and the top surface of the insulating layer 131b.

Between the adjacent light-emitting elements, a step is generated at the end portions of the EL layer 112 owing to a region where the EL layer 112 is provided and a region where the EL layer 112 is not provided. By including the insulating layer 131a and the insulating layer 131b in the display device of one embodiment of the present invention, the step can be planarized and coverage with the common electrode can be improved as compared with the case where the common electrode 113 is provided in contact with the substrate 101 between the adjacent light-emitting elements. Thus, connection failures due to the disconnection at the step can be inhibited. Alternatively, it is possible to inhibit an increase in electric resistance due to local thinning of the common electrode 113 by the step.

In one embodiment of the present invention, provision of the insulating layer 131a and the insulating layer 131b between the EL layers 112 that are placed adjacent to each other can make the unevenness on the formation surface of the common electrode 113 smaller, whereby coverage with the common electrode 113 at the end portion of the EL layer 112 can be increased and favorable conductivity of the common electrode 113 can be achieved.

For the formation surface of the common electrode 113 to have higher planarity, the top surface of the insulating layer 131a and the top surface of the insulating layer 131b are preferably substantially level with the top surface of the EL layer 112 in the end portions of the EL layer 112. In addition, the top surface of the insulating layer 131 preferably has a flat shape. Note that it is not always necessary that the top surface of the insulating layer 131a, the top surface of the insulating layer 131b, and the top surface of the EL layer 112 are aligned with each other. In the case where the levels of the top surfaces of the EL layers 112 are different in the EL layers 112 corresponding to different colors, the level of the top surface of the insulating layer 131a is preferably substantially level with the level of the top surface of the EL layer in the vicinity of the EL layer. The level of the top surface of the insulating layer 131b is preferably substantially level with the level of the EL layer in a region in contact with the side surfaces of the EL layers.

As illustrated in FIG. 2A and the like, the level of the top surface of the insulating layer 131a is, for example, substantially level with the level of the top surface of the EL layer 112B in the vicinity of the EL layer 112B, and substantially level with the level of the top surface of the EL layer 112R in the vicinity of the EL layer 112R. The level of the top surface of the insulating layer 131b is, for example, substantially level with the level of the top surface of the EL layer 112B in a region in contact with a side surface of the EL layer 112B, and substantially level with the level of the top surface of the EL layer 112R in a region in contact with a side surface of the EL layer 112R.

FIG. 2C illustrates an example in which the shape of the insulating layer 131a or the like is different from that in FIG. 2B. In FIG. 2C, the level of the top surface of the insulating layer 131a is lower than the level of the end portions of the EL layer 112.

FIG. 3A and FIG. 3B each illustrate an example in which the shape of the insulating layer 131a or the like is different from that in FIG. 2A and FIG. 2B. In FIG. 3A and FIG. 3B, the top surface of the insulating layer 131a has a hollow shape in the center and its vicinity.

FIG. 3C illustrates an example in which the shape of the insulating layer 131a or the like is different from that in FIG. 2B. In FIG. 3C, the top surface of the insulating layer 131a has a bulging shape in the center and its vicinity.

The insulating layer 131b includes a region in contact with the side surface of the EL layer 112 and functions as a protective insulating layer of the EL layer 112. Provision of the insulating layer 131b can inhibit oxygen, moisture, or constituent elements thereof from entering the inside of the EL layer 112 through the side surface thereof, whereby a highly reliable display device can be provided.

If the width of the insulating layer 131b in the region in contact with the side surface of the EL layer 112 is large in a cross-sectional view, the distance between the EL layers 112 is increased and the aperture ratio is lowered in some cases. If the width of the insulating layer 131b is small, the effect of inhibiting the entry of oxygen, moisture, or constituent elements thereof into the inside of the EL layer 112 through the side surface thereof becomes small in some cases. The width of the insulating layer 131b in the region in contact with the side surface of the EL layer 112 is preferably greater than or equal to 3 nm and less than or equal to 200 nm, further preferably greater than or equal to 3 nm and less than or equal to 150 nm, further preferably greater than or equal to 5 nm and less than or equal to 150 nm, still further preferably greater than or equal to 5 nm and less than or equal to 100 nm, still further preferably greater than or equal to 10 nm and less than or equal to 100 nm, yet further preferably greater than or equal to 10 nm and less than or equal to 50 nm. When the width of the insulating layer 131b is within the above-described range, a highly reliable display device with a high aperture ratio can be obtained.

The insulating layer 131b can be an insulating layer containing an inorganic material. As the insulating layer 131b, a single layer or stacked layers of aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, or the like can be used, for example. In particular, aluminum oxide is preferable because it has high selectivity with respect to the EL layer 112 in etching and has a function of protecting the EL layer 112 in forming the insulating layer 131b which is to be described later. In particular, with the use of an inorganic insulating material such as aluminum oxide, hafnium oxide, or silicon oxide formed by an ALD method for the insulating layer 131b, the insulating layer 131b can be a film with few pinholes and can have an excellent function of protecting the EL layer 112.

Note that in this specification, an oxynitride refers to a material that contains more oxygen than nitrogen in its composition, and a nitride oxide refers to a material that contains more nitrogen than oxygen in its composition. For example, in the case where silicon oxynitride is described, it refers to a material that contains more oxygen than nitrogen in its composition. In the case where silicon nitride oxide is described, it refers to a material that contains more nitrogen than oxygen in its composition.

For the formation of the insulating layer 131b, a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like can be used. An ALD method achieving favorable coverage can be suitably used for forming the insulating layer 131b.

The insulating layer 131a provided over the insulating layer 131b has a function of filling the depressed portion of the insulating layer 131b, which is formed between the adjacent light-emitting elements. In other words, the insulating layer 131a has an effect of improving the planarity of the formation surface of the common electrode 113. An insulating layer containing an organic material can be suitably used for the insulating layer 131a. As the insulating layer 131a, an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a polyimide-amide resin, a siloxane resin, a benzocyclobutene-based resin, a phenol resin, a precursor of any of these resins, or the like can be used, for example. Moreover, the insulating layer 131a can be formed using a photosensitive resin. As the photosensitive resin, a positive material or a negative material can be used.

When the insulating layer 131a is formed using a photosensitive resin, the insulating layer 131a can be fabricated only by light exposure and development steps.

For example, the difference in level between the top surface of the insulating layer 131a and the top surface of the EL layer 112 is preferably less than or equal to 0.5 times, further preferably less than or equal to 0.3 times as larger as the thickness of the insulating layer 131a. In addition, for example, the insulating layer 131a may be provided so that the top surface of the EL layer 112 is higher than the top surface of the insulating layer 131a. Furthermore, for example, the insulating layer 131a may be provided so that the top surface of the insulating layer 131a is higher than the top surface of the light-emitting layer included in the EL layer 112. It is preferable that the thickness of the insulating layer 131a be, for example, greater than or equal to 0.3 times, greater than or equal to 0.5 times, or greater than or equal to 0.7 times as large as the thickness of the pixel electrode 111.

A protective layer 121 is provided over the common electrode 113 to cover the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B. The protective layer 121 has a function of preventing diffusion of impurities such as water into the light-emitting elements from above.

The protective layer 121 can have, for example, a single-layer structure or a stacked-layer structure at least including an inorganic insulating film. Examples of the inorganic insulating film include an oxide film and a nitride film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material such as an indium gallium oxide or an indium gallium zinc oxide may be used for the protective layer 121.

As the protective layer 121, a stacked-layer film of an inorganic insulating film and an organic insulating film can be used. For example, a structure where an organic insulating film is interposed between a pair of inorganic insulating films is preferable. Furthermore, the organic insulating film preferably functions as a planarization film. This enables the top surface of the organic insulating film to be flat, and accordingly coverage with the inorganic insulating film thereover is improved, leading to an improvement in barrier properties. Moreover, this structure is preferable because when a component (e.g., a color filter, an electrode of a touch sensor, a lens array, or the like) is provided above the protective layer 121, the flat top surface of the protective layer 121 allows the component to be less affected by an uneven shape caused by the lower components.

Like the common electrode 113, the common layer 114 is provided across a plurality of light-emitting elements. The common layer 114 is provided to cover the EL layer 112R, the EL layer 112G, and the EL layer 112B. The structure including the common layer 114 can simplify the fabrication process, reducing the fabrication cost. The common layer 114 and the common electrode 113 can be formed successively without an etching step or the like between formations of the common layer 114 and the common electrode 113. Thus, the interface between the common layer 114 and the common electrode can be clean, and the light-emitting element can have favorable characteristics.

Each of the EL layer 112R, the EL layer 112G, and the EL layer 112B preferably includes at least a light-emitting layer containing a light-emitting material emitting light of one color, for example. The common layer 114 preferably includes one or more of an electron-injection layer, an electron-transport layer, a hole-injection layer, and a hole-transport layer, for example. In the light-emitting element in which the pixel electrode serves as an anode and the common electrode serves as a cathode, a structure including the electron-injection layer or a structure including the electron-injection layer and the electron-transport layer can be used as the common layer 114.

Manufacturing Method Example 1

An example of a manufacturing method of the display device of one embodiment of the present invention will be described below with reference to drawings. Here, description is made using the display device 100 described in the above structure example as an example. FIG. 4A to FIG. 7C are schematic cross-sectional views in steps of the manufacturing method of the display device described below as an example.

Note that thin films that constitute the display device (insulating films, semiconductor films, conductive films, or the like) can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like. Examples of the CVD method include a plasma-enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. In addition, an example of a thermal CVD method is a metal organic CVD (MOCVD) method.

Alternatively, thin films that constitute the display device (insulating films, semiconductor films, conductive films, or the like) can be formed by a method such as spin coating, dipping, spray coating, ink-jetting, dispensing, screen printing, offset printing, a doctor knife method, a slit coater, a roll coater, a curtain coater, or a knife coater.

Thin films that constitute the display device can be processed by a photolithography method or the like. Besides, a nanoimprinting method, a sandblasting method, a lift-off method, or the like may be used for the processing of the thin films. Alternatively, island-shaped thin films may be directly formed by a film formation method using a shielding mask such as a metal mask.

There are the following two typical examples of a photolithography method. In one of the methods, a resist mask is formed over a thin film that is to be processed, the thin film is processed by etching or the like, and then the resist mask is removed. In the other method, a photosensitive thin film is formed and then processed into a desired shape by light exposure and development.

As the light used for light exposure in the photolithography method, for example, an i-line (with a wavelength of 365 nm), a g-line (with a wavelength of 436 nm), an h-line (with a wavelength of 405 nm), or combined light of any of them can be used. Alternatively, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. In addition, light exposure may be performed by liquid immersion exposure technique. As the light used for light exposure, extreme ultraviolet (EUV) light or X-rays may also be used. Furthermore, instead of the light used for the light exposure, an electron beam can also be used. It is preferable to use EUV light, X-rays, or an electron beam because they can perform extremely minute processing. Note that a photomask is not needed when light exposure is performed by scanning with a beam such as an electron beam.

For etching of thin films, a dry etching method, a wet etching method, a sandblast method, or the like can be used.

[Preparation for Substrate 101]

As the substrate 101, a substrate having at least heat resistance high enough to withstand the following heat treatment can be used. In the case where an insulating substrate is used as the substrate 101, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, an organic resin substrate, or the like can be used. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate using silicon or silicon carbide as a material, a compound semiconductor substrate of silicon germanium or the like, a semiconductor substrate such as an SOI substrate, or the like can be used.

As the substrate 101, it is particularly preferable to use the semiconductor substrate or the insulating substrate over which a semiconductor circuit including a semiconductor element such as a transistor is formed. The semiconductor circuit preferably forms a pixel circuit, a gate line driver circuit (a gate driver), a source line driver circuit (a source driver), or the like. In addition to the above, an arithmetic circuit, a memory circuit, or the like may be formed.

Then, a conductive film to be the pixel electrode 111 is formed over the substrate 101. Next, part of the conductive film is etched, and the pixel electrode 111R, the pixel electrode 111G, the pixel electrode 111B, and the connection electrode 111C are formed over the substrate 101 (FIG. 4A).

In the case where a conductive film having a property of reflecting visible light is used as the pixel electrode, a material that has a reflectance as high as possible in the whole wavelength range of visible light (e.g., silver, aluminum, or the like) is preferably used. This can increase color reproducibility as well as light extraction efficiency of the light-emitting elements.

[Formation of EL Film 112Rf]

Next, an EL film 112Rf to be the EL layer 112R later is deposited over the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B.

The EL film 112Rf includes at least a film containing a light-emitting compound. Besides, a structure where one or more of films functioning as an electron-injection layer, an electron-transport layer, a charge generation layer, a hole-transport layer, and a hole-injection layer are stacked may be employed. The EL film 112Rf can be formed by, for example, an evaporation method, a sputtering method, an inkjet method, or the like. Note that without limitation to this, the above deposition method can be used as appropriate.

[Formation of Sacrificial Film 144(1)R and Sacrificial Film 144(2)R]

Next, the deposition step of sacrificial films will be described.

A sacrificial film 144R is a film to be the sacrificial layer 145R. A sacrificial film 144G is a film to be a sacrificial layer 145G. A sacrificial film 144B is a film to be a sacrificial layer 145B. The sacrificial layer 145R, the sacrificial layer 145G, and the sacrificial layer 145B are collectively referred to as the sacrificial layer 145 in some cases. The sacrificial layer 145 may have a single-layer structure or a stacked-layer structure of two or more layers.

An example in which a sacrificial layer with a two-layer structure is used will be described below.

In the example described below, a stacked-layer structure of a sacrificial film 144(1)R and a sacrificial film 144(2)R is used for the sacrificial film 144R, a stacked-layer structure of a sacrificial film 144(1)G and a sacrificial film 144(2)G is used as the sacrificial film 144G, and a stacked-layer structure of a sacrificial film 144(1)B and a sacrificial film 144(2)B is used as the sacrificial film 144B.

The sacrificial film 144(1)R is a film to be the sacrificial layer 145(1)R, and the sacrificial film 144(2)R is a film to be the sacrificial layer 145(2)R. The sacrificial film 144(1)G is a film to be the sacrificial layer 145(1)G, and the sacrificial film 144(2)G is a film to be the sacrificial layer 145(2)G. The sacrificial film 144(1)B is a film to be the sacrificial layer 145(1)B, and the sacrificial film 144(2)B is a film to be the sacrificial layer 145(2)B.

In the deposition step of the sacrificial film, first, the sacrificial film 144(1)R is formed to cover the EL film 112Rf. Moreover, the sacrificial film 144(1)R is provided in contact with the top surface of the connection electrode 111C. Next, the sacrificial film 144(2)R is formed over the sacrificial film 144(1)R.

The sacrificial film 144(1)R and the sacrificial film 144(2)R can be formed by a sputtering method, an ALD method (a thermal ALD method or a PEALD method), or a vacuum evaporation method, for example. A formation method that gives less damage to an EL layer is preferred, and for the sacrificial film 144(1)R directly formed over the EL film 112Rf, an ALD method or a vacuum evaporation method is more suitable for the formation of the sacrificial film 144(1)R than a sputtering method.

For example, an inorganic film such as a metal film, an alloy film, a metal oxide film, a semiconductor film, or an inorganic insulating film can be suitably used as the sacrificial film 144(1)R.

Alternatively, an oxide film can be used as the sacrificial film 144(1)R. Typically, an oxide film or an oxynitride film such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, or hafnium oxynitride can be used. Alternatively, a nitride film can be used as the sacrificial film 144(1)R, for example. Specifically, it is possible to use a nitride such as silicon nitride, aluminum nitride, hafnium nitride, titanium nitride, tantalum nitride, tungsten nitride, gallium nitride, or germanium nitride. A film containing such an inorganic insulating material can be formed by a film formation method such as a sputtering method, a CVD method, or an ALD method; the sacrificial film 144(1)R, which is formed directly over the EL film 112Rf, is particularly preferably formed by an ALD method.

For the sacrificial film 144(1)R, a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, or tantalum or an alloy material containing the metal material can be used. It is particularly preferable to use a low-melting-point material such as aluminum or silver.

A metal oxide such as an indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO) can be used for the sacrificial film 144(1)R. It is also possible to use indium oxide, an indium zinc oxide (an In—Zn oxide), an indium tin oxide (an In—Sn oxide), an indium titanium oxide (an In—Ti oxide), an indium tin zinc oxide (an In—Sn—Zn oxide), an indium titanium zinc oxide (an In—Ti—Zn oxide), an indium gallium tin zinc oxide (an In—Ga—Sn—Zn oxide), or the like. Alternatively, an indium tin oxide containing silicon or the like can also be used.

Note that an element M (Mis one or more kinds selected from aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) may be used instead of gallium. In particular, M is preferably one or more kinds selected from gallium, aluminum, and yttrium.

Any of the above-described materials usable for the sacrificial film 144(1)R can be used for the sacrificial film 144(2)R. From the above materials usable for the sacrificial film 144(1)R, one material can be selected for the sacrificial film 144(1)R and another material can be selected for the sacrificial film 144(2)R. One or more of the above materials usable for the sacrificial film 144(1)R can be selected for the sacrificial film 144(1)R, and a material other than the material(s) selected for the sacrificial film 144(1)R can be selected for the sacrificial film 144(2)R.

As the sacrificial film 144(1)R, it is possible to use a film highly resistant to etching treatment performed on various EL films such as the EL film 112Rf, i.e., a film having high etching selectivity. Moreover, as the sacrificial film 144(1)R, it is particularly preferable to use a film that can be removed by a wet etching method that is less likely to cause damage to the EL film.

Moreover, a material that can be dissolved in a solvent chemically stable with respect to at least a film positioned in the uppermost portion of the EL film 112Rf may be used for the sacrificial film 144(1)R. In particular, a material that is dissolved in water or alcohol can be suitably used for the sacrificial film 144(1)R. In deposition of the sacrificial film 144(1)R, it is preferable that application of such a material dissolved in a solvent such as water or alcohol be performed by a wet film formation method and followed by heat treatment for evaporating the solvent. At this time, the heat treatment is preferably performed in a reduced-pressure atmosphere, in which case the solvent can be removed at a low temperature in a short time and thermal damage to the EL film 112Rf can be reduced accordingly.

Examples of the wet film formation method that can be employed for the formation of the sacrificial film 144(1)R include spin coating, dipping, spray coating, ink-jetting, dispensing, screen printing, offset printing, a doctor knife method, a slit coater, a roll coater, a curtain coater, a knife coater, and the like.

For the sacrificial film 144(1)R, an organic material such as polyvinyl alcohol (PVA), polyvinylbutyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or an alcohol-soluble polyamide resin can be used.

As the sacrificial film 144(2)R, a film having high etching selectivity with respect to the sacrificial film 144(1)R is used.

It is particularly preferable that an inorganic insulating material such as aluminum oxide, hafnium oxide, or silicon oxide, which is formed by an ALD method, be used for the sacrificial film 144(1)R, and a metal oxide containing indium such as indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), which is formed by a sputtering method, be used for the sacrificial film 144(2)R.

An organic film that can be used as the EL film 112Rf or the like can be used as the sacrificial film 144(2)R. For example, the organic film that is used as the EL film 112Rf, an EL film 112Gf, or an EL film 112Bf can be used as the sacrificial film 144(2)R. The use of such an organic film is preferable, in which case the deposition apparatus for the EL film 112Rf or the like can be used in common. Furthermore, a sacrificial layer 145(2)R can be removed at the same time as the etching of the EL film 112Rf or the like; thus, the process can be simplified.

For example, in the case where dry etching using a gas containing fluorine (also referred to as a fluorine-based gas) is used for the etching of the sacrificial film 144(1)R, silicon, silicon nitride, silicon oxide, tungsten, titanium, molybdenum, tantalum, tantalum nitride, an alloy containing molybdenum and niobium, an alloy containing molybdenum and tungsten, or the like can be used for the sacrificial film 144(2)R. Here, a metal oxide film such as IGZO or ITO is given as a film having high etching selectivity (that is, enabling low etching rate) in dry etching using the fluorine-based gas, and such a film can be used as the sacrificial film 144(1)R.

[Formation of Resist Mask 143a]

Next, a resist mask 143a is formed over the sacrificial film 144(2)R (FIG. 4B). Note that FIG. 4B illustrates an example in which the EL film 112Rf is not formed in the region 130. In the case where the region 130 is shielded in deposition of the EL film 112Rf, a metal mask can be used. Since the metal used here does not need to shield a pixel region of the display portion, a fine mask does not need to be used.

For the resist mask 143a, a resist material containing a photosensitive resin such as a positive resist material or a negative resist material can be used.

Here, in the case where the resist mask 143a is formed over the sacrificial film 144(2)R, if a defect such as a pinhole exists in the sacrificial film 144(2)R, the EL film 112Rf might be dissolved in a solvent of the resist material. With the use of an inorganic insulating material such as aluminum oxide, hafnium oxide, or silicon oxide formed by an ALD method for the sacrificial film 144(1)R, a film with few pinholes can be formed and generation of such a defect can be prevented.

[Etching of Sacrificial Film 144(1)R and Sacrificial Film 144(2)R]

Then, part of the sacrificial film 144(2)R and part of the sacrificial film 144(1)R that are not covered with the resist mask 143a are removed by etching, whereby the island-shaped or band-shaped sacrificial layer 145(1)R and sacrificial layer 145(2)R are formed. Here, the sacrificial layer 145(1)R and the sacrificial layer 145(2)R are formed over the pixel electrode 111R and over the connection electrode 111C.

The sacrificial film 144(1)R is preferably processed by etching using a hard mask. The hard mask is preferably formed by processing the sacrificial film 144(2)R.

First, while at least part of the sacrificial film 144(1)R is made to remain, part of the sacrificial film 144(2)R that is not covered with the resist mask 143a is removed by etching, whereby the sacrificial layer 145(2)R is formed. After that, the resist mask 143a is removed.

The etching of the sacrificial film 144(2)R preferably employs etching conditions with high selectivity with respect to the sacrificial film 144(1)R. Although a wet etching or a dry etching can be used for the etching for forming the hard mask, a shrinkage of the pattern can be inhibited by a dry etching method. For example, in the case where an inorganic insulating material such as aluminum oxide, hafnium oxide, or silicon oxide, which is formed by an ALD method, is used for the sacrificial film 144(1)R and a metal oxide containing indium such as indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), which is formed by a sputtering method, is used for the sacrificial film 144(2)R, the sacrificial film 144(2)R formed by a sputtering method is etched here to serve as a hard mask.

The removal of the resist mask 143a can be performed by wet etching or dry etching. It is particularly preferable to perform dry etching (also referred to as plasma ashing) using an oxygen gas as an etching gas to remove the resist mask 143a.

By etching of the sacrificial film 144(1)R using the sacrificial layer 145(2)R as a hard mask, the removal of the resist mask 143a can be performed in a state where the EL film 112Rf is covered with the sacrificial film 144(1)R. This is particularly suitable in the case where etching using an oxygen gas, such as plasma ashing, is performed because the electrical characteristics might be adversely affected when the EL film 112Rf is exposed to oxygen.

Next, the sacrificial film 144(1)R is removed by etching using the sacrificial layer 145(2)R as a hard mask, so that the island-shaped or band-shaped sacrificial layer 145(1)R is formed. Note that in the manufacturing method of the display device of one embodiment of the present invention, a structure may be employed where either the sacrificial layer 145(1)R and the sacrificial layer 145(2)R is not used.

[Etching of EL Film 112Rf]

Next, part of the EL film 112Rf that is not covered with the sacrificial layer 145(1)R is removed by etching, so that the island-shaped or band-shaped EL layer 112R is formed.

For the etching of the EL film 112Rf, it is preferable to use dry etching using an etching gas that does not contain oxygen as its main component. This can inhibit the alteration of the EL film 112Rf to achieve a highly reliable display device. Examples of the etching gas that does not contain oxygen as its main component include CF₄, C₄F₈, SF₆, CHF₃, Cl₂, H₂O, BCl₃, and a noble gas such as He. Alternatively, a mixed gas of the above gas and a dilution gas that does not contain oxygen can be used as the etching gas. Here, in the etching of the EL film 112Rf, part of the sacrificial layer 145(1)R may be removed. For example, in the case where the sacrificial film 144(1)R has a two-layer structure, an inorganic insulating material such as aluminum oxide, hafnium oxide, or silicon oxide formed by an ALD method is used for a lower layer, and a metal oxide containing indium such as indium gallium zinc oxide (also referred to as In—Ga—Zn oxide or IGZO) formed by a sputtering method is used for an upper layer, the upper layer may be etched in the etching of the EL film 112Rf.

Note that etching of the EL film 112Rf is not limited to the above and may be performed by dry etching using another gas or wet etching.

When dry etching using an oxygen gas or an etching gas containing an oxygen gas is employed for the etching of the EL film 112Rf, the etching rate can be increased. Consequently, etching under a low-power condition can be performed while the etching rate is kept adequately high; hence, damage due to the etching can be reduced. Furthermore, a defect such as attachment of a reaction product generated in the etching can be inhibited. For example, an etching gas obtained by adding an oxygen gas to the etching gas that does not contain oxygen as its main component can be used.

[Formation of EL Layer 112G and EL Layer 112B]

Next, the EL film 112Gf to be the EL layer 112G is formed over the sacrificial layer 145(1)R. For the EL film 112Gf, the description of the EL film 112Rf can be referred to.

Next, the sacrificial film 144(1)G is deposited over the EL film 112Gf. For the sacrificial film 144(1)G, the description of the sacrificial film 144(1)R can be referred to.

Subsequently, the sacrificial film 144(2)G is deposited over the sacrificial film 144(1)G. For the sacrificial film 144(2)G, the description of the sacrificial film 144(2)R can be referred to.

Next, a resist mask 143b is formed over the sacrificial film 144(2)G (FIG. 4C).

Subsequently, the sacrificial layer 145(1)G, the sacrificial layer 145(2)G, and the EL layer 112G are formed. For the formation of the sacrificial layer 145(1)G, the sacrificial layer 145(2)G, and the EL layer 112G, the formation of the sacrificial layer 145(1)R, the sacrificial layer 145(2)R, and the EL layer 112R can be referred to.

Next, the EL film 112Bf to be the EL layer 112B is deposited over the sacrificial layer 145(2)R and the sacrificial layer 145(2)G. For the EL film 112Bf, the description of the EL film 112Rf can be referred to.

Subsequently, the sacrificial film 144(1)B is deposited over the EL film 112Bf. For the sacrificial film 144(1)B, the description of the sacrificial film 144(1)R can be referred to.

Next, a sacrificial film 144(2)c is deposited over the sacrificial film 144(2). For the sacrificial film 144(2)B, the description of the sacrificial film 144(2)R can be referred to.

Subsequently, a resist mask 143c is formed over the sacrificial film 144(2)B (FIG. 4D).

Next, the sacrificial layer 145(1)B, the sacrificial layer 145(2)B, and the EL layer 112B are formed (FIG. 4E). For the formation of the sacrificial layer 145(1)B, the sacrificial layer 145(2)B, and the EL layer 112B, the formation of the sacrificial layer 145(1)R, the sacrificial layer 145(2)R, and the EL layer 112R can be referred to.

FIG. 4F illustrates an enlarged view of a region surrounded by the dashed-dotted square in FIG. 4E.

In this specification and the like, the thicknesses of a layer and a film are sometimes drawn to be larger for easy viewing in a drawing that is not enlarged. In an enlarged drawing, the distance between components included in a display device or the like may be differ. For example, the distance between the end portions of the pixel electrode 111 and the end portions of the EL layer 112 is drawn to be wide in FIG. 4F. In addition, the interval between components of the light-emitting element 110B and components of the light-emitting element 110R is widely drawn.

Next, the sacrificial layer 145(2)R, the sacrificial layer 145(2)G, and the sacrificial layer 145(2)B (hereinafter collectively referred to as “sacrificial layer 145(2)”) are removed by etching or the like (FIG. 5A). For the etching of the sacrificial layer 145(2), the condition that can provide a high selectivity of the sacrificial layer 145(2) with respect to the sacrificial layer 145(1)R, the sacrificial layer 145(1)G, and the sacrificial layer 145(1)B (hereinafter collectively referred to as “sacrificial layer 145(1)”) is preferably employed. Note that the removal of the sacrificial layer 145(2) is not necessarily performed.

[Formation of Insulating Layer 131]

Next, an insulating film 131bf to be the insulating layer 131b is formed (FIG. 5B). A film containing an inorganic material is preferably used as the insulating film 131bf. For example, a single layer or stacked layers of a film containing aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, or the like can be used.

For the formation of the insulating film 131bf, a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like can be used. An ALD method achieving favorable coverage can be suitably used for formation of the insulating film 131bf.

As the insulating film 131bf, a single layer or stacked layers of aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, or the like can be used. In particular, aluminum oxide is preferable because it has high selectivity with respect to the EL layer 112 in etching and has a function of protecting the EL layer 112 in forming the insulating layer 131b which is to be described later.

The insulating film 131bf formed by an ALD method can be a film with few pinholes, and the insulating layer 131b can have an excellent function of protecting the EL layer 112.

The formation temperature of the insulating film 131bf is preferably lower than the upper temperature limit of the EL layer 112.

Here, aluminum oxide is formed by an ALD method as the insulating film 131bf. The formation temperature of the insulating film 131bf by an ALD method is preferably higher than or equal to 60° C. and lower than or equal to 150° C., further preferably higher than or equal to 70° C. and lower than or equal to 115° C., still further preferably higher than or equal to 80° C. and lower than or equal to 100° C. By forming the insulating film 131bf at such a temperature, a dense insulating film can be obtained and damage to the EL layer 112 can be reduced.

Next, an insulating film 131af to be the insulating layer 131a is formed (FIG. 5C). The insulating film 131af is provided so as to fill the depressed portion of the insulating film 131bf. The insulating film 131af is provided so as to cover the sacrificial layer 145(1), the EL layer 112, and the pixel electrode 111. The insulating film 131af is preferably a planarization film.

As the insulating film 131af, an insulating film containing an organic material is preferably used, and a resin is preferably used as the organic material.

As a material that can be used for the insulating film 131af, an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a polyimide-amide resin, a siloxane resin, a benzocyclobutene-based resin, a phenol resin, and precursors of these resins can be given, for example. A photosensitive resin can be used for the insulating film 131af. As the photosensitive resin, a positive material or a negative material can be used.

By forming the insulating film 131af using a photosensitive resin, the insulating film 131af can be formed only by light exposure and development steps; thus, damage to layers included in the light-emitting elements 110, in particular, damage to EL layers, can be reduced.

As illustrated in FIG. 5C, the insulating film 131af may have a slight unevenness reflecting unevenness of the formation surface. Alternatively, as illustrated in FIG. 5D, the insulating film 131af is less influenced by the unevenness of the formation surface and has higher planarity in some cases than in FIG. 5C.

Next, the insulating layer 131a is formed. Here, when a photosensitive resin is used for the insulating film 131af, the insulating layer 131a can be formed without providing an etching mask such as a resist mask or a hard mask. Since a photosensitive resin can be processed only by light exposure and development steps, the insulating layer 131a can be formed without using a dry etching method or the like. Thus, the process can be simplified. In addition, damage to the EL layer due to etching of the insulating film 131af can be reduced. Furthermore, an upper portion of the insulating layer 131a may be partly etched to adjust the level of the surface.

The insulating layer 131a may alternatively be formed by performing etching substantially uniformly on the top surface of the insulating film 131af. Such uniform etching for planarization is also referred to as etch back.

To form the insulating layer 131a, the light exposure and development steps and the etch back step may be used in combination.

An example of a method for forming the insulating layer 131a is described with reference to FIG. 6A to FIG. 6C. FIG. 6A illustrates an example in which a photosensitive resin is used for the insulating film 131af, processing of the insulating film 131af is performed using the light exposure and development steps to form an insulating layer 131ap. FIG. 6B is an enlarged view of a region surrounded by the dashed-dotted square in FIG. 6A. The insulating layer 131ap illustrated in FIG. 6B is further subjected to etching, whereby the insulating layer 131a illustrated in FIG. 6C can be formed.

Note that the insulating layer 131ap illustrated in FIG. 6B can be used as the insulating layer 131a, and in such a case, the light-emitting elements 110 include a structure in which the sacrificial layer 145(1) remains between the insulating layer 131a and the EL layer 112 in some cases.

Next, etching of the insulating film 131bf and the sacrificial layer 145(1) is performed (FIG. 7A). At this time, a method that causes damage to the EL layer 112R, the EL layer 112G, and the EL layer 112B as little as possible is preferably employed. Thus, the insulating layer 131b covering the side surfaces of the EL layer 112R, the EL layer 112G, and the EL layer 112B is formed. FIG. 7B is an enlarged view of a region surrounded by the dashed-dotted square in FIG. 7A.

The insulating film 131bf and the sacrificial layer 145(1) are formed using the same material, whereby etching can be performed at the same time, so that the step can be simplified in some cases.

A dry etching method or a wet etching method can be used for the etching of the insulating film 131bf. The etching may be performed by ashing using oxygen plasma or the like. Chemical mechanical polishing (CMP) may be used for the etching of the insulating film 131bf.

Note that at the time of etching the insulating film 131bf, damage to the EL layer 112 due to the etching is preferably reduced. Thus, the insulating film 131bf is preferably formed using a material having high etching selectivity with respect to the EL layer 112.

The use of an inorganic material for the insulating film 131bf can increase the selectivity with respect to the EL layer 112 in some cases. As the insulating layer 131b, a single layer or stacked layers of aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, or the like can be used, for example. In particular, aluminum oxide is preferable because it has high selectivity with respect to the EL layer 112 in etching and has a function of protecting the EL layer 112 in forming the insulating layer 131b which is to be described later. In particular, with the use of an inorganic material such as aluminum oxide, hafnium oxide, or silicon oxide formed by an ALD method for the insulating layer 131b, the insulating layer 131b can be a film with few pinholes and can have an excellent function of protecting the EL layer 112.

In formation of the insulating film 131af and the insulating film 131bf, the top surface levels can be adjusted by the etching amounts. Here, the etching amount is preferably adjusted such that the insulating layer 131b covers the side surface of the EL layer 112. In particular, the etching amount is preferably adjusted such that the insulating layer 131b covers a side surface of the light-emitting layer included in the EL layer 112.

The surface planarity of the insulating film 131af containing an organic material may change due to unevenness of the formation surface and the sparseness and density of the pattern formed on the formation surface. The planarity of the insulating film 131af may change due to the viscosity or the like of a material used for the insulating film 131af. For example, in some cases, the thickness of the insulating film 131af in a region not overlapping with the EL layer 112 becomes smaller than the thickness of the insulating film 131af in a region overlapping with the EL layer 112. In such a case, for example, etch back of the insulating film 131af is performed, whereby the level of the top surface of the insulating layer 131 becomes lower than the level of the top surface of the sacrificial layer 145(1) in some cases.

The insulating film 131af has a concave curved surface shape (a hollow shape), a convex curved surface shape (a bulging shape), or the like in a region between the plurality of EL layers 112 in some cases.

[Formation of Common Layer 114]

Next, the common layer 114 is formed. In the case of a structure not including the common layer 114, the common electrode 113 is formed to cover the EL layer 112R, the EL layer 112G, and the EL layer 112B.

[Formation of Common Electrode 113]

Subsequently, the common electrode 113 is formed over the common layer 114. The common electrode 113 can be formed by a sputtering method or an evaporation method, for example. Note that in the case where the common layer 114 is not provided over the connection electrode 111C, a metal mask that shields the upper portion of the connection electrode 111C may be used in depositing the common layer 114. The metal mask used here does not need to shield a pixel region of the display portion; hence, a fine mask does not need to be used.

Through the above steps, the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B can be manufactured.

[Formation of Protective Layer 121]

Next, the protective layer 121 is formed over the common electrode 113 (FIG. 7C). An inorganic insulating film used for the protective layer 121 is preferably deposited by a sputtering method, a PECVD method, or an ALD method. In particular, an ALD method is preferable because it provides excellent step coverage and is less likely to cause a defect such as a pinhole. In addition, an organic insulating film is preferably deposited by an inkjet method because a uniform film can be formed in a desired area.

Through the above steps, the display device 100 illustrated in FIG. 1A can be manufactured.

Modification Examples of Structure Example 1

FIG. 8A and FIG. 8B illustrate a modification example of a structure of the display device 100 illustrated in FIG. 1.

The display device 100 illustrated in FIG. 8A is different from that in FIG. 1B in the shapes of the insulating layer 131a, the insulating layer 131b, and the like. FIG. 8B illustrates an enlarged view of a region surrounded by the dashed-dotted square in FIG. 8A.

In FIG. 8A and FIG. 8B, the display device 100 includes the sacrificial layer 145(1) between the insulating layer 131b and the pixel electrode 111. Such a structure can be obtained by processing the insulating layer 131ap so that a region covering the sacrificial layer 145(1) remains in the structure illustrated in FIG. 5B.

FIG. 9A and FIG. 9B are different from that in FIG. 8B in the shapes of the insulating layer 131a, the insulating layer 131b, and the like

The structure illustrated in FIG. 9A can be obtained by using the insulating layer 131ap illustrated in FIG. 5B as the insulating layer 131a.

The structure in FIG. 9B illustrates an example in which the end portions of the EL layer 112 do not have a step. With the structure illustrated in FIG. 9B, the distance between the EL layers 112 included in different light-emitting elements 110 can be reduced and the aperture ratio of the light-emitting elements 110 can be increased in some cases.

At least part of this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 2

In this embodiment, structure examples of a display device of one embodiment of the present invention are described.

The display device in this embodiment can be a high-definition display device or a large-sized display device. Accordingly, the display device in this embodiment can be used for display portions of electronic devices such as a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a smartphone, a watch-type terminal, a tablet terminal, a portable information terminal, and an audio reproducing device, in addition to display portions of electronic devices with a relatively large screen, such as a television device, a desktop or laptop personal computer, a monitor of a computer or the like, digital signage, and a large game machine such as a pachinko machine.

[Structure Example of Display Device]

FIG. 10 is a perspective view of a display device 400A, and FIG. 11A is a cross-sectional view of the display device 400A.

The display device 400A has a structure where a substrate 452 and a substrate 451 are bonded to each other. In FIG. 10, the substrate 452 is denoted by a dashed line.

The display device 400A includes a display portion 462, a circuit 464, a wiring 465, and the like. FIG. 10 illustrates an example where an IC 473 and an FPC 472 are mounted on the display device 400A. Thus, the structure illustrated in FIG. 10 can be regarded as a display module including the display device 400A, the IC (integrated circuit), and the FPC.

As the circuit 464, a scan line driver circuit can be used, for example.

The wiring 465 has a function of supplying a signal and electric power to the display portion 462 and the circuit 464. The signal and electric power are input to the wiring 465 from the outside through the FPC 472 or from the IC 473.

FIG. 10 illustrates an example where the IC 473 is provided over the substrate 451 by a COG (Chip On Glass) method, a COF (Chip on Film) method, or the like. An IC including a scan line driver circuit, a signal line driver circuit, or the like can be used as the IC 473, for example. Note that the display device 400A and the display module are not necessarily provided with an IC. The IC may be mounted on the FPC by a COF method or the like.

FIG. 11A illustrates an example of cross sections of part of a region including the FPC 472, part of the circuit 464, part of the display portion 462, and part of a region including an end portion of the display device 400A.

The display device 400A illustrated in FIG. 11A includes a transistor 201, a transistor 205, a light-emitting element 430a that emits red light, a light-emitting element 430b that emits green light, a light-emitting element 430c that emits blue light, and the like between the substrate 451 and the substrate 452.

The light-emitting element described in Embodiment 1 can be used as the light-emitting element 430a, the light-emitting element 430b, and the light-emitting element 430c.

In the case where a pixel of the display device includes three kinds of subpixels including light-emitting elements emitting different colors from each other, as the three subpixels, subpixels of three colors of R, G, and B, subpixels of three colors of yellow (Y), cyan (C), and magenta (M), and the like can be given. In the case where four subpixels are included, as the four subpixels, subpixels of four colors of R, G, B, and white (W), subpixels of four colors of R, G, B, and Y, and the like can be given.

A protective layer 410 and the substrate 452 are bonded to each other with an adhesive layer 442. A solid sealing structure, a hollow sealing structure, or the like can be employed to seal the light-emitting elements. In FIG. 11A, a hollow sealing structure is employed where a space 443 surrounded by the substrate 452, the adhesive layer 442, and the substrate 451 is filled with an inert gas (e.g., nitrogen or argon). The adhesive layer 442 may be provided to overlap with the light-emitting element. The space 443 surrounded by the substrate 452, the adhesive layer 442, and the substrate 451 may be filled with a resin different from that of the adhesive layer 442.

In an opening portion provided in an insulating layer 214 so as to expose the top surface of a conductive layer 222b included in the transistor 205, parts of a conductive layer 418a, a conductive layer 418b, and a conductive layer 418c are formed along the bottom surface and side surface of the opening portion. The conductive layer 418a, the conductive layer 418b, and the conductive layer 418c are each connected to the conductive layer 222b included in the transistor 205 through the opening provided in the insulating layer 214. The pixel electrodes each contain a material reflecting visible light, and a counter electrode contains a material transmitting visible light. In addition, other parts of the conductive layer 418a, the conductive layer 418b, and the conductive layer 418c are provided over the insulating layer 214.

A pixel electrode 411a, a pixel electrode 411b, and a pixel electrode 411c are provided over the conductive layer 418a, the conductive layer 418b, and the conductive layer 418c, respectively.

As illustrated in FIG. 11, over the pixel electrode 411a, the pixel electrode 411b, and the pixel electrode 411c, an insulating layer 414 may be provided between an EL layer 416a included in the light-emitting element 430a, an EL layer 416b included in the light-emitting element 430b, and an EL layer 416c included in the light-emitting element 430c.

The pixel electrode 111 described in the above embodiment can be used as each of the pixel electrode 411a, the pixel electrode 411b, and the pixel electrode 411c.

An insulating layer 421 is provided in each of a region that is between the light-emitting element 430a and the light-emitting element 430b and over the insulating layer 214, and a region that is between the light-emitting element 430b and the light-emitting element 430c and over the insulating layer 214. For the insulating layer 421, the insulating layer 131 described in the above embodiment can be referred to.

Light from the light-emitting element is emitted toward the substrate 452 side. For the substrate 452, a material having a high property of transmitting visible light is preferably used.

The transistor 201 and the transistor 205 are formed over the substrate 451. These transistors can be fabricated using the same material in the same step.

An insulating layer 211, an insulating layer 213, an insulating layer 215, and the insulating layer 214 are provided in this order over the substrate 451. Part of the insulating layer 211 functions as a gate insulating layer of each transistor. Part of the insulating layer 213 functions as a gate insulating layer of each transistor. The insulating layer 215 is provided to cover the transistors. The insulating layer 214 is provided to cover the transistors and has a function of a planarization layer. Note that there is no limitation on the number of gate insulating layers and the number of insulating layers covering the transistors, and each insulating layer may be either a single layer or two or more layers.

A material through which impurities such as water and hydrogen do not easily diffuse is preferably used for at least one of the insulating layers covering the transistors. This allows the insulating layer to serve as a barrier layer. Such a structure can effectively inhibit diffusion of impurities into the transistors from the outside and increase the reliability of the display device.

An inorganic insulating film is preferably used as each of the insulating layer 211, the insulating layer 213, and the insulating layer 215. As the inorganic insulating film, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum nitride film can be used, for example. A hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, a neodymium oxide film, or the like may be used. A stack including two or more of the above insulating films may also be used.

Here, an organic insulating film often has a lower barrier property than an inorganic insulating film. Therefore, the organic insulating film preferably has an opening in the vicinity of the end portion of the display device 400A. This can inhibit entry of impurities from the end portion of the display device 400A through the organic insulating film. Alternatively, the organic insulating film may be formed such that its end portion is positioned on the inner side of the end portion of the display device 400A, to prevent the organic insulating film from being exposed at the end portion of the display device 400A.

An organic insulating film is suitable for the insulating layer 214 functioning as a planarization layer. Examples of a material that can be used for the organic insulating film include an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a polyimide-amide resin, a siloxane resin, a benzocyclobutene-based resin, a phenol resin, and precursors of these resins.

In a region 228 illustrated in FIG. 11A, an opening is formed in a two-layer stacked structure of the insulating layer 214 and the insulating layer 421b over the insulating layer 214. The insulating layer 421b can be formed using the same material as the insulating layer 421. In addition, the insulating layer 421b is formed using the same steps as the insulating layer 421, for example. The protective layer 410 is formed to cover the opening. The use of an inorganic layer as the protective layer 410 can inhibit entry of impurities into the display portion 462 from the outside through the insulating layer 214 even when an organic insulating film is used for the insulating layer 214. Consequently, the reliability of the display device 400A can be increased.

Each of the transistor 201 and the transistor 205 includes a conductive layer 221 functioning as a gate, the insulating layer 211 functioning as a gate insulating layer, a conductive layer 222a functioning as one of a source and a drain, the conductive layer 222b functioning as other of the source and the drain, a semiconductor layer 231, the insulating layer 213 functioning as a gate insulating layer, and a conductive layer 223 functioning as a gate. Here, a plurality of layers obtained by processing the same conductive film are illustrated with the same hatching pattern. The insulating layer 211 is positioned between the conductive layer 221 and the semiconductor layer 231. The insulating layer 213 is positioned between the conductive layer 223 and the semiconductor layer 231.

There is no particular limitation on the structures of the transistors included in the display device of this embodiment. For example, a planar transistor, a staggered transistor, or an inverted staggered transistor can be used. Either of a top-gate transistor structure and a bottom-gate transistor structure can be used. Alternatively, gates may be provided above and below a semiconductor layer where a channel is formed.

The structure where the semiconductor layer where a channel is formed is provided between two gates is used for the transistor 201 and the transistor 205. The two gates may be connected to each other and supplied with the same signal to drive the transistor. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other of the two gates.

There is no particular limitation on the crystallinity of a semiconductor material used for the transistor, and an amorphous semiconductor or a semiconductor having crystallinity (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor partly including crystal regions) may be used. A semiconductor having crystallinity is preferably used because degradation of the transistor characteristics can be inhibited.

A semiconductor layer of a transistor preferably includes a metal oxide (also referred to as an oxide semiconductor). That is, a transistor including a metal oxide in its channel formation region (hereinafter, also referred to as an OS transistor) is preferably used for the display device of this embodiment. Alternatively, a semiconductor layer of a transistor may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon (e.g., low-temperature polysilicon or single crystal silicon).

The semiconductor layer preferably contains indium, M (M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc, for example. Specifically, M is preferably one or more selected from aluminum, gallium, yttrium, and tin.

It is particularly preferable that an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) be used as the semiconductor layer.

When the semiconductor layer is an In-M-Zn oxide, the atomic proportion of In is preferably greater than or equal to the atomic proportion of M in the In-M-Zn oxide. Examples of the atomic ratio of the metal elements in such an In-M-Zn oxide include In:M:Zn=1:1:1 or a composition in the neighborhood thereof, In:M:Zn=1:1:1.2 or a composition in the neighborhood thereof, In:M:Zn=2:1:3 or a composition in the neighborhood thereof, In:M:Zn=3:1:2 or a composition in the neighborhood thereof, In:M:Zn=4:2:3 or a composition in the neighborhood thereof, In:M:Zn=4:2:4.1 or a composition in the neighborhood thereof, In:M:Zn=5:1:3 or a composition in the neighborhood thereof, In:M:Zn=5:1:6 or a composition in the neighborhood thereof, In:M:Zn=5:1:7 or a composition in the neighborhood thereof, In:M:Zn=5:1:8 or a composition in the neighborhood thereof, In:M:Zn=6:1:6 or a composition in the neighborhood thereof, and In:M:Zn=5:2:5 or a composition in the neighborhood thereof. Note that a composition in the neighborhood includes the range of +30% of an intended atomic ratio.

For example, in the case of describing an atomic ratio of In:Ga:Zn=4:2:3 or a composition in the neighborhood thereof, the case is included where with the atomic ratio of In being 4, the atomic ratio of Ga is greater than or equal to 1 and less than or equal to 3 and the atomic ratio of Zn is greater than or equal to 2 and less than or equal to 4. In the case of describing an atomic ratio of In:Ga:Zn=5:1:6 or a composition in the neighborhood thereof, the case is included where with the atomic ratio of In being 5, the atomic ratio of Ga is greater than 0.1 and less than or equal to 2 and the atomic ratio of Zn is greater than or equal to 5 and less than or equal to 7. In the case of describing an atomic ratio of In:Ga:Zn=1:1:1 or a composition in the neighborhood thereof, the case is included where with the atomic ratio of In being 1, the atomic ratio of Ga is greater than 0.1 and less than or equal to 2 and the atomic ratio of Zn is greater than 0.1 and less than or equal to 2.

The transistor included in the circuit 464 and the transistor included in the display portion 462 may have the same structure or different structures. A plurality of transistors included in the circuit 464 may have the same structure or two or more kinds of structures. Similarly, a plurality of transistors included in the display portion 462 may have the same structure or two or more kinds of structures.

A connection portion 204 is provided in a region of the substrate 451 not overlapping with the substrate 452. In the connection portion 204, the wiring 465 is electrically connected to the FPC 472 through a conductive layer 466 and a connection layer 242. For the conductive layer 466, a conductive film obtained by processing the same conductive film as the pixel electrode or a conductive film obtained by processing a stacked-layer film of the same conductive film as the pixel electrode and the same conductive film as the optical adjustment layer can be used. On the top surface of the connection portion 204, the conductive layer 466 is exposed. Thus, the connection portion 204 and the FPC 472 can be electrically connected to each other through the connection layer 242.

A light-blocking layer 417 is preferably provided on the surface of the substrate 452 on the substrate 451 side. A variety of optical members can be arranged on the outer side of the substrate 452. Examples of the optical members include a polarizing plate, a retardation plate, a light diffusion layer (e.g., a diffusion film), an anti-reflective layer, and a light-condensing film. Furthermore, an antistatic film inhibiting the attachment of dust, a water repellent film inhibiting the attachment of stain, a hard coat film inhibiting generation of a scratch caused by the use, an impact-absorbing layer, or the like may be provided on the outer side of the substrate 452.

Providing the protective layer 410 covering the light-emitting elements inhibits entry of impurities such as water into the light-emitting elements, thereby increasing the reliability of the light-emitting elements.

In the region 228 in the vicinity of the end portion of the display device 400A, the insulating layer 215 and the protective layer 410 are preferably in contact with each other through an opening in the insulating layer 214. In particular, the inorganic insulating film included in the insulating layer 215 and the inorganic insulating film included in the protective layer 410 are preferably in contact with each other. This can inhibit entry of impurities into the display portion 462 from the outside through the organic insulating film. Consequently, the reliability of the display device 400A can be increased.

For each of the substrate 451 and the substrate 452, glass, quartz, ceramics, sapphire, a resin, a metal, an alloy, a semiconductor, or the like can be used. The substrate on the side where light from the light-emitting element is extracted is formed using a material that transmits the light. When the substrate 451 and the substrate 452 are formed using a flexible material, the flexibility of the display device can be increased. Furthermore, a polarizing plate may be used as the substrate 451 or the substrate 452.

For each of the substrate 451 and the substrate 452, it is possible to use a polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), a polyacrylonitrile resin, an acrylic resin, a polyimide resin, a polymethyl methacrylate resin, a polycarbonate (PC) resin, a polyethersulfone (PES) resin, a polyamide resin (e.g., nylon or aramid), a polysiloxane resin, a cycloolefin resin, a polystyrene resin, a polyamide-imide resin, a polyurethane resin, a polyvinyl chloride resin, a polyvinylidene chloride resin, a polypropylene resin, a polytetrafluoroethylene (PTFE) resin, an ABS resin, cellulose nanofiber, or the like. Glass that is thin enough to have flexibility may be used for one or both of the substrate 451 and the substrate 452.

In the case where a circularly polarizing plate overlaps with the display device, a highly optically isotropic substrate is preferably used as the substrate included in the display device. A highly optically isotropic substrate has a low birefringence (in other words, a small amount of birefringence).

The absolute value of a retardation (phase difference) of a highly optically isotropic substrate is preferably less than or equal to 30 nm, further preferably less than or equal to 20 nm, still further preferably less than or equal to 10 nm.

Examples of the film having high optical isotropy include a triacetyl cellulose (TAC, also referred to as cellulose triacetate) film, a cycloolefin polymer (COP) film, a cycloolefin copolymer (COC) film, and an acrylic film.

In the case where a film is used for the substrate and the film absorbs water, the shape of the display panel might be changed, e.g., creases are generated. Thus, for the substrate, a film with a low water absorption rate is preferably used. For example, a film with a water absorption rate lower than or equal to 1% is preferably used, a film with a water absorption rate lower than or equal to 0.1% is further preferably used, and a film with a water absorption rate lower than or equal to 0.01% is still further preferably used.

As the adhesive layer, any of a variety of curable adhesives such as a reactive curable adhesive, a thermosetting curable adhesive, an anaerobic adhesive, and a photocurable adhesive such as an ultraviolet curable adhesive can be used. Examples of these adhesives include an epoxy resin, an acrylic resin, a silicone resin, a phenol resin, a polyimide resin, an imide resin, a PVC (polyvinyl chloride) resin, a PVB (polyvinyl butyral) resin, and an EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as an epoxy resin, is preferable. Alternatively, a two-liquid-mixture-type resin may be used. An adhesive sheet or the like may be used.

As the connection layer 242, an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like can be used.

As materials for the gate, the source, and the drain of a transistor and conductive layers such as a variety of wirings and electrodes included in the display device, any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, or an alloy containing any of these metals as its main component can be used, for example. A single-layer structure or a stacked-layer structure including a film containing any of these materials can be used.

As a light-transmitting conductive material, a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, or zinc oxide containing gallium, or graphene can be used. It is also possible to use a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium; or an alloy material containing any of these metal materials. Alternatively, a nitride of the metal material (e.g., titanium nitride) or the like may be used. Note that in the case of using the metal material or the alloy material (or the nitride thereof), the thickness is preferably set small enough to transmit light. Furthermore, a stacked-layer film of the above materials can be used for a conductive layer. For example, a stacked-layer film of indium tin oxide and an alloy of silver and magnesium is preferably used because conductivity can be increased. They can also be used for conductive layers such as a variety of wirings and electrodes included in the display device, and conductive layers (e.g., conductive layers functioning as the pixel electrode and the common electrode) included in the light-emitting element.

Examples of insulating materials that can be used for the insulating layers include a resin such as an acrylic resin or an epoxy resin, and an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or aluminum oxide.

The transistor 201 and the transistor 205 each include the conductive layer 221 functioning as a gate, the insulating layer 211 functioning as a gate insulating layer, a semiconductor layer including a channel formation region 231i and a pair of low-resistance regions 231n, the conductive layer 222a connected to one of the pair of low-resistance regions 231n, the conductive layer 222b connected to the other of the pair of low-resistance regions 231n, an insulating layer 225 functioning as a gate insulating layer, the conductive layer 223 functioning as a gate, and the insulating layer 215 covering the conductive layer 223. The insulating layer 211 is positioned between the conductive layer 221 and the channel formation region 231i. The insulating layer 225 is positioned between the conductive layer 223 and the channel formation region 231i.

The conductive layer 222a and the conductive layer 222b are connected to the low-resistance regions 231n through openings provided in the insulating layer 215 and the insulating layer 225. One of the conductive layer 222a and the conductive layer 222b functions as a source, and the other functions as a drain.

FIG. 11B illustrates an example where the insulating layer 225 covers the top surface and the side surface of the semiconductor layer. The conductive layer 222a and the conductive layer 222b are connected to the low-resistance regions 231n through openings provided in the insulating layer 225 and the insulating layer 215.

Meanwhile, in a transistor 209 illustrated in FIG. 11C, the insulating layer 225 overlaps with the channel formation region 231i of the semiconductor layer 231 and does not overlap with the low-resistance regions 231n. The structure illustrated in FIG. 11C can be fabricated by processing the insulating layer 225 using the conductive layer 223 as a mask, for example. In FIG. 11C, the insulating layer 215 is provided to cover the insulating layer 225 and the conductive layer 223, and the conductive layer 222a and the conductive layer 222b are connected to the low-resistance regions 231n through the openings in the insulating layer 215. Furthermore, an insulating layer 218 covering the transistor may be provided.

Transistors containing silicon in their semiconductor layers where channels are formed may be used as all transistors included in the pixel circuit for driving the light-emitting element. As silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, and the like can be given. In particular, a transistor containing low-temperature polysilicon (LTPS) in its semiconductor layer (hereinafter also referred to as an LTPS transistor) can be used. The LTPS transistor has high field-effect mobility and favorable frequency characteristics.

With the use of transistors containing silicon, such as LTPS transistors, a circuit required to be driven at a high frequency (e.g., a source driver circuit) can be formed on the same substrate as the display portion. Thus, external circuits mounted on the display device can be simplified, whereby parts costs and mounting costs can be reduced.

It is preferable to use transistors including a metal oxide (hereinafter also referred to as an oxide semiconductor) in their semiconductor layers where channels are formed (such transistors are hereinafter also referred to as OS transistors) as at least one of the transistors included in the pixel circuit. An OS transistor has extremely higher field-effect mobility than amorphous silicon. In addition, the OS transistor has an extremely low leakage current between a source and a drain in an off state (hereinafter, also referred to as off-state current), and charge accumulated in a capacitor that is connected in series to the transistor can be retained for a long period. Furthermore, power consumption of the display device can be reduced with the use of an OS transistor.

When an LTPS transistor is used as one or more of the transistors included in the pixel circuit and an OS transistor is used as the rest, a display device with low power consumption and high driving capability can be achieved. Note that a structure where an LTPS transistor and an OS transistor are used in combination is referred to as LTPO in some cases. Note that as a more preferable example, it is preferable to use an OS transistor as, for example, a transistor functioning as a switch for controlling electrical continuity between wirings and an LTPS transistor as, for example, a transistor for controlling current.

For example, one of the transistors included in the pixel circuit functions as a transistor for controlling current flowing through the light-emitting element and can be referred to as a driving transistor. One of a source and a drain of the driving transistor is electrically connected to the pixel electrode of the light-emitting element. An LTPS transistor is preferably used as the driving transistor. In this case, the amount of current flowing through the light-emitting element can be increased in the pixel circuit.

Another transistor included in the pixel circuit functions as a switch for controlling selection and non-selection of the pixel and can be referred to as a selection transistor. A gate of the selection transistor is electrically connected to a gate line, and one of a source and a drain thereof is electrically connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. Accordingly, the gray level of the pixel can be maintained even with an extremely low frame frequency (e.g., 1 fps or less); thus, power consumption can be reduced by stopping the driver in displaying a still image.

As described above, the display device of one embodiment of the present invention can have all of a high aperture ratio, a high resolution, high display quality, and low power consumption.

When a transistor using an oxide semiconductor in a channel formation region (hereinafter referred to as an OS transistor) is used as a transistor included in the pixel circuit, electric charge written to each node can be held for a long period. When a still image for which rewriting every frame is not required is displayed at high frequency, the frame frequency is lowered, a signal corresponding to image data is written to the pixel circuit, and then the operation of a peripheral driver circuit can be stopped. A driving method in which the operation of a peripheral driver circuit is stopped in such a manner while a still image is displayed is also referred to as “idling stop driving.” The idling stop driving results in lower power consumption of the display device.

The refresh rate of the display device of one embodiment of the present invention can be variable. For example, the refresh rate is adjusted (adjusted in the range from 0.01 Hz to 240 Hz, for example) in accordance with contents displayed on the display device, whereby power consumption can be reduced. Moreover, driving with a lowered refresh rate that reduces the power consumption of the display device may be referred to as idling stop (IDS) driving.

The driving frequency of a touch sensor or a near touch sensor may be changed in accordance with the refresh rate described above. In the case where the refresh rate of the display device is 120 Hz, for example, the driving frequency of the touch sensor or the near touch sensor can be higher than 120 Hz (typically 240 Hz). With this structure, low power consumption can be achieved, and the response speed of the touch sensor or the near touch sensor can be increased.

To increase the emission luminance of the light-emitting element included in the pixel circuit, the amount of current fed through the light-emitting element needs to be increased. For this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and the drain than a Si transistor, a high voltage can be applied between the source and the drain of the OS transistor. Accordingly, when an OS transistor is used as the driving transistor in the pixel circuit, the amount of current flowing through the light-emitting element can be increased, so that the emission luminance of the light-emitting element can be increased.

When transistors operate in a saturation region, a change in source-drain current with respect to a change in gate-source voltage can be smaller in an OS transistor than in a Si transistor. Accordingly, when an OS transistor is used as the driving transistor in the pixel circuit, the amount of current flowing between the source and the drain can be set minutely by a change in gate-source voltage; hence, the amount of current flowing through the light-emitting element can be controlled. Accordingly, the number of gray levels in the pixel circuit can be increased.

Regarding saturation characteristics of current flowing when the transistor operates in a saturation region, the OS transistor can make current (saturation current) flow more stably than the Si transistor even when the source drain voltage gradually increases. Thus, by using an OS transistor as the driving transistor, a stable current can be fed through a light-emitting element that contains an EL material even when the current-voltage characteristics of the light-emitting element vary, for example. In other words, when the OS transistor operates in the saturation region, the source-drain current hardly changes with an increase in the source-drain voltage; hence, the emission luminance of the light-emitting element can be stable.

As described above, with use of an OS transistor as a driving transistor included in the pixel circuit, it is possible to achieve “inhibition of black floating,” “increase in emission luminance,” “increase in gray level,” “inhibition of variation in light-emitting elements,” and the like.

An OS transistor has extremely higher field-effect mobility than amorphous silicon. In addition, the OS transistor has an extremely low leakage current between a source and a drain in an off state (hereinafter, also referred to as off-state current), and charge accumulated in a capacitor that is connected in series to the transistor can be retained for a long period. Furthermore, power consumption of the display device can be reduced with the use of an OS transistor.

The off-state current value per micrometer of channel width of the OS transistor at room temperature can be lower than or equal to 1 aA (1×10⁻¹⁸A), lower than or equal to 1 zA (1×10⁻²¹A), or lower than or equal to 1 yA (1×10⁻²⁴A). Note that the off-state current per micrometer of channel width of a transistor including silicon in a channel formation region (hereinafter, referred to as a Si transistor) at room temperature is higher than or equal to 1 fA (1×10⁻¹⁵A) and lower than or equal to 1 pA (1×10⁻¹²A). Therefore, the off-state current of an OS transistor is lower than that of a Si transistor by approximately ten orders of magnitude.

The off-state current of the OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even at an environment temperature higher than or equal to room temperature and lower than or equal to 200° C. Furthermore, the on-state current is unlikely to decrease even in the high-temperature environment. A display device including the OS transistor can operate stably and have high reliability even in a high-temperature environment.

At least part of the structure examples, the drawings corresponding thereto, and the like described in this embodiment as an example can be combined with the other structure examples, the other drawings, and the like as appropriate.

Embodiment 3

In this embodiment, a structure example of a display device different from those described above will be described.

The display device in this embodiment can be a high-resolution display device. Accordingly, the display device in this embodiment can be used for display portions of information terminals (wearable devices) such as watch-type and bracelet-type information terminals and display portions of wearable devices capable of being worn on the head, such as a VR device like a head-mounted display and a glasses-type AR device.

[Display Module]

FIG. 12A is a perspective view of a display module 280. The display module 280 includes a display device 400C and an FPC 290. Note that the display device included in the display module 280 is not limited to the display device 400C and may be a display device 400D, a display device 400E, or the display device 400F described later.

The display module 280 includes a substrate 291 and a substrate 292. The display module 280 includes a display portion 281. The display portion 281 is a region of the display module 280 where an image is displayed, and is a region where light from pixels provided in a pixel portion 284 described later can be seen.

FIG. 12B is a perspective view schematically illustrating a structure on the substrate 291 side. Over the substrate 291, a circuit portion 282, a pixel circuit portion 283 over the circuit portion 282, and the pixel portion 284 over the pixel circuit portion 283 are stacked. A terminal portion 285 to be connected to the FPC 290 is provided in a portion over the substrate 291 which does not overlap with the pixel portion 284. The terminal portion 285 and the circuit portion 282 are electrically connected to each other through a wiring portion 286 formed of a plurality of wirings.

The pixel portion 284 includes a plurality of pixels 284a arranged periodically. An enlarged view of one pixel 284a is illustrated on the right side of FIG. 12B. The pixel 284a includes the light-emitting elements 430a, 430b, and 430c that emit light of different colors. The plurality of light-emitting elements are preferably arranged in a stripe pattern as illustrated in FIG. 12B. With the stripe pattern that enables high-density arrangement of the light-emitting elements of one embodiment of the present invention or pixel circuits, a high-resolution display device can be provided. Alternatively, any of a variety of arrangement methods such as delta arrangement and PenTile arrangement can be employed.

The pixel circuit portion 283 includes a plurality of pixel circuits 283a arranged periodically.

One pixel circuit 283a is a circuit that controls light emission of three light-emitting elements included in one pixel 284a. One pixel circuit 283a may be provided with three circuits each of which controls light emission of one light-emitting element. For example, the pixel circuit 283a can include at least one selection transistor, one current control transistor (driving transistor), and a capacitor for one light-emitting element. In this case, a gate signal is input to a gate of the selection transistor and a source signal is input to one of a source and a drain thereof. With such a structure, an active-matrix display device is achieved.

The circuit portion 282 includes a circuit for driving the pixel circuits 283a in the pixel circuit portion 283. For example, one or both of a gate line driver circuit and a source line driver circuit are preferably included. The circuit portion 282 may also include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like.

The FPC 290 functions as a wiring for supplying a video signal, a power supply potential, or the like to the circuit portion 282 from the outside. An IC may be mounted on the FPC 290.

The display module 280 can have a structure where one or both of the pixel circuit portion 283 and the circuit portion 282 are stacked below the pixel portion 284; hence, the aperture ratio (effective display area ratio) of the display portion 281 can be significantly high. For example, the aperture ratio of the display portion 281 can be greater than or equal to 40% and less than 100%, preferably greater than or equal to 50% and less than or equal to 95%, further preferably greater than or equal to 60% and less than or equal to 95%. Furthermore, the pixels 284a can be arranged extremely densely and thus the display portion 281 can have an extremely high resolution. For example, the pixels 284a are preferably arranged in the display portion 281 with a resolution higher than or equal to 2000 ppi, preferably higher than or equal to 3000 ppi, further preferably higher than or equal to 5000 ppi, still further preferably higher than or equal to 6000 ppi, and lower than or equal to 20000 ppi or lower than or equal to 30000 ppi.

Such the display module 280 has an extremely high resolution, and thus can be suitably used for a VR device such as a head-mounted display or a glasses-type AR device. For example, even with a structure where the display portion of the display module 280 is seen through a lens, pixels of the extremely-high-resolution the display portion 281 included in the display module 280 are prevented from being perceived when the display portion is enlarged by the lens, so that display providing a high sense of immersion can be performed. Without being limited thereto, the display module 280 can be suitably used for electronic devices including a relatively small display portion. For example, the display module 280 can be favorably used in a display portion of a wearable electronic device, such as a watch.

[Structure Example of Display Device]

FIG. 13A illustrates a block diagram of a display device 10. The display device 10 includes a display portion 11, a driver circuit portion 12, a driver circuit portion 13, and the like.

The display portion 11 includes a plurality of pixels 30 arranged in a matrix. The pixels 30 each include a subpixel 21R, a subpixel 21G, and a subpixel 21B. The subpixel 21R, the subpixel 21G, and the subpixel 21B each include a light-emitting element functioning as a display element.

The pixel 30 is electrically connected to a wiring GL, a wiring SLR, a wiring SLG, and a wiring SLB. The wiring SLR, the wiring SLG, and the wiring SLB are electrically connected to the driver circuit portion 12. The wiring GL is electrically connected to the driver circuit portion 13. The driver circuit portion 12 functions as a source line driver circuit (also referred to as a source driver), and the driver circuit portion 13 functions as a gate line driver circuit (also referred to as a gate driver). The wiring GL functions as a gate line, and the wiring SLR, the wiring SLG, and the wiring SLB each function as a source line.

The subpixel 21R includes a light-emitting element emitting red light. The subpixel 21G includes a light-emitting element emitting green light. The subpixel 21B includes a light-emitting element emitting blue light. Thus, the display device 10 can perform full-color display. Note that the pixel 30 may include a subpixel including a light-emitting element emitting light of another color. For example, the pixel 30 may include, in addition to the three subpixels, a subpixel including a light-emitting element emitting white light, a subpixel including a light-emitting element emitting yellow light, or the like.

The wiring GL is electrically connected to the subpixel 21R, the subpixel 21G, and the subpixel 21B arranged in a row direction (an extending direction of the wiring GL). The wiring SLR, the wiring SLG, and the wiring SLB are electrically connected to the subpixels 21R, the subpixels 21G, and the subpixels 21B arranged in a column direction (an extending direction of the wiring SLR and the like), respectively.

FIG. 13B illustrates an example of a circuit diagram of a pixel 21 that can be used as the subpixel 21R, the subpixel 21G, and the subpixel 21B. The pixel 21 includes a transistor M1, a transistor M2, a transistor M3, a capacitor C1, and a light-emitting element EL. The wiring GL and a wiring SL are electrically connected to the pixel 21. The wiring SL corresponds to any of the wiring SLR, the wiring SLG, and the wiring SLB illustrated in FIG. 13A.

A gate of the transistor M1 is electrically connected to the wiring GL, one of a source and a drain of the transistor M1 is electrically connected to the wiring SL, and the other thereof is electrically connected to one electrode of the capacitor C1 and a gate of the transistor M2. One of a source and a drain of the transistor M2 is electrically connected to a wiring AL, and the other of the source and the drain of the transistor M2 is electrically connected to one electrode of the light-emitting element EL, the other electrode of the capacitor C1, and one of a source and a drain of the transistor M3. A gate of the transistor M3 is electrically connected to the wiring GL, and the other of the source and the drain of the transistor M3 is electrically connected to a wiring RL. The other electrode of the light-emitting element EL is electrically connected to a wiring CL.

The transistor M1 and the transistor M3 each function as a switch. For example, the transistor M2 functions as a transistor for controlling current flowing through the light-emitting element EL. For example, it can be said that the transistor M1 functions as a selection transistor and the transistor M2 functions as a driving transistor.

Here, it is preferable to use LTPS transistors as all of the transistor M1 to the transistor M3. Alternatively, it is preferable to use OS transistors as the transistor M1 and the transistor M3 and to use an LTPS transistor as the transistor M2.

Alternatively, OS transistors may be used as all of the transistor M1 to the transistor M3. In this case, an LTPS transistor can be used as at least one of a plurality of transistors included in the driver circuit portion 12 and a plurality of transistors included in the driver circuit portion 13, and OS transistors can be used as the other transistors. For example, OS transistors can be used as the transistors provided in the display portion 11, and LTPS transistors can be used as the transistors provided in the driver circuit portion 12 and the driver circuit portion 13.

A transistor using an oxide semiconductor having a wider band gap and a lower carrier density than silicon can achieve an extremely low off-state current. Thus, such a low off-state current enables long-term retention of electric charge accumulated in a capacitor that is connected to the transistor in series. Therefore, it is particularly preferable to use a transistor including an oxide semiconductor as the transistor M1 and the transistor M3 each of which is connected to the capacitor C1 in series. The use of the transistor including an oxide semiconductor as each of the transistor M1 and the transistor M3 can prevent leakage of charge retained in the capacitor C1 through the transistor M1 or the transistor M3. Furthermore, since charge retained in the capacitor C1 can be retained for a long time, a still image can be displayed for a long time without rewriting data in the pixel 21.

A data potential D is supplied to the wiring SL. A selection signal is supplied to the wiring GL. The selection signal includes a potential for bringing a transistor into a conducting state and a potential for bringing a transistor into a non-conducting state.

A reset potential is supplied to the wiring RL. An anode potential is supplied to the wiring AL. A cathode potential is supplied to the wiring CL. In the pixel 21, the anode potential is a potential higher than the cathode potential. The reset potential supplied to the wiring RL can be set such that a potential difference between the reset potential and the cathode potential is lower than the threshold voltage of the light-emitting element EL. The reset potential can be a potential higher than the cathode potential, a potential equal to the cathode potential, or a potential lower than the cathode potential.

Note that although the transistor is illustrated as an n-channel transistor in FIG. 13B, a p-channel transistor can also be used.

The transistors included in the pixel 21 are preferably formed to be arranged over the same substrate.

Note that transistors each including a pair of gates overlapping with each other with a semiconductor layer therebetween can be used as the transistors included in the pixel 21.

In the transistor including a pair of gates, the same potential is supplied to the pair of gates electrically connected to each other, which brings advantage that the transistor can have a higher on-state current and improved saturation characteristics. A potential for controlling the threshold voltage of the transistor may be supplied to one of the pair of gates. Furthermore, when a constant potential is supplied to one of the pair of gates, the stability of the electrical characteristics of the transistor can be improved. For example, one of the gates of the transistor may be electrically connected to a wiring to which a constant potential is supplied or may be electrically connected to a source or a drain of the transistor.

The pixel 21 illustrated in FIG. 13C is an example in which a transistor including a pair of gates is used as each of the transistor M1, the transistor M2, and the transistor M3. The pair of gates of the transistor M2 are electrically connected to each other. When such a transistor is as the transistor M1 and the transistor M3, the period in which data is written to the pixel 21 can be shortened. When such a transistor is used as the transistor M2, the saturation characteristics are improved, whereby emission luminance of the light-emitting element EL can be controlled easily and the display quality can be increased.

The pixel 21 illustrated in FIG. 13D is different from that in FIG. 13C in that a transistor M4, a wiring GL2, and a wiring GL3 are included and the gate of the transistor M3 is electrically connected to the wiring GL2. Different selection signals are supplied to the wiring GL2 and the wiring GL3. A gate of the transistor M4 is electrically connected to the wiring GL3. One of a source and a drain of the transistor M4 is electrically connected to the gate of the transistor M2 and the other of the source and the drain of the transistor M4 is electrically connected to the wiring RL.

The pixel 21 illustrated in FIG. 13E is different from that in FIG. 13D in including a capacitor C2. One electrode of the capacitor C1 is electrically connected to the gate of the transistor M2, and the other electrode thereof is electrically connected to the wiring AL.

FIG. 14 illustrates a configuration example of the pixel 21 that can be used as the subpixel 21R, the subpixel 21G, the subpixel 21B, or the like. The pixel 21 includes a light-emitting device 64, a transistor 51, a transistor 52, a transistor 53, a transistor 54, a capacitor 61, and a capacitor 62.

One electrode of the light-emitting device 64 is electrically connected to one of a source and a drain of the transistor 51. A gate of the transistor 51 is electrically connected to one electrode of the capacitor 61. The gate of the transistor 51 is electrically connected to one of a source and a drain of the transistor 52. The other of the source and the drain of the transistor 51 is electrically connected to one electrode of the capacitor 62. The other electrode of the capacitor 62 is electrically connected to the other electrode of the capacitor 61. The other electrode of the capacitor 62 is electrically connected to one of a source and a drain of the transistor 53. The other electrode of the capacitor 62 is electrically connected to one of a source and a drain of the transistor 54.

In the pixel 21 illustrated in FIG. 14, the capacitor 61 and the capacitor 62 are connected in series, and the gate of the transistor 51 functioning as a driving transistor and the other of the source and the drain of the transistor 51 are electrically connected to each other through these capacitors.

Examples of the light-emitting device 64 include self-light-emitting devices such as a light-emitting diode (LED), an organic light-emitting diode (OLED), a light-emitting diode in which quantum dots are used in a light-emitting layer (QLED: Quantum-dot Light Emitting Diode), and a semiconductor laser. It is also possible to use, for example, a MEMS (Micro Electro Mechanical Systems) shutter element, an optical interference type MEMS element, or an element using a microcapsule method, an electrophoretic method, an electrowetting method, an Electronic Liquid Powder (registered trademark) method, or the like.

A wiring to which the gate of the transistor 51, the one of the source and the drain of the transistor 52, and the one electrode of the capacitor 61 are connected is referred to as a node ND1. The current flowing to the light-emitting device 64 can be controlled with the potential of the node ND1 to control the emission luminance of the light-emitting device 64. A wiring to which the one of the source and the drain of the transistor 53, one electrode of the source and the drain of the transistor 54, the other electrode of the capacitor 61, and the other electrode of the capacitor 62 are connected is referred to as a node ND2.

The transistor 51 functions as a driving transistor that controls the amount of current flowing to the light-emitting device 64. The transistor 52 and the transistor 53 each function as a selection transistor that selects a pixel. The transistor 54 functions as a switch for writing, to the pixel, a specific potential (a reference potential) “Vref” driving the pixel 21.

A gate of the transistor 52 is electrically connected to a wiring 141. A gate of the transistor 54 is electrically connected to a wiring 141. A gate of the transistor 53 is electrically connected to the wiring 142. The other of the source and the drain of the transistor 52 is electrically connected to a wiring 151. The other of the source and the drain of the transistor 53 is electrically connected to the wiring 151.

One electrode of the capacitor 62 is electrically connected to a wiring 128. The wiring 128 preferably has a function of supplying a specific potential. The one electrode of the capacitor 62 is electrically connected to the wiring 128, whereby the potential of the one electrode of the capacitor 62 can be fixed to a specific potential supplied from the wiring 128 and a boosting operation can be stably performed. The other electrode of the light-emitting device 64 is electrically connected to a wiring 129. The wiring 128 and the wiring 129 can each function as a wiring (a power supply line) to which a power supply potential is supplied. For example, the wiring 128 can function as a high potential power supply line for supplying a potential higher than that of the wiring 129. The wiring 129 can function as a low potential power supply line for supplying a potential lower than that of the wiring 128.

The wiring 141 and the wiring 142 have a function of a scan line for controlling the operation of the transistor 52, the transistor 53, and the transistor 54. A scan signal supplied to the scan line is a signal for controlling the conducting state or non-conducting state (on or off) of the selection transistor (the transistor 52, the transistor 53, and the transistor 54) that functions as a switch in the pixel 21. The wiring 151 has a function of a data line for supplying the first data and the second data. The wiring 127 has a function of supplying a specific potential (reference potential) “Vref” for driving the pixel 21.

The node ND1 is a storage node, and the data supplied to the wiring 151 can be written to the node ND1 when the transistor 52 is brought into a conduction state. When the transistor 52 is brought into a non-conduction state, the data written to the node ND1 can be retained.

The node ND2 is a storage node, and the data supplied to the wiring 151 can be written to the node ND2 when the transistor 53 is brought into a conduction state. When the transistor 54 is brought into a conduction state, the data supplied to the wiring 127 can be written to the node ND2. In addition, when the transistor 53 and the transistor 54 are brought into a non-conduction state, the data written to the node ND2 can be retained.

A transistor having an extremely low off-state current is preferably used as at least one of the transistor 51, the transistor 52, the transistor 53, and the transistor 54. In particular, when transistors having an extremely low off-state current are used as the transistor 52, the transistor 53, and the transistor 54, the potentials of the node ND1 and the node ND2 can be retained for a long time. As the transistor, a transistor using a metal oxide in a channel formation region (hereinafter an OS transistor) can be suitably used, for example.

It is further preferable that OS transistors be used as all of the transistor 51, the transistor 52, the transistor 53, and the transistor 54. An OS transistor may be used as a transistor other than the transistor 51, the transistor 52, the transistor 53, and the transistor 54. In the case of operating within a range where the amount of leakage current is acceptable, a transistor containing silicon in a channel formation region (hereinafter a Si transistor) may be used. Alternatively, an OS transistor and a Si transistor may be used together. Examples of the Si transistor include a transistor containing amorphous silicon and a transistor containing crystalline silicon (microcrystalline silicon, low-temperature polysilicon, or single crystal silicon). Note that the transistors illustrated in FIG. 14 are all n-channel transistors, but p-channel transistors can also be used.

An example of the boosting operation of the pixel 21 illustrated in FIG. 14 will be described with reference to a timing chart shown in FIG. 15. Here is described an example of an operation in which the same image data are used as the first data and the second data and the second data is added to the first data to generate a voltage higher than a voltage corresponding to the image data.

In the following description, a high potential is represented by “High” and a low potential is represented by “Low.” The image data and a specific potential are represented by “Vdata” and “Vref,” respectively. As “Vref,” 0 V, a GND potential, or a specific reference potential can be used, for example. In addition, the potential of the wiring 128 is represented by “Vano.” For example, “Vano” is preferably set to a potential at which the transistor 51 operates in a saturation region when luminance of the light-emitting device 64 is the maximum. In addition, the potential of the wiring 129 is represented by “Vcath.” “Vcath” is preferably a potential at which the light-emitting device 64 does not emit light at the time when the potential of the node ND1 is the lowest.

First, an operation of writing image data “Vdata” to the node ND1 as the first data is described. Note that in potential distribution, potential coupling, or potential loss, detailed changes due to a circuit configuration, operation timing, and the like are not considered here.

At time T1, the potential of the wiring 141 is set to “High,” the potential of the wiring 142 is set to “Low,” the potential of the wiring 151 is set to “Vdata,” and the potential of the wiring 127 is set to “Vref,” so that the transistor 52 and the transistor 54 are brought into conduction states, and the potential “Vdata” of the wiring 151 is written to the node ND1 and the potential “Vref” of the wiring 127 is written to the node ND2.

At this time, when a difference between potentials applied to both terminals of the capacitor 61 is V1, the potential difference V1 can be expressed by Formula (1).

V1=Vdata−Vref (1)

Similarly, when a difference between potentials applied to both terminals of the capacitor 62 is V2, the potential difference V2 can be expressed by Formula (2).

V2=Vano−Vref (2)

At time T2, the potential of the wiring 141 is set to “Low” and the potential of the wiring 142 is set to “Low,” so that the transistor 52 and the transistor 54 are brought into non-conduction states.

At this time, the potential V_ND1of the node ND1 can be expressed in Formula (3). The potential V_ND2of the node ND2 can be expressed in Formula (4).

V_ND1=Vdata−a (3)

V_ND2=Vref−b (4)

At this time, the potential difference V1 between both terminals of the capacitor 61 can be expressed in Formula (5). The potential difference V2 between both terminals of the capacitor 62 can be expressed in Formula (6).

V1=(Vdata−a)−(Vref−b) (5)

V2=Vano−(Vref−b) (6)

Note that a is a constant and represents the amount of change in potential because of influences by feedthrough, charge injection, and the like when the transistor 52 is brought into a non-conduction state. In addition, b is a constant and represents the amount of change in potential because of influences by feedthrough, charge injection, and the like when the transistor 54 is brought into a non-conduction state.

Next, an operation in which the image data “Vdata” is written to the node ND2 as the second data and the potential of the node ND1 is boosted is described.

At time T3, the potential of the wiring 141 is set to “Low,” and the potential of the wiring 142 is set to “High,” whereby the transistor 53 is turned on, and the potential “Vdata” of the wiring 151 is written to the node ND2.

At this time, as the potential difference V1 between both terminals of the capacitor 61, the potential difference V1 expressed in Formula (5) is retained; thus, the potential V_ND1of the node ND1 can be expressed in Formula (7). The potential V_ND2of the node ND2 can be expressed in Formula (8).

V_ND1=2Vdata−Vref−a+b (7)

V_ND2=Vdata (8)

At Time T4, the potential of the wiring 141 is set to “Low” and the potential of the wiring 142 is set to “Low” to turn off the transistor 53 and a voltage Vgs between the gate and source of the transistor 51 becomes the sum of voltages held in the capacitor 61 and the capacitor 62, and current corresponding to Vgs flows through the light-emitting device 64.

In this case, the potential V_ND1of the node ND1 can be expressed in Formula (9). The potential V_ND2of the node ND2 can be expressed in Formula (10).

V_ND1=2Vdata−Vref−a+b−c (9)

V_ND2=Vdata−c (10)

Note that c is a constant and represents the amount of change in potential because of influences by feedthrough, charge injection, and the like when the transistor 53 is brought into a non-conduction state.

Here, in Formula (9), when Vref is “0 V” and the constant a, the constant b, and the constant c are zero, V_ND1can be expressed as “2Vdata” and can be obtained as a higher value than a potential “Vdata” supplied to the pixel 21. That is, by boosting V_ND1to a voltage higher than the voltage (Vdata) corresponding to the image data supplied to the pixel 21, the boosted voltage can be supplied to the transistor 51 functioning as a driving transistor. Accordingly, the current flowing in the light-emitting device 64 can be increased, and a display device with high luminance can be obtained.

The operations in FIG. 15 can be sequentially performed in one horizontal period.

In the display device of one embodiment of the present invention, a high voltage can be generated even by using a general-purpose driver IC. For example, a voltage that is supplied from a driver IC in order to drive the light-emitting device or the like can be approximately halved; thus, power consumption of the display device can be reduced. As another example, by writing the same image data twice, the current flowing through the light-emitting device can be increased, so that the luminance of the display can be increased.

Such a combination of the first data and the second data enables upconversion, HDR display, correction of display unevenness unique to display devices, and correction of the threshold voltage of transistors included in pixels, for example. Alternatively, they can be performed in combination.

In the upconversion operation, for example, different correction data are supplied to four adjacent pixels (in two rows and two columns) and the same image data are supplied to these pixels. The supplied image data are corrected (converted) into different image data in the respective pixels, and display in each pixel can be performed. For example, image data that is applied to one given pixel for 4K2K data is input to four given pixels in a display device having pixels in number corresponding to 8K4K, and different correction data are input to the four pixels, whereby display with increased resolution can be performed.

The display device of one embodiment of the present invention can display different images superimposed on each other, which is the correction of image data in a broad sense. For example, it is possible to display a composite image in which a first image composed of the image data “Vdata” and a second image composed of the correction data “Vw” are superimposed on each other. Such a combination of the image data and the correction data enables improvement in luminance of the entire displayed image, for example, as well as display of an image synthesized from different images. For example, the combination can be applied to insertion of a character, display of augmented reality (AR), and the like.

[Display Device 400C]

The display device 400C illustrated in FIG. 16 includes a substrate 301, the light-emitting elements 430a, 430b, and 430c, a capacitor 240, and a transistor 310.

The transistor 310 is a transistor including a channel formation region in the substrate 301. As the substrate 301, a semiconductor substrate such as a single crystal silicon substrate can be used, for example. The transistor 310 includes part of the substrate 301, a conductive layer 311, low-resistance regions 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is positioned between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance regions 312 are regions where the substrate 301 is doped with an impurity, and function as a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311 and functions as an insulating layer.

An element isolation layer 315 is provided between two adjacent transistors 310 to be embedded in the substrate 301.

An insulating layer 261 is provided to cover the transistor 310, and the capacitor 240 is provided over the insulating layer 261.

The capacitor 240 includes a conductive layer 241, a conductive layer 245, and an insulating layer 243 positioned therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

The conductive layer 241 is provided over the insulating layer 261 and is embedded in an insulating layer 254. The conductive layer 241 is electrically connected to one of the source and the drain of the transistor 310 through a plug 271 embedded in the insulating layer 261. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 therebetween.

The insulating layer 255 is provided to cover the capacitor 240, and the light-emitting element 430a, the light-emitting element 430b, the light-emitting element 430c, and the like are provided over the insulating layer 255. The protective layer 416 is provided over the light-emitting element 430a, the light-emitting element 430b, and the light-emitting element 430c, and a substrate 420 is bonded to a top surface of the protective layer 416 with a resin layer 419. The substrate 420 corresponds to the substrate 292 illustrated in FIG. 12A.

The pixel electrode of the light-emitting element is electrically connected to one of the source and the drain of the transistor 310 through a plug 256 embedded in the insulating layer 255, the conductive layer 241 embedded in the insulating layer 254, and the plug 271 embedded in the insulating layer 261.

[Display Device 400D]

The display device 400D illustrated in FIG. 17 differs from the display device 400C mainly in a structure of a transistor. Note that portions similar to those of the display device 400C are not described in some cases.

A transistor 320 is a transistor that contains a metal oxide (also referred to as an oxide semiconductor) in a semiconductor layer where a channel is formed.

The transistor 320 includes a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a pair of conductive layers 325, an insulating layer 326, and a conductive layer 327.

A substrate 331 corresponds to the substrate 291 in FIG. 12A and FIG. 12B. As the substrate 331, an insulating substrate or a semiconductor substrate can be used.

An insulating layer 332 is provided over the substrate 331. The insulating layer 332 functions as a barrier layer that prevents diffusion of impurities such as water and hydrogen from the substrate 331 into the transistor 320 and release of oxygen from the semiconductor layer 321 to the insulating layer 332 side. As the insulating layer 332, for example, a film through which hydrogen or oxygen is less likely to diffuse than in a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

The conductive layer 327 is provided over the insulating layer 332, and the insulating layer 326 is provided to cover the conductive layer 327. The conductive layer 327 functions as a first gate electrode of the transistor 320, and part of the insulating layer 326 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used as at least part of the insulating layer 326 that is in contact with the semiconductor layer 321. The top surface of the insulating layer 326 is preferably planarized.

The semiconductor layer 321 is provided over the insulating layer 326. The semiconductor layer 321 preferably includes a metal oxide (also referred to as an oxide semiconductor) film having semiconductor characteristics. A material that can be suitably used for the semiconductor layer 321 will be described in detail later.

The pair of conductive layers 325 are provided over and in contact with the semiconductor layer 321 and function as a source electrode and a drain electrode.

An insulating layer 328 is provided to cover the top surfaces and side surfaces of the pair of conductive layers 325, the side surface of the semiconductor layer 321, and the like, and an insulating layer 264 is provided over the insulating layer 328. The insulating layer 328 functions as a barrier layer that prevents diffusion of impurities such as water and hydrogen from the insulating layer 264 and the like into the semiconductor layer 321 and release of oxygen from the semiconductor layer 321. As the insulating layer 328, an insulating film similar to the insulating layer 332 can be used.

An opening reaching the semiconductor layer 321 is provided in the insulating layer 328 and the insulating layer 264. The insulating layer 323 that is in contact with the side surfaces of the insulating layer 264, the insulating layer 328, and the conductive layer 325, and the top surface of the semiconductor layer 321, and the conductive layer 324 are embedded in the opening. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer.

The top surface of the conductive layer 324, the top surface of the insulating layer 323, and the top surface of the insulating layer 264 are planarized so that they are substantially level with each other, and an insulating layer 329 and an insulating layer 265 are provided to cover these layers.

The insulating layer 264 and the insulating layer 265 each function as an interlayer insulating layer. The insulating layer 329 functions as a barrier layer that prevents diffusion of impurities such as water and hydrogen from the insulating layer 265 and the like into the transistor 320. As the insulating layer 329, an insulating film similar to the insulating layer 328 and the insulating layer 332 can be used.

A plug 274 electrically connected to one of the pair of conductive layers 325 is provided so as to be embedded in the insulating layer 265, the insulating layer 329, and the insulating layer 264. Here, the plug 274 preferably includes a conductive layer 274a that covers the side surface of an opening in the insulating layer 265, the insulating layer 329, the insulating layer 264, and the insulating layer 328 and part of the top surface of the conductive layer 325, and a conductive layer 274b in contact with the top surface of the conductive layer 274a. In this case, a conductive material through which hydrogen and oxygen are less likely to diffuse is preferably used for the conductive layer 274a.

The structures of the insulating layer 254 and the components thereover up to the substrate 420 in the display device 400D are similar to those in the display device 400C.

[Display Device 400E]

The display device 400E illustrated in FIG. 18 has a structure in which a transistor 310A and a transistor 310B each having a channel formed in a semiconductor substrate are stacked.

In the display device 400E, a substrate 301B provided with the transistor 310B, the capacitor 240, and the light-emitting elements is attached to a substrate 301A provided with the transistor 310A.

The substrate 301B is provided with a plug 343 that penetrates the substrate 301B. In addition, the plug 343 is electrically connected to a conductive layer 342 that is provided on a rear surface of the substrate 301 (a surface that is opposite to the substrate 120 side). Meanwhile, over the substrate 301A, a conductive layer 341 is provided over the insulating layer 261.

The conductive layer 341 and the conductive layer 342 are bonded to each other, whereby the substrate 301A and the substrate 301B are electrically connected to each other.

The conductive layer 341 and the conductive layer 342 are preferably formed using the same conductive material. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, a metal nitride film containing the above element as a component (a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film), or the like can be used. Copper is particularly preferably used for the conductive layer 341 and the conductive layer 342. In that case, it is possible to employ Cu-to-Cu (copper-to-copper) direct bonding technique (a technique for achieving electrical continuity by connecting Cu (copper pads). Note that the conductive layer 341 and the conductive layer 342 may be bonded to each other with a bump therebetween.

[Display Device 400F]

The display device 400F illustrated in FIG. 19 has a structure in which the transistor 310 whose channel is formed in the substrate 301 and the transistor 320 including a metal oxide in the semiconductor layer where the channel is formed are stacked. Note that portions similar to those of the display device 400C and the display device 400D are not described in some cases.

The insulating layer 261 is provided to cover the transistor 310, and a conductive layer 251 is provided over the insulating layer 261. An insulating layer 262 is provided to cover the conductive layer 251, and a conductive layer 252 is provided over the insulating layer 262. The conductive layer 251 and the conductive layer 252 each function as a wiring. An insulating layer 263 and the insulating layer 332 are provided to cover the conductive layer 252, and the transistor 320 is provided over the insulating layer 332. The insulating layer 265 is provided to cover the transistor 320, and the capacitor 240 is provided over the insulating layer 265. The capacitor 240 and the transistor 320 are electrically connected to each other through the plug 274.

The transistor 320 can be used as a transistor included in the pixel circuit. The transistor 310 can be used as a transistor included in the pixel circuit or a transistor included in a driver circuit (a gate line driver circuit or a source line driver circuit) for driving the pixel circuit. The transistor 310 and the transistor 320 can also be used as transistors included in a variety of circuits such as an arithmetic circuit and a memory circuit.

With such a structure, not only the pixel circuit but also the driver circuit and the like can be formed directly under the light-emitting elements; thus, the display device can be downsized as compared with the case where a driver circuit is provided around a display region.

At least part of the structure examples, the drawings corresponding thereto, and the like described in this embodiment as an example can be combined with the other structure examples, the other drawings, and the like as appropriate.

Embodiment 4

In this embodiment, structure examples of a display device of one embodiment of the present invention are described.

The display device of one embodiment of the present invention includes a first layer, a second layer over the first layer, and a third layer over the second layer. The first layer includes a first transistor including silicon in a channel formation region. The second layer includes a second transistor including a metal oxide in a channel formation region. The third layer includes a plurality of light-emitting elements.

An EL layer includes, for example, a light-emitting layer that exhibits white light, and the EL layer is provided to be shared across the plurality of light-emitting elements arranged in a matrix. It is preferable that crosstalk be not observed between adjacent light-emitting elements among the plurality of light-emitting elements.

FIG. 20 is a schematic cross-sectional view of a display device 200A. The display device 200A includes, between a substrate 501 and a substrate 502, a light-emitting element 250R, a light-emitting element 250G, a transistor 210, a transistor 220, a capacitor 240, and the like.

The transistor 210 is a transistor whose channel formation region is formed in the substrate 501. As the substrate 501, a semiconductor substrate such as a single crystal silicon substrate can be used, for example. The transistor 210 includes part of the substrate 501, a conductive layer 511, a low-resistance region 512, an insulating layer 513, an insulating layer 514, and the like. The conductive layer 511 functions as a gate electrode. The insulating layer 513 is positioned between the substrate 501 and the conductive layer 511 and functions as a gate insulating layer. The low-resistance region 512 is a region where the substrate 501 is doped with an impurity, and functions as one of a source and a drain. The insulating layer 514 is provided to cover a side surface of the conductive layer 511 and functions as an insulating layer.

In addition, an element isolation layer 515 is provided between two adjacent transistors 210 to be embedded in the substrate 501.

A wiring layer 203 is provided between the transistor 210 and the transistor 220. The wiring layer 203 has a structure in which layers each including one or more wirings are stacked. Each of the layers includes a conductive layer 571, and an interlayer insulating layer 573 is provided between the layers. Furthermore, the conductive layers 571 of different layers are electrically connected to one another with plugs 572 provided in the interlayer insulating layers 573.

The transistor 220 is provided over the wiring layer 203. The transistor 220 is a transistor in which a metal oxide (also referred to as an oxide semiconductor) is used in a semiconductor layer where a channel is formed.

The transistor 220 includes a semiconductor layer 521, an insulating layer 523, a conductive layer 524, a pair of conductive layers 525, an insulating layer 226, a conductive layer 227, and the like.

An insulating layer 279 is provided over the wiring layer 203. The insulating layer 279 functions as a barrier layer that prevents diffusion of impurities such as water and hydrogen from the wiring layer 203 side into the transistor 220 and release of oxygen from the semiconductor layer 521 to the wiring layer 203 side. As the insulating layer 279, for example, a film through which hydrogen or oxygen is less likely to diffuse than in a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

The conductive layer 227 is provided over the insulating layer 279, and the insulating layer 226 is provided to cover the conductive layer 227. The conductive layer 227 functions as a first gate electrode of the transistor 220, and part of the insulating layer 226 functions as a first gate insulating layer. For the insulating layer 226 at least in a portion in contact with the semiconductor layer 521, an oxide insulating film such as a silicon oxide film is preferably used.

The semiconductor layer 521 is provided over the insulating layer 226. The semiconductor layer 521 preferably includes a metal oxide (also referred to as an oxide semiconductor) film having semiconductor characteristics.

The pair of conductive layers 525 are provided over and in contact with the semiconductor layer 521 and function as a source electrode and a drain electrode.

An insulating layer 232 is provided to cover the top surfaces and side surfaces of the pair of conductive layers 525, the side surfaces of the semiconductor layer 521, and the like, and an insulating layer 261 is provided over the insulating layer 232. The insulating layer 232 functions as a barrier layer that prevents diffusion of impurities such as water and hydrogen from the interlayer insulating layer and the like into the semiconductor layer 521 and release of oxygen from the semiconductor layer 521. As the insulating layer 232, an insulating film similar to the insulating layer 279 can be used.

An opening reaching the semiconductor layer 521 is provided in the insulating layer 232 and the insulating layer 261. The insulating layer 523 that is in contact with the side surfaces of the insulating layer 261, the insulating layer 232, and the conductive layer 525, and the top surface of the semiconductor layer 521, and the conductive layer 524 over the insulating layer 523 are embedded in the opening. The conductive layer 524 functions as a second gate electrode, and the insulating layer 523 functions as a second gate insulating layer.

The top surface of the conductive layer 524, the top surface of the insulating layer 523, and the top surface of the insulating layer 261 are planarized so that they are substantially level with each other, and an insulating layer 233 is provided to cover these layers. An opening portion is provided in the stacked-layer structure between the insulating layer 233 and the insulating layer 279, and part of the insulating layer 233 is in contact with the insulating layer 279 in the opening portion. The insulating layer 261 functions as an interlayer insulating layer. The insulating layer 233 functions as a barrier layer that prevents diffusion of impurities such as water or hydrogen from layers above the insulating layer 233. As the insulating layer 233, an insulating film similar to the insulating layer 279 or the like can be used.

A capacitor 240 is provided over the insulating layer 233.

The capacitor 240 includes a conductive layer 241, a conductive layer 245, and an insulating layer 243 positioned therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

An insulating layer 234 is provided to cover the capacitor 240. As the insulating layer 234, an insulating film similar to the insulating layer 279 can be used. The insulating layer 262 is provided over the insulating layer 279 with an interlayer insulating layer and a wiring therebetween, and the light-emitting element 250R and the light-emitting element 250G are provided over the insulating layer 262.

The light-emitting element 250R includes the conductive layer 251, the conductive layer 252R, the EL layer 253W, a conductive layer 267, and the like.

The conductive layer 251 has a property of reflecting visible light, and the conductive layer 252R has a property of transmitting visible light. The conductive layer 267 has a property of reflecting and transmitting visible light. The conductive layer 252R functions as an optical adjustment layer for adjusting the optical path length between the conductive layer 251 and the conductive layer 267. The thickness of the optical adjustment layer can differ between the light-emitting elements of different colors. The thickness of the conductive layer 252R of the light-emitting element 250R is different from the thickness of a conductive layer 252G of the light-emitting element 250G.

An insulating layer 269 is provided to cover an end portion of the conductive layer 252R and an end portion of the conductive layer 252G.

The EL layer 253W and the conductive layer 267 are provided across a plurality of pixels. The EL layer 253W includes the light-emitting layer that exhibits white light.

A coloring layer 268R is provided over the light-emitting element 250R with an insulating layer 235 therebetween. A coloring layer 268G is provided over the light-emitting element 250G. Part of a coloring layer 268B is illustrated in FIG. 20.

For example, the coloring layer 268R transmits red light, the coloring layer 268G transmits green light, and the coloring layer 268B transmits blue light. This can increase the color purity of light from the light-emitting elements, so that a display device with higher display quality can be achieved. Furthermore, positional alignment of the light-emitting elements and the coloring layers is easier in the case where the coloring layers are formed over the insulating layer 235 than in the case where the coloring layers are formed on the substrate 502 side and then the substrates 501 and substrate 502 are bonded to each other; accordingly, a display device with extremely high resolution can be achieved.

A lens array 257 is provided over the coloring layer 268R and over the coloring layer 268G. Light emitted from the light-emitting element 250R is colored by the coloring layer 268R and is emitted to the outside through the lens array 257. The lens array 257 is not necessarily provided if not needed.

The display device 200A includes the substrate 502 on the viewing side. The substrate 502 and the substrate 501 are bonded to each other. As the substrate 502, a light-transmitting substrate, such as a glass substrate, a quartz substrate, a sapphire substrate, or a plastic substrate, can be used.

With such a structure, a display device with extremely high resolution and high display quality can be achieved.

At least part of the structure examples, the drawings corresponding thereto, and the like described in this embodiment as an example can be combined with the other structure examples, the other drawings, and the like as appropriate.

Embodiment 5

In this embodiment, a light-emitting element (also referred to as a light-emitting device) that can be used in the display device of one embodiment of the present invention will be described.

As illustrated in FIG. 21A, the light-emitting device includes an EL layer 786 between a pair of electrodes (a lower electrode 772 and an upper electrode 788). The EL layer 786 can be formed of a plurality of layers such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can include, for example, a layer containing a substance with a high electron-injection property (an electron-injection layer) and a layer containing a substance with a high electron-transport property (an electron-transport layer). The light-emitting layer 4411 contains a light-emitting compound, for example. The layer 4430 can include, for example, a layer containing a substance with a high hole-injection property (a hole-injection layer) and a layer containing a substance with a high hole-transport property (a hole-transport layer).

The structure including the layer 4420, the light-emitting layer 4411, and the layer 4430, which is provided between the pair of electrodes, can serve as a single light-emitting unit, and the structure in FIG. 21A is referred to as a single structure in this specification.

FIG. 21B is a variation example of the EL layer 786 included in the light-emitting device illustrated in FIG. 21A. Specifically, the light-emitting device illustrated in FIG. 21B includes a layer 4430-1 over the lower electrode 772, a layer 4430-2 over the layer 4430-1, the light-emitting layer 4411 over the layer 4430-2, a layer 4420-1 over the light-emitting layer 4411, a layer 4420-2 over the layer 4420-1, and the upper electrode 788 over the layer 4420-2. For example, when the lower electrode 772 functions as an anode and the upper electrode 788 functions as a cathode, the layer 4430-1 functions as a hole-injection layer, the layer 4430-2 functions as a hole-transport layer, the layer 4420-1 functions as an electron-transport layer, and the layer 4420-2 functions as an electron-injection layer. Alternatively, when the lower electrode 772 functions as a cathode and the upper electrode 788 functions as an anode, the layer 4430-1 functions as an electron-injection layer, the layer 4430-2 functions as an electron-transport layer, the layer 4420-1 functions as a hole-transport layer, and the layer 4420-2 functions as a hole-injection layer. With such a layer structure, carriers can be efficiently injected to the light-emitting layer 4411, and the efficiency of the recombination of carriers in the light-emitting layer 4411 can be enhanced.

Note that the structure where a plurality of light-emitting layers (light-emitting layers 4411, 4412, and 4413) are provided between the layer 4420 and the layer 4430 as illustrated in FIG. 21C and FIG. 21D is a variation of the single structure.

The structure where a plurality of light-emitting units (an EL layer 786a and an EL layer 786b) is connected in series with an intermediate layer (charge generation layer) 4440 therebetween as illustrated in FIG. 21E and FIG. 21F is referred to as a tandem structure in this specification. In this specification and the like, the structure illustrated in FIG. 21E and FIG. 21F is referred to as a tandem structure; however, without being limited to this, a tandem structure may be referred to as a stack structure, for example. Note that the tandem structure enables a light-emitting device capable of high-luminance light emission.

Furthermore, a display device with a high contrast ratio can be obtained by combining a white light-emitting device (one or both of a single structure and a tandem structure), a color filter, and the MML structure of one embodiment of the present invention.

When the above-described white light-emitting device (having the single structure or the tandem structure) and a light-emitting device having the SBS structure are compared with each other, the light-emitting device having the SBS structure can have lower power consumption than the white light-emitting device. To reduce power consumption, a light-emitting device having the SBS structure is preferably used. Meanwhile, the white light-emitting device is preferable in terms of lower manufacturing cost or higher manufacturing yield because the manufacturing process of the white light-emitting device is simpler than that of a light-emitting device having the SBS structure.

In particular, in the case where a light-emitting device having an MML structure employs the SBS structure, a layer provided between light-emitting devices (e.g., also referred to as an organic layer or a common layer which is shared by the light-emitting devices) is divided; accordingly, display with no or extremely low side leakage can be achieved.

In FIG. 21C, light-emitting material that emit light of the same color may be used for the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413.

Alternatively, different light-emitting materials may be used for the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413. White light emission can be obtained when the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413 emit light of complementary colors. FIG. 21D illustrates an example where a coloring layer 785 functioning as a color filter is provided. When white light passes through a color filter, light of a desired color can be obtained.

In FIG. 21E, the same light-emitting material may be used for the light-emitting layer 4411 and the light-emitting layer 4412. Alternatively, light-emitting materials that emit light of different colors may be used for the light-emitting layer 4411 and the light-emitting layer 4412. White light emission can be obtained when the light-emitting layer 4411 and the light-emitting layer 4412 emit light of complementary colors. FIG. 21F illustrates an example where the coloring layer 785 is further provided.

Note that also in FIG. 21C, FIG. 21D, FIG. 21E, and FIG. 21F, the layer 4420 and the layer 4430 may each have a stacked-layer structure of two or more layers as illustrated in FIG. 21B.

A structure where light-emitting layers (here, blue (B), green (G), and red (R)) of light-emitting devices are separately formed is referred to as an SBS (Side By Side) structure in some cases.

The emission color of the light-emitting device can be red, green, blue, cyan, magenta, yellow, white, or the like depending on the material that constitutes the EL layer 786. Furthermore, the color purity can be further increased when the light-emitting device has a microcavity structure.

The light-emitting device that emits white light preferably contains two or more kinds of light-emitting substances in the light-emitting layer. To obtain white light emission, two or more kinds of light-emitting substances are selected such that their emission colors are complementary. For example, when the emission color of a first light-emitting layer and the emission color of a second light-emitting layer are complementary colors, the light-emitting device can be configured to emit white light as a whole. The same applies to a light-emitting device including three or more light-emitting layers.

The light-emitting layer preferably contains two or more light-emitting substances that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), and the like. Alternatively, the light-emitting layer preferably contains two or more light-emitting substances that emit light containing two or more of spectral components of R, G, and B.

A specific structure example of the light-emitting device will be described here.

The light-emitting devices include at least the light-emitting layer. The light-emitting device may further include, as a layer other than the light-emitting layer, a layer including a substance with a high hole-injection property, a substance with a high hole-transport property, a hole-blocking material, a substance with a high electron-transport property, an electron-blocking material, a substance with a high electron-injection property, a substance with a bipolar property (a substance with a high electron-transport property and a high hole-transport property), or the like.

Either a low molecular compound or a high molecular compound can be used for the light-emitting device, and an inorganic compound may also be included. Each layer included in the light-emitting device can be formed by an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

For example, the light-emitting device can include one or more of a hole-injection layer, a hole-transport layer, a hole-blocking layer, an electron-blocking layer, an electron-transport layer, and an electron-injection layer.

The hole-injection layer is a layer injecting holes from an anode to the hole-transport layer, and a layer containing a material with a high hole-injection property. Examples of a material with a high hole-injection property include an aromatic amine compound and a composite material containing a hole-transport material and an acceptor material (electron-accepting material).

The hole-transport layer is a layer transporting holes, which are injected from the anode by the hole-injection layer, to the light-emitting layer. The hole-transport layer is a layer containing a hole-transport material. As the hole-transport material, a substance having a hole mobility higher than or equal to 10⁻⁶cm²/Vs is preferable. Note that other substances can also be used as long as they have a property of transporting more holes than electrons. As the hole-transport material, materials with a high hole-transport property, such as a π-electron rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, and a furan derivative) and an aromatic amine (a compound having an aromatic amine skeleton), are preferable.

The electron-transport layer is a layer transporting electrons, which are injected from a cathode by the electron-injection layer, to the light-emitting layer. The electron-transport layer is a layer containing an electron-transport material. As the electron-transport material, a substance having an electron mobility higher than or equal to 1×10⁻⁶cm²/Vs is preferable. Note that other substances can also be used as long as they have a property of transporting more electrons than holes. As the electron-transport material, it is possible to use a material having a high electron-transport property, such as a metal complex having a quinoline skeleton, a metal complex having a benzoquinoline skeleton, a metal complex having an oxazole skeleton, a metal complex having a thiazole skeleton, an oxadiazole derivative, a triazole derivative, an imidazole derivative, an oxazole derivative, a thiazole derivative, a phenanthroline derivative, a quinoline derivative having a quinoline ligand, a benzoquinoline derivative, a quinoxaline derivative, a dibenzoquinoxaline derivative, a pyridine derivative, a bipyridine derivative, a pyrimidine derivative, or a π-electron deficient heteroaromatic compound such as a nitrogen-containing heteroaromatic compound.

The electron-injection layer is a layer injecting electrons from a cathode to the electron-transport layer and a layer containing a material with a high electron-injection property. As the material with a high electron-injection property, an alkali metal, an alkaline earth metal, or a compound thereof can be used. As the material with a high electron-injection property, a composite material containing an electron-transport material and a donor material (an electron-donating material) can also be used.

For the electron-injection layer, for example, an alkali metal, an alkaline earth metal, or a compound thereof, such as lithium, cesium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF₂), 8-(quinolinolato)lithium (abbreviation: Liq), 2-(2-pyridyl)phenolatolithium (abbreviation: LiPP), 2-(2-pyridyl)-3-pyridinolato lithium (abbreviation: LiPPy), 4-phenyl-2-(2-pyridyl)phenolatolithium (abbreviation: LiPPP), lithium oxide (LiO_x), or cesium carbonate can be used.

Alternatively, as the above-described electron-injection layer, an electron-transport material may be used. For example, a compound having an unshared electron pair and an electron deficient heteroaromatic ring can be used as the electron-transport material. Specifically, a compound having at least one of a pyridine ring, a diazine ring (a pyrimidine ring, a pyrazine ring, and a pyridazine ring), and a triazine ring can be used.

Note that the lowest unoccupied molecular orbital (LUMO) of the organic compound having an unshared electron pair is preferably greater than or equal to −3.6 eV and less than or equal to −2.3 eV. In general, the highest occupied molecular orbital (HOMO) level and the LUMO level of an organic compound can be estimated by CV (cyclic voltammetry), photoelectron spectroscopy, optical absorption spectroscopy, inverse photoelectron spectroscopy, or the like.

For example, 4,7-diphenyl-1,10-phenanthroline (abbreviation: BPhen), 2,9-di(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen), diquinoxalino[2,3-a:2′,3′-c]phenazine (abbreviation: HATNA), 2,4,6-tris[3′-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviation: TmPPPyTz), or the like can be used as the organic compound having an unshared electron pair. Note that NBPhen has a higher glass transition temperature (Tg) than BPhen and thus has high heat resistance.

The light-emitting layer is a layer containing a light-emitting substance. The light-emitting layer can contain one or more kinds of light-emitting substances. As the light-emitting substance, a substance that exhibits an emission color of blue, violet, bluish violet, green, yellowish green, yellow, orange, red, or the like is appropriately used. A substance that emits near-infrared light can also be used as the light-emitting substance.

Examples of the light-emitting substance include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

Examples of a fluorescent material include a pyrene derivative, an anthracene derivative, a triphenylene derivative, a fluorene derivative, a carbazole derivative, a dibenzothiophene derivative, a dibenzofuran derivative, a dibenzoquinoxaline derivative, a quinoxaline derivative, a pyridine derivative, a pyrimidine derivative, a phenanthrene derivative, and a naphthalene derivative.

Examples of a phosphorescent material include an organometallic complex (particularly an iridium complex) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; an organometallic complex (particularly an iridium complex) having a phenylpyridine derivative including an electron-withdrawing group as a ligand; a platinum complex; and a rare earth metal complex.

The light-emitting layer may contain one or more kinds of organic compounds (e.g., a host material or an assist material) in addition to the light-emitting substance (guest material). As one or more kinds of organic compounds, one or both of a hole-transport material and an electron-transport material can be used. Alternatively, as one or more kinds of organic compounds, a bipolar material or a TADF material may be used.

The light-emitting layer preferably contains a phosphorescent material and a combination of a hole-transport material and an electron-transport material that easily forms an exciplex, for example. With such a structure, light emission can be efficiently obtained by ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from an exciplex to a light-emitting substance (a phosphorescent material). When a combination of materials is selected to form an exciplex that exhibits light emission whose wavelength overlaps with the wavelength of the lowest-energy-side absorption band of the light-emitting substance, energy can be transferred smoothly and light emission can be obtained efficiently. With this structure, high efficiency, low-voltage driving, and a long lifetime of a light-emitting device can be achieved at the same time.

This embodiment can be combined with the other embodiments as appropriate.

Embodiment 6

In this embodiment, a metal oxide (also referred to as an oxide semiconductor) that can be used in the OS transistor described in the above embodiment will be described.

The metal oxide preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. In addition, aluminum, gallium, yttrium, tin, or the like is preferably contained. Furthermore, one or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like may be contained.

The metal oxide can be formed by a sputtering method, a chemical vapor deposition (CVD) method such as a metal organic chemical vapor deposition (MOCVD) method, an atomic layer deposition (ALD) method, or the like.

Amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single-crystal, and polycrystalline (polycrystal) structures can be given as examples of a crystal structure of an oxide semiconductor.

Note that a crystal structure of a film or a substrate can be evaluated with an X-ray diffraction (XRD) spectrum. For example, evaluation is possible using an XRD spectrum which is obtained by GIXD (Grazing-Incidence XRD) measurement. Note that a GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.

For example, an XRD spectrum of a quartz glass substrate shows a peak with a substantially bilaterally symmetrical shape. On the other hand, a peak of an XRD spectrum of an IGZO film having a crystal structure has a bilaterally asymmetrical shape. The asymmetrical peak of the XRD spectrum clearly shows the existence of crystals in the film or the substrate. In other words, the crystal structure of the film or the substrate cannot be regarded as “amorphous” unless it has a bilaterally symmetrical peak in the XRD spectrum.

A crystal structure of a film or a substrate can also be evaluated with a diffraction pattern obtained by a nanobeam electron diffraction (NBED) method (such a pattern is also referred to as a nanobeam electron diffraction pattern). For example, a halo pattern is observed in the diffraction pattern of the quartz glass substrate, which indicates that the quartz glass substrate is in an amorphous state. Furthermore, not a halo pattern but a spot-like pattern is observed in a diffraction pattern of an IGZO film formed at room temperature. Thus, it is suggested that the IGZO film formed at room temperature is in an intermediate state, which is neither a crystal state nor an amorphous state, and it cannot be concluded that the IGZO film is in an amorphous state.

<<Structure of Oxide Semiconductor>>

Oxide semiconductors might be classified in a manner different from the above-described one when classified in terms of the structure. Oxide semiconductors are classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor, for example. Examples of the non-single-crystal oxide semiconductor include the above-described CAAC-OS and nc-OS. Other examples of the non-single-crystal oxide semiconductor include a polycrystalline oxide semiconductor, an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

Here, the above-described CAAC-OS, nc-OS, and a-like OS are described in detail.

[CAAC-OS]

The CAAC-OS is an oxide semiconductor that has a plurality of crystal regions each of which has c-axis alignment in a particular direction. Note that the particular direction refers to the film thickness direction of a CAAC-OS film, the normal direction of the surface where the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystal region refers to a region having a periodic atomic arrangement. When an atomic arrangement is regarded as a lattice arrangement, the crystal region also refers to a region with a uniform lattice arrangement. The CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and the region has distortion in some cases. Note that distortion refers to a portion where the direction of a lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of crystal regions are connected. That is, the CAAC-OS is an oxide semiconductor having c-axis alignment and having no clear alignment in the a-b plane direction.

Note that each of the plurality of crystal regions is formed of one or more fine crystals (crystals each of which has a maximum diameter of less than 10 nm). In the case where the crystal region is formed of one fine crystal, the maximum diameter of the crystal region is less than 10 nm. In the case where the crystal region is formed of a large number of fine crystals, the size of the crystal region may be approximately several tens of nanometers.

In the case of an In-M-Zn oxide (the element M is one or more kinds selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, an (M,Zn) layer) are stacked. Note that indium and the element M can be replaced with each other. Therefore, indium may be contained in the (M,Zn) layer. In addition, the element M may be contained in the In layer. Note that Zn may be contained in the In layer. Such a layered structure is observed as a lattice image in a high-resolution TEM (Transmission Electron Microscope) image, for example.

When the CAAC-OS film is subjected to structural analysis by Out-of-plane XRD measurement with an XRD apparatus using θ/2θ scanning, for example, a peak indicating c-axis alignment is detected at 2θ of 31° or around 31°. Note that the position of the peak indicating c-axis alignment (the value of 2θ) may change depending on the kind, composition, or the like of the metal element contained in the CAAC-OS.

For example, a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that one spot and another spot are observed point-symmetrically with a spot of the incident electron beam passing through a sample (also referred to as a direct spot) as the symmetric center.

When the crystal region is observed from the particular direction, a lattice arrangement in the crystal region is basically a hexagonal lattice arrangement; however, a unit lattice is not always a regular hexagon and is a non-regular hexagon in some cases. A pentagonal lattice arrangement, a heptagonal lattice arrangement, and the like are included in the distortion in some cases. Note that a clear crystal grain boundary (grain boundary) cannot be observed even in the vicinity of the distortion in the CAAC-OS. That is, formation of a crystal grain boundary is inhibited by the distortion of lattice arrangement. This is probably because the CAAC-OS can tolerate distortion owing to a low density of arrangement of oxygen atoms in the a-b plane direction, an interatomic bond distance changed by substitution of a metal atom, and the like.

Note that a crystal structure in which a clear crystal grain boundary is observed is what is called polycrystal. It is highly probable that the crystal grain boundary becomes a recombination center and captures carriers and thus decreases the on-state current and field-effect mobility of a transistor, for example. Thus, the CAAC-OS in which no clear crystal grain boundary is observed is one of crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that Zn is preferably contained to form the CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can inhibit generation of a crystal grain boundary as compared with In oxide.

The CAAC-OS is an oxide semiconductor with high crystallinity in which no clear crystal grain boundary is observed. Thus, in the CAAC-OS, a reduction in electron mobility due to the crystal grain boundary is unlikely to occur. Moreover, since the crystallinity of an oxide semiconductor might be decreased by entry of impurities, formation of defects, or the like, the CAAC-OS can be regarded as an oxide semiconductor that has small amounts of impurities and defects (e.g., oxygen vacancies). Thus, an oxide semiconductor including the CAAC-OS is physically stable. Therefore, the oxide semiconductor including the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable with respect to high temperature in the manufacturing process (what is called thermal budget). Accordingly, the use of the CAAC-OS for the OS transistor can extend the degree of freedom of the manufacturing process.

[nc-OS]

In the nc-OS, a microscopic region (e.g., a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. In other words, the nc-OS includes a fine crystal. Note that the size of the fine crystal is, for example, greater than or equal to 1 nm and less than or equal to 10 nm, particularly greater than or equal to 1 nm and less than or equal to 3 nm; thus, the fine crystal is also referred to as a nanocrystal. Furthermore, there is no regularity of crystal orientation between different nanocrystals in the nc-OS. Thus, the orientation in the whole film is not observed. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor by some analysis methods. For example, when an nc-OS film is subjected to structural analysis by Out-of-plane XRD measurement with an XRD apparatus using θ/2θ scanning, a peak indicating crystallinity is not detected. Furthermore, a diffraction pattern like a halo pattern is observed when the nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than the diameter of a nanocrystal (e.g., larger than or equal to 50 nm). Meanwhile, in some cases, a plurality of spots in a ring-like region with a direct spot as the center are observed in a nanobeam electron diffraction pattern of the nc-OS film obtained using an electron beam with a probe diameter nearly equal to or smaller than the diameter of a nanocrystal (e.g., larger than or equal to 1 nm and smaller than or equal to 30 nm).

[a-Like OS]

The a-like OS is an oxide semiconductor having a structure between those of the nc-OS and the amorphous oxide semiconductor. The a-like OS contains a void or a low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS. Moreover, the a-like OS has higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.

<<Structure of Oxide Semiconductor>>

Next, the above-described CAC-OS is described in detail. Note that the CAC-OS relates to the material composition.

[CAC-OS]

The CAC-OS refers to one composition of a material in which elements constituting a metal oxide are unevenly distributed with a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size, for example. Note that a state in which one or more metal elements are unevenly distributed and regions including the metal element(s) are mixed with a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size in a metal oxide is hereinafter referred to as a mosaic pattern or a patch-like pattern.

In addition, the CAC-OS has a composition in which materials are separated into a first region and a second region to form a mosaic pattern, and the first regions are distributed in the film (this composition is hereinafter also referred to as a cloud-like composition). That is, the CAC-OS is a composite metal oxide having a composition in which the first regions and the second regions are mixed.

Here, the atomic ratios of In, Ga, and Zn to the metal elements contained in the CAC-OS in In—Ga—Zn oxide are denoted by [In], [Ga], and [Zn], respectively. For example, the first region in the CAC-OS in the In—Ga—Zn oxide has [In] higher than that in the composition of the CAC-OS. Moreover, the second region has [Ga] higher than that in the composition of the CAC-OS. For example, the first region has higher [In] and lower [Ga] than the second region. Moreover, the second region has higher [Ga] and lower [In] than the first region.

Specifically, the first region contains indium oxide, indium zinc oxide, or the like as its main component. The second region contains gallium oxide, gallium zinc oxide, or the like as its main component. That is, the first region can be referred to as a region containing In as its main component. The second region can be referred to as a region containing Ga as its main component.

Note that a clear boundary between the first region and the second region cannot be observed in some cases.

In a material composition of a CAC-OS in In—Ga—Zn oxide that contains In, Ga, Zn, and O, regions containing Ga as a main component are observed in part of the CAC-OS and regions containing In as a main component are observed in part thereof. These regions are randomly present to form a mosaic pattern. Thus, it is suggested that the CAC-OS has a structure in which metal elements are unevenly distributed.

The CAC-OS can be formed by a sputtering method under a condition where a substrate is not heated, for example. Moreover, in the case of forming the CAC-OS by a sputtering method, any one or more selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas are used for a deposition gas. The ratio of the flow rate of an oxygen gas to the total flow rate of the film formation gas at the time of film formation is preferably as low as possible, and for example, the ratio of the flow rate of an oxygen gas to the total flow rate of the film formation gas at the time of film formation is preferably higher than or equal to 0% and lower than 30%, further preferably higher than or equal to 0% and lower than or equal to 10%.

For example, energy dispersive X-ray spectroscopy (EDX) is used to obtain EDX mapping, and according to the EDX mapping, the CAC-OS in the In—Ga—Zn oxide has a structure in which the region containing In as its main component (the first region) and the region containing Ga as its main component (the second region) are unevenly distributed and mixed.

Here, the first region has higher conductivity than the second region. In other words, when carriers flow through the first region, the conductivity of a metal oxide is exhibited. Accordingly, when the first regions are distributed in a metal oxide like a cloud, high field-effect mobility (μ) can be achieved.

The second region has a higher insulating property than the first region. In other words, when the second regions are distributed in a metal oxide, leakage current can be inhibited.

Thus, in the case where a CAC-OS is used for a transistor, by the complementary action of the conductivity due to the first region and the insulating property due to the second region, the CAC-OS can have a switching function (On/Off function). That is, the CAC-OS has a conducting function in part of the material and has an insulating function in another part of the material; as a whole, the CAC-OS has a function of a semiconductor. Separation of the conducting function and the insulating function can maximize each function. Accordingly, when the CAC-OS is used for a transistor, high on-state current (Ion), high field-effect mobility (u), and excellent switching operation can be achieved.

A transistor using the CAC-OS has high reliability. Thus, the CAC-OS is the most suitable for a variety of semiconductor devices such as display devices.

An oxide semiconductor has various structures with different properties. Two or more kinds among the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the CAC-OS, the nc-OS, and the CAAC-OS may be included in an oxide semiconductor of one embodiment of the present invention.

Next, the case where the above oxide semiconductor is used for a transistor is described.

When the above oxide semiconductor is used for a transistor, a transistor with high field-effect mobility can be obtained. In addition, a transistor having high reliability can be obtained.

An oxide semiconductor having a low carrier concentration is preferably used in a transistor. For example, the carrier concentration of an oxide semiconductor is lower than or equal to 1×10¹⁷cm⁻³, preferably lower than or equal to 1×10¹⁵cm⁻³, further preferably lower than or equal to 1×10¹³cm⁻³, still further preferably lower than or equal to 1×10¹¹cm⁻³, yet further preferably lower than 1×10¹⁰cm⁻³, and higher than or equal to 1×10⁻⁹cm⁻³. In order to reduce the carrier concentration in an oxide semiconductor film, the impurity concentration in the oxide semiconductor film is reduced so that the density of defect states can be reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. Note that an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and thus has a low density of trap states in some cases.

Charge trapped by the trap states in the oxide semiconductor takes a long time to disappear and might behave like fixed charge. Thus, a transistor whose channel formation region is formed in an oxide semiconductor with a high density of trap states has unstable electrical characteristics in some cases.

Accordingly, in order to obtain stable electrical characteristics of a transistor, reducing the impurity concentration in an oxide semiconductor is effective. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable that the impurity concentration in an adjacent film also be reduced. Examples of impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon.

Here, the influence of each impurity in the oxide semiconductor is described.

When silicon or carbon, which is one of Group 14 elements, is contained in the oxide semiconductor, defect states are formed in the oxide semiconductor. Thus, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of an interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are each set lower than or equal to 2×10¹⁸atoms/cm³, preferably lower than or equal to 2×10¹⁷atoms/cm³.

When the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are formed and carriers are generated in some cases. Thus, a transistor using an oxide semiconductor that contains an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Thus, the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor, which is obtained by SIMS, is set lower than or equal to 1×10¹⁸atoms/cm³, preferably lower than or equal to 2×10¹⁶atoms/cm³.

Furthermore, when the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type by generation of electrons serving as carriers and an increase in carrier concentration. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. When nitrogen is contained in the oxide semiconductor, trap states are sometimes formed. This might make the electrical characteristics of the transistor unstable. Therefore, the concentration of nitrogen in the oxide semiconductor, which is obtained by SIMS, is set lower than 5×10¹⁹atoms/cm³, preferably lower than or equal to 5×10¹⁸atoms/cm³, further preferably lower than or equal to 1×10¹⁸atoms/cm³, still further preferably lower than or equal to 5×10¹⁷atoms/cm³.

Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus forms an oxygen vacancy in some cases. Entry of hydrogen into the oxygen vacancy generates an electron serving as a carrier in some cases. Furthermore, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier in some cases. Thus, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Accordingly, hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor, which is obtained by SIMS, is set lower than 1×10²⁰atoms/cm³, preferably lower than 1×10¹⁹atoms/cm³, further preferably lower than 5×10¹⁸atoms/cm³, still further preferably lower than 1×10¹⁸atoms/cm³.

When an oxide semiconductor with sufficiently reduced impurities is used for the channel formation region of the transistor, stable electrical characteristics can be given.

At least part of this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 7

In this embodiment, electronic devices of embodiments of the present invention is described with reference to FIG. 22 to FIG. 25.

An electronic device in this embodiment includes the display device of one embodiment of the present invention. Resolution, definition, and sizes of the display device of one embodiment of the present invention are easily increased. Thus, the display device of one embodiment of the present invention can be used for display portions of a variety of electronic devices.

The display device of one embodiment of the present invention can be fabricated at low cost, which leads to a reduction in manufacturing cost of an electronic device.

Examples of electronic devices include a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, and an audio reproducing device in addition to electronic devices with a relatively large screen, such as a television device, a desktop or notebook personal computer, a monitor of a computer or the like, digital signage, and a large game machine like a pachinko machine.

In particular, the display device of one embodiment of the present invention can have a high resolution, and thus can be suitably used for an electronic device having a relatively small display portion. As such an electronic device, a watch-type or bracelet-type information terminal (wearable device); and a wearable device worn on a head, such as a device for VR such as a head-mounted display and a glasses-type device for AR can be given, for example. Examples of wearable devices include a device for SR and a device for MR.

The definition of the display device of one embodiment of the present invention is preferably as high as HD (number of pixels: 1280×720), FHD (number of pixels: 1920×1080), WQHD (number of pixels: 2560×1440), WQXGA (number of pixels: 2560×1600), 4K2K (number of pixels: 3840×2160), or 8K4K (number of pixels: 7680×4320). In particular, definition of 4K2K, 8K4K, or higher is preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably higher than or equal to 300 ppi, further preferably higher than or equal to 500 ppi, still further preferably higher than or equal to 1000 ppi, still further preferably higher than or equal to 2000 ppi, still further preferably higher than or equal to 3000 ppi, still further preferably higher than or equal to 5000 ppi, yet further preferably higher than or equal to 7000 ppi. With such a display device with high definition and high resolution, the electronic device can have higher realistic sensation, sense of depth, and the like in personal use such as portable use and home use.

The electronic device in this embodiment can be incorporated along a curved surface of an inside wall or an outside wall of a house or a building or the interior or the exterior of a car.

The electronic device in this embodiment may include an antenna. With the antenna receiving a signal, a video, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

The electronic device in this embodiment may include a sensor (a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, a chemical substance, sound, time, hardness, an electric field, current, voltage, electric power, radiation, a flow rate, humidity, gradient, oscillation, a smell, or infrared rays).

The electronic device in this embodiment can have a variety of functions. For example, the electronic device can have a function of displaying a variety of information (a still image, a moving image, a text image, and the like) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of executing a variety of software (programs), a wireless communication function, and a function of reading out a program or data stored in a recording medium.

An electronic device 6500 illustrated in FIG. 22A is a portable information terminal that can be used as a smartphone.

The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, buttons 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

The display device of one embodiment of the present invention can be used in the display portion 6502.

FIG. 22B is a schematic cross-sectional view including an end portion of the housing 6501 on the microphone 6506 side.

A protection member 6510 having a light-transmitting property is provided on a display surface side of the housing 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, and the like are provided in a space surrounded by the housing 6501 and the protection member 6510.

The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protection member 6510 with an adhesive layer (not illustrated).

Part of the display panel 6511 is folded back in a region outside the display portion 6502, and an FPC 6515 is connected to the part that is folded back. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on the printed circuit board 6517.

A flexible display of one embodiment of the present invention can be used as the display panel 6511. Thus, an extremely lightweight electronic device can be achieved. Since the display panel 6511 is extremely thin, the battery 6518 with high capacity can be mounted while the thickness of the electronic device is controlled. Moreover, part of the display panel 6511 is folded back so that a connection portion with the FPC 6515 is provided on the back side of the pixel portion, whereby an electronic device with a narrow bezel can be achieved.

FIG. 23A illustrates an example of a television device. In a television device 7100, a display portion 7000 is incorporated in a housing 7101. Here, the housing 7101 is supported by a stand 7103.

The display device of one embodiment of the present invention can be used for the display portion 7000.

Operation of the television device 7100 illustrated in FIG. 23A can be performed with an operation switch provided in the housing 7101 and a separate remote controller 7111. Alternatively, the display portion 7000 may include a touch sensor, and the television device 7100 may be operated by touch on the display portion 7000 with a finger or the like. The remote controller 7111 may be provided with a display portion for displaying information output from the remote controller 7111. With operation keys or a touch panel provided in the remote controller 7111, channels and volume can be operated and videos displayed on the display portion 7000 can be operated.

Note that the television device 7100 has a structure in which a receiver, a modem, and the like are provided. A general television broadcast can be received with the receiver. When the television device is connected to a communication network with or without wires via the modem, one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver or between receivers, for example) information communication can be performed.

FIG. 23B illustrates an example of a laptop personal computer. A laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. In the housing 7211, the display portion 7000 is incorporated.

The display device of one embodiment of the present invention can be used for the display portion 7000.

FIG. 23C and FIG. 23D illustrate examples of digital signage.

Digital signage 7300 illustrated in FIG. 23C includes a housing 7301, the display portion 7000, a speaker 7303, and the like. The digital signage 7300 can also include an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, a variety of sensors, a microphone, and the like.

FIG. 23D illustrates digital signage 7400 mounted on a cylindrical pillar 7401. The digital signage 7400 includes the display portion 7000 provided along a curved surface of the pillar 7401.

The display device of one embodiment of the present invention can be used in the display portion 7000 in each of FIG. 23C and FIG. 23D.

A larger area of the display portion 7000 can increase the amount of information that can be provided at a time. The larger display portion 7000 attracts more attention, so that the effectiveness of the advertisement can be increased, for example.

The use of a touch panel in the display portion 7000 is preferable because in addition to display of a still image or a moving image on the display portion 7000, intuitive operation by a user is possible. Moreover, for an application for providing information such as route information or traffic information, usability can be enhanced by intuitive operation.

As illustrated in FIG. 23C and FIG. 23D, it is preferable that the digital signage 7300 or the digital signage 7400 be capable of working with an information terminal 7311 or an information terminal 7411 such as a smartphone a user has through wireless communication. For example, information of an advertisement displayed on the display portion 7000 can be displayed on a screen of the information terminal 7311 or the information terminal 7411. By operation of the information terminal 7311 or the information terminal 7411, display on the display portion 7000 can be switched.

It is possible to make the digital signage 7300 or the digital signage 7400 execute a game with use of the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). Thus, an unspecified number of users can join in and enjoy the game concurrently.

FIG. 24A is an external view of a camera 8000 to which a finder 8100 is attached.

The camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, and the like. Furthermore, a detachable lens 8006 is attached to the camera 8000. Note that the lens 8006 and the housing may be integrated with each other in the camera 8000.

Images can be taken with the camera 8000 at the press of the shutter button 8004 or the touch of the display portion 8002 serving as a touch panel.

The housing 8001 includes a mount including an electrode, so that the finder 8100, a stroboscope, or the like can be connected to the housing.

The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

The housing 8101 is attached to the camera 8000 by a mount for engagement with the mount of the camera 8000. The finder 8100 can display a video received from the camera 8000 and the like on the display portion 8102.

The button 8103 functions as a power button or the like.

The display device of one embodiment of the present invention can be used in the display portion 8002 of the camera 8000 and the display portion 8102 of the finder 8100. Note that a finder may be incorporated in the camera 8000.

FIG. 24B is an external view of a head-mounted display 8200.

The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. A battery 8206 is incorporated in the mounting portion 8201.

The cable 8205 supplies electric power from the battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like to receive video information and display it on the display portion 8204. The main body 8203 includes a camera, and information on the movement of the eyeballs or the eyelids of the user can be used as an input means.

The mounting portion 8201 may include a plurality of electrodes capable of sensing current flowing accompanying with the movement of the user's eyeball at a position in contact with the user to recognize the user's sight line. The mounting portion 8201 may also have a function of monitoring the user's pulse with use of current flowing through the electrodes. The mounting portion 8201 may include a variety of sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor to have a function of displaying the user's biological information on the display portion 8204, a function of changing a video displayed on the display portion 8204 in accordance with the movement of the user's head, and the like.

The display device of one embodiment of the present invention can be used in the display portion 8204.

FIG. 24C to FIG. 24E are diagrams illustrating the appearance of a head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display portion 8302, a band-like fixing member 8304, and a pair of lenses 8305.

A user can see display on the display portion 8302 through the lenses 8305. The display portion 8302 is preferably curved so that the user can feel high realistic sensation. Another image displayed on another region of the display portion 8302 is viewed through the lenses 8305, so that three-dimensional display using parallax or the like can be performed. Note that the structure is not limited to the structure in which one display portion 8302 is provided; two display portions 8302 may be provided and one display portion may be provided per eye of the user.

The display device of one embodiment of the present invention can be used for the display portion 8302. The display device of one embodiment of the present invention achieves an extremely high resolution. For example, a pixel is not easily seen by the user even when the user sees display that is magnified by the use of the lenses 8305 as illustrated in FIG. 24E. In other words, a video with a strong sense of reality can be seen by the user with use of the display portion 8302.

FIG. 24F is an external view of a goggles-type head-mounted display 8400. The head-mounted display 8400 includes a pair of housings 8401, a mounting portion 8402, and a cushion 8403. A display portion 8404 and a lens 8405 are provided in each of the pair of housings 8401. Furthermore, when the pair of display portions 8404 display different images, three-dimensional display using parallax can be performed.

A user can see display on the display portion 8404 through the lens 8405. The lens 8405 has a focus adjustment mechanism, and the focus adjustment mechanism can adjust the position of the lens 8405 according to the user's eyesight. The display portion 8404 is preferably a square or a horizontal rectangle. This can improve a realistic sensation.

The mounting portion 8402 preferably has flexibility and elasticity so as to be adjusted to fit the size of the user's face and not to slide down. In addition, part of the mounting portion 8402 preferably has a vibration mechanism functioning as a bone conduction earphone. Thus, audio devices such as an earphone and a speaker are not necessarily provided separately, and the user can enjoy videos and sounds only when wearing the head-mounted display 8400. Note that the housing 8401 may have a function of outputting sound data by wireless communication.

The mounting portion 8402 and the cushion 8403 are portions in contact with the user's face (forehead, cheek, or the like). The cushion 8403 is in close contact with the user's face, so that light leakage can be prevented, which increases the sense of immersion. The cushion 8403 is preferably formed using a soft material so that the head-mounted display 8400 is in close contact with the user's face when being worn by the user. For example, a material such as rubber, silicone rubber, urethane, or sponge can be used. Furthermore, when a sponge or the like whose surface is covered with cloth, leather (natural leather or synthetic leather), or the like is used, a gap is unlikely to be generated between the user's face and the cushion 8403, whereby light leakage can be suitably prevented. Furthermore, using such a material is preferable because it has a soft texture and the user does not feel cold when wearing the device in a cold season, for example. The member in contact with user's skin, such as the cushion 8403 or the mounting portion 8402, is preferably detachable in order to easily perform cleaning or replacement.

Electronic devices illustrated in FIG. 25A to FIG. 25F include a housing 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, a chemical substance, sound, time, hardness, an electric field, current, voltage, electric power, radiation, a flow rate, humidity, gradient, oscillation, a smell, or infrared rays), a microphone 9008, and the like.

The electronic devices illustrated in FIG. 25A to FIG. 25F have a variety of functions. For example, the electronic device can have a function of displaying a variety of information (a still image, a moving image, a text image, and the like) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of controlling processing with the use of a variety of software (programs), a wireless communication function, and a function of reading out and processing a program or data stored in a recording medium. Note that the functions of the electronic devices are not limited thereto, and the electronic devices can have a variety of functions. The electronic devices may include a plurality of display portions. The electronic devices may each be provided with a camera or the like and have a function of taking a still image or a moving image, a function of storing the taken image in a storage medium (an external storage medium or a storage medium incorporated in the camera), a function of displaying the taken image on the display portion, or the like.

The display device of one embodiment of the present invention can be used for the display portion 9001.

The electronic devices illustrated in FIG. 25A to FIG. 25F will be described in detail below.

FIG. 25A is a perspective view illustrating a portable information terminal 9101. The portable information terminal 9101 can be used as a smartphone, for example. Note that the portable information terminal 9101 may include the speaker 9003, the connection terminal 9006, the sensor 9007, or the like. The portable information terminal 9101 can display characters and image information on its plurality of surfaces. FIG. 25A illustrates an example in which three icons 9050 are displayed. Furthermore, information 9051 indicated by dashed rectangles can be displayed on another surface of the display portion 9001. Examples of the information 9051 include notification of reception of an e-mail, an SNS, or an incoming call, the title and sender of an e-mail, an SNS, or the like, the date, the time, remaining battery, and the reception strength of an antenna. Alternatively, the icon 9050 or the like may be displayed at the position where the information 9051 is displayed.

FIG. 25B is a perspective view illustrating a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, an example is illustrated in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user of the portable information terminal 9102 can check the information 9053 displayed such that it can be seen from above the portable information terminal 9102, with the portable information terminal 9102 put in a breast pocket of his/her clothes. The user can see the display without taking out the portable information terminal 9102 from the pocket and decide whether to answer the call, for example.

FIG. 25C is a perspective view illustrating a watch-type portable information terminal 9200. For example, the portable information terminal 9200 can be used as a Smartwatch (registered trademark). The display surface of the display portion 9001 is curved, and an image can be displayed on the curved display surface. Furthermore, intercommunication between the portable information terminal 9200 and, for example, a headset capable of wireless communication enables hands-free calling. With the connection terminal 9006, the portable information terminal 9200 can perform mutual data transmission with another information terminal and charging. Note that the charging operation may be performed by wireless power feeding.

FIG. 25D to FIG. 25F are perspective views illustrating a foldable portable information terminal 9201. FIG. 25D is a perspective view of an opened state of the portable information terminal 9201, FIG. 25F is a perspective view of a folded state thereof, and FIG. 25E is a perspective view of a state in the middle of change from one of FIG. 25D and FIG. 25F to the other. The portable information terminal 9201 is highly portable when folded. When the portable information terminal 9201 is opened, a seamless large display region is highly browsable. The display portion 9001 of the portable information terminal 9201 is supported by three housings 9000 joined together by hinges 9055. The display portion 9001 can be folded with a radius of curvature greater than or equal to 0.1 mm and less than or equal to 150 mm, for example.

At least part of the structure examples, the drawings corresponding thereto, and the like described in this embodiment as an example can be combined with the other structure examples, the other drawings, and the like as appropriate.

Example 1

In this example, display panels of one embodiment of the present invention were fabricated.

[Display Panel Fabrication 1]

A panel S1 was fabricated as a display panel. Fabrication of the panel S1 was performed by the method described in Manufacturing method example 1 in Embodiment 1. Specifically, first, a substrate provided with a pixel circuit including a transistor, a wiring, and the like on a single crystal silicon substrate and a pixel electrode was prepared. Next, after an EL layer of red color, an EL layer of green color, and an EL layer of blue color were formed in this order, insulating layers protecting side surfaces of the EL layers were formed. Subsequently, sacrificial layers and protective layers over the EL layers were removed. Then, an electron-injection layer, a common electrode, and a protective layer were formed in this order over the EL layers.

The single crystal silicon substrate was used as the substrate, and a single crystal silicon transistor, a wiring layer, an oxide semiconductor transistor (an OS transistor), and a light-emitting element were stacked in this order. For the OS transistor, an In—Ga—Zn oxide film (IGZO) was used as a semiconductor layer.

The EL layer was formed to have a stacked-layer structure including a hole-injection layer, a hole-transport layer, a light-emitting layer, and an electron-transport layer. As the sacrificial layer, an aluminum oxide film formed by an ALD method at a substrate temperature of 80° C. and a tungsten film formed by a sputtering method were used. As an insulating layer protecting a sidewall of the EL layer, an aluminum oxide film formed by an ALD method and a photosensitive resin were used. A stacked film of a lithium fluoride film and an ytterbium film was used as the electron-injection layer, a mixed film of silver and magnesium was used as the common electrode, and an ITO film formed by a sputtering method was used as the protective layer over the common electrode.

In the panel S1, the display portion has a size of a square with a diagonal of 0.99 inches, the number of effective pixels is 1920×1920, the resolution is 2731 ppi, the pixel pitches are 9.3 μm in the vertical direction and 9.3 μm in the horizontal direction, the pixel arrangement is a stripe arrangement of R, G, and B, the aperture ratio is 43% (designed value), and the frame frequency is 90 Hz.

[Display Panel Fabrication 2]

Next, a panel S2 was fabricated as a display panel. For the panel S2, a white OLED and a color filter were used, a single crystal silicon transistor was used in a driver circuit, an OS transistor formed over the single crystal S1 transistor was used in a pixel circuit. For the structure of the panel S2, Embodiment 4 was referred to. In the panel S2, the display portion has a size of a square with a diagonal of 0.66 inches, the number of effective pixels is 1440×1440, the resolution is 3079 ppi, the pixel pitches are 8.3 μm in the vertical direction and 8.3 μm in the horizontal direction, the pixel arrangement is a stripe arrangement of R, G, and B, the aperture ratio is 34% (designed value), and the frame frequency is 90 Hz.

[Display Result]

FIG. 26A shows a photograph of display on the panel S1 and FIG. 26B shows a photograph of display on the panel S2.

[Luminance Measurement]

The in-plane distributions of the luminance of green display (G) by the fabricated display panels were measured at wavelengths of 458 nm (blue), 531 nm (green), and 623 nm (red). For comparison, evaluations were performed in a similar manner on two kinds of display panels (Comparative example 1 and Comparative example 2) using single crystal silicon transistor for a pixel circuit and a white OLED for a light-emitting element and a color filter.