num="0000">

where t_{Y_bottom}represents a high-voltage bridge alternating current inflow conduction width, t_{Y_top}represents a high-voltage bridge alternating current outflow conduction width, t_{D_bottom}represents a low-voltage bridge alternating current inflow conduction width, t_{D_top}represents a low-voltage bridge alternating current outflow conduction width, t_YHV1, t_YHV3, and t_YHV5represent time widths of a high-voltage bridge common anode valve conduction state, t_YHV2, t_YHV4, and t_YHV6represent time widths of a high-voltage bridge common cathode valve conduction state, t_DHV1, t_DHV3, and t_DHV5represent time widths of a low-voltage bridge common anode valve conduction state, and t_DHV2, t_DHV4, and t_DHV6represent time widths of a low-voltage bridge common cathode valve conduction state.

The constructing a direct current conduction width according to a direct-current high-voltage current amplitude and a direct-current neutral current amplitude specifically includes:

- defining a flow state of a direct-current high-voltage current and a flow state of a direct-current neutral current according to the direct-current high-voltage current amplitude and the direct-current neutral current amplitude based on the following formulas:

$S_{dH} = {\begin{matrix} 1; i_{dH} \geq i_{set} \\ 0; i_{dH} < i_{set} \end{matrix}; S_{dN} = {\begin{matrix} 1; i_{dN} \geq i_{set} \\ 0; i_{dN} < i_{set} \end{matrix}$

- where S_dHrepresents the flow state of the direct-current high-voltage current, S_dNrepresents the flow state of the direct-current neutral current, and i_setrepresents a threshold of a direct current flow state; and
- integrating the flow state of the direct-current high-voltage current and the flow state of the direct-current neutral current in each power frequency cycle to obtain a direct current conduction width based on the following formulas:

$t_{dH} = \int_{t - T}^{t} S_{dH} dt; t_{dN} = \int_{t - T}^{t} S_{dN} dt$

- where t_dHrepresents a direct current inflow conduction width, and t_dNrepresents a direct current outflow conduction width.

Further, the horizontal and vertical timing features are constructed on the circuit structure of the converter according to the alternating current conduction width and the direct current conduction width based on the following formulas:

${\begin{matrix} t_{DCVTF} = t_{dH} - t_{dN} \\ t_{ACVTF_HB} = t_{Y_top} - t_{Y_{_bottom}} \\ t_{ACVTF_LB} = t_{D_top} - t_{D_{_bottom}} \\ t_{ACVTF_HLB} = t_{Y_bottom} - t_{D_top} \end{matrix}; {\begin{matrix} t_{THTF_HB} = t_{dH} - t_{Y_top} \\ t_{THTF_LB} = t_{dH} - t_{D_{_top}} \\ t_{BHTF_HB} = t_{dN} - t_{Y_{_bottom}} \\ t_{BHTF_LB} = t_{dN} - t_{D_bottom} \end{matrix}$

- where t_DCVTFrepresents a direct-current vertical timing feature, t_{ACVTF_HB}represents a high-voltage bridge vertical timing feature, t_{ACVTF_LB}represents a low-voltage bridge vertical timing feature, t_{ACVTF_HLB}represents a double-bridge vertical timing feature, t_{THTF_HB}represents a high-voltage bridge top horizontal timing feature, t_{THTF_LB}represents a low-voltage bridge top horizontal timing feature, t_{BHTF_HB}represents a high-voltage bridge bottom horizontal timing feature, and t_{BHTF_LB}represents a low-voltage bridge bottom horizontal timing feature.

Further, the implementing valve-level fault location for the converter according to the time width of each valve conduction state, the alternating current conduction width, the direct current conduction width, the horizontal and vertical timing features, each valve state signal, and the current data specifically includes:

- determining whether the direct current inflow conduction width is less than the power frequency cycle;
- determining that a fault is a line fault k9 if the direct current inflow conduction width is less than the power frequency cycle;
- determining whether the direct-current vertical timing feature satisfies t_dH−t_dN>Δ if the direct current inflow conduction width is greater than or equal to the power frequency cycle, where Δ represents a value greater than 0;
- determining whether the high-voltage bridge vertical timing feature satisfies t_{Y_top}≠t_{Y_bottom}or whether the low-voltage bridge vertical timing feature satisfies t_{D_top}≠t_{D_bottom}if the direct-current vertical timing feature satisfies t_dH−t_dN>Δ;
- determining that the fault is an external fault k7 if the high-voltage bridge vertical timing feature satisfies t_{Y_top}≠t_{Y_bottom}or the low-voltage bridge vertical timing feature satisfies t_{D_top}≠t_{D_bottom};
- determining that the faults are internal fault k4 and k5 if the high-voltage bridge vertical timing feature does not satisfy t_{Y_top}≠t_{Y_bottom}or the low-voltage bridge vertical timing feature does not satisfy t_{D_top}≠t_{D_bottom};
- determining whether the valve state signal is abnormal according to each valve state signal if the direct-current vertical timing feature does not satisfy t_dH−t_dN>Δ;
- determining, if the valve state signal is abnormal, whether three conditions are simultaneously satisfied: a maximum value of the direct-current high-voltage current and the direct-current neutral current is greater than a maximum value of the three-phase alternating currents of the j bridge, commutation fails, and there is no difference in high-voltage bridge or low-voltage bridge top horizontal timing features, if yes, determining that the faults are external faults k6 and k8, and if no, determining that the faults are internal faults k1, k2, and k3; and
- returning to collecting current data of a converter if the valve state signal is not abnormal.

Further, the method further includes:

- further locating the internal faults to implement fault valve and fault phase location, specifically:
- determining each internal fault type using data of the horizontal and vertical timing features in a time window width according to internal faults k1-k5, and obtaining internal fault types of k1, k3, and k5 which are successfully determined; and
- implementing fault valve and fault phase location using data of the time width of each valve conduction state in a converter bridge where the internal fault types of k1, k3, and k5 are located in the time window width.

The second object of the present disclosure may be achieved by adopting the following technical solution.

The valve-level fault location system for converters based on horizontal and vertical state differences of valves includes:

- a collection unit, configured to collect current data of a converter, the current data including three-phase alternating currents of a j bridge, a direct-current high-voltage current, and a direct-current neutral current, where j=Y/D, Y representing a high voltage, and D representing a low voltage;
- a calculation unit, configured to calculate a time width of each valve conduction state, an alternating current conduction width, and a direct current conduction width based on the current data;
- a construction unit, configured to construct horizontal and vertical timing features on a circuit structure of the converter according to the alternating current conduction width and the direct current conduction width;
- a comparison unit, configured to compare the time width of each valve conduction state with a time width of a normal valve conduction state, and output each valve state signal; and
- a fault location unit, configured to implement valve-level fault location for the converter according to the time width of each valve conduction state, the alternating current conduction width, the direct current conduction width, the horizontal and vertical timing features, each valve state signal, and the current data.

The third object of the present disclosure may be achieved by adopting the following technical solution.

The computing device includes a processor and a memory for storing a program executable by the processor. The processor, when executing the program stored in the memory, implements the foregoing valve-level fault location method for converters.

The fourth object of the present disclosure may be achieved by adopting the following technical solution.

The storage medium stores a program. The program, when executed by a processor, implements the foregoing valve-level fault location method for converters.

The present disclosure has the following beneficial effects in contrast to the related art.

According to the present disclosure, by constructing a difference between horizontal and vertical conduction widths of an alternating current and a direct current based on current timing features, valve-level faults of converters can be accurately located. In the meantime, according to the present disclosure, fault valves and fault phases of internal faults as well as external faults and line faults can be located without loss of generality. In addition, the method of the present disclosure can monitor the converter without using additional current measuring point equipment, thereby not only saving equipment cost but also having small limitations in engineering application.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure or the related art, the drawings required to describe the embodiments or the related art will be briefly introduced below. Apparently, the drawings described below are merely some embodiments of the present disclosure, and those of ordinary skill in the art may obtain other drawings according to structures shown in these drawings without inventive effort.

FIG. 1 is a flowchart of a valve-level fault location method for converters according to Embodiment 1 of the present disclosure;

FIG. 2 is a distribution diagram of 9 faults and acquired current data of a converter and a neighbor area thereof according to Embodiment 1 of the present disclosure;

FIG. 3 is a diagram of a relationship between conduction width types and horizontal and vertical timing features according to Embodiment 1 of the present disclosure;

FIG. 4 is a flowchart of fault area location according to Embodiment 1 of the present disclosure;

FIG. 5 is a schematic diagram of a time window width for fault location according to Embodiment 1 of the present disclosure;

FIG. 6 is a flowchart of location of each internal fault type of a converter according to embodiment 1 of the present disclosure;

FIG. 7 is a flowchart of location of a fault valve in a fault type k1 according to Embodiment 1 of the present disclosure;

FIG. 8 is a flowchart of location of a fault phase in a fault type k3 according to Embodiment 1 of the present disclosure;

FIG. 9 is a flowchart of location of a fault phase in a fault type k5 according to Embodiment 1 of the present disclosure;

FIG. 10 is a flowchart of a valve-level fault location system for converters according to Embodiment 2 of the present disclosure; and

FIG. 11 is a structural block diagram of a computer device according to Embodiment 3 of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Apparently, the described embodiments are merely some embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without inventive effort should fall within the scope of the present disclosure.

Embodiment 1

In traditional high-voltage direct current transmission projects, 12-pulse bridge converters are mostly used. An inverter side covers all fault types at a rectifier side. In addition, there is a special problem at the inverter side, namely, the problem of commutation failure. In this embodiment, in order not to lose generality, the inverter side is taken as a research object.

As shown in FIG. 1, this embodiment provides a valve-level fault location method for converters based on horizontal and vertical state differences of valves. The method includes the following steps.

At S101, current data of a converter is collected.

As shown in FIG. 2, in this embodiment, currents i_Ya, i_Yb, and i_Ycmeasured by a converter high-voltage bridge alternating-current three-phase current transformer CT_I_acYand currents i_Da, i_Db, and i_Dcmeasured by a converter low-voltage bridge alternating-current three-phase current transformer CT_I_acDin a high-voltage direct current transmission system (LCC-HVDC) at an inverter side of a direct current engineering model are collected. In this embodiment, a direct current i_dHmeasured by a converter direct-current high-voltage direct current transformer CT_I_dHand a direct current i_dNmeasured by a converter direct-current neutral direct current transformer CT_I_dNare collected.

In this embodiment, i_Ya, i_Yb, i_Yc, i_Da, i_Dband i_Dcare all represented by i_ja, i_jb, and i_jc, and are collectively referred to as three-phase alternating currents of a j bridge, where j=Y/D, Y represents a high voltage, and D represents a low voltage. A converter direct-current high-voltage current is i_dH, and a converter direct-current neutral current is i_dN.

The current data in this embodiment includes the three-phase alternating currents of the j bridge, a direct-current high-voltage current, and a direct-current neutral current.

At S102, a time width of each valve conduction state, an alternating current conduction width, and a direct current conduction width are calculated based on the current data.

At S1021, a plurality of valve currents of the j bridge and a valve current base value of the j bridge are calculated according to absolute values of the three-phase alternating currents of the j bridge.

- (1) Absolute values of the three-phase alternating currents of the j bridge are obtained.
- (2) The plurality of valve currents of the j bridge are calculated according to the absolute values of the three-phase alternating currents of the j bridge based on the following formulas:

$\begin{matrix} i_{jV 4} = {\begin{matrix} i_{ja}; i_{ja} > 0 \\ 0; i_{ja} \leq 0 \end{matrix} \\ i_{jV 1} = {\begin{matrix} - i_{ja}; i_{ja} < 0 \\ 0; i_{ja} \geq 0 \end{matrix} \end{matrix} ❘ \begin{matrix} i_{jV 6} = {\begin{matrix} i_{jb}; i_{jb} > 0 \\ 0; i_{jb} \leq 0 \end{matrix} \\ i_{jV 3} = {\begin{matrix} - i_{jb}; i_{jb} < 0 \\ 0; i_{jb} \geq 0 \end{matrix} \end{matrix} ❘ \begin{matrix} i_{jV 2} = {\begin{matrix} i_{jc}; i_{jc} > 0 \\ 0; i_{jc} \leq 0 \end{matrix} \\ i_{jV 5} = {\begin{matrix} - i_{jc}; i_{jc} < 0 \\ 0; i_{jc} \geq 0 \end{matrix} \end{matrix}$

- where j=Y/D, i_jV1represents a j-bridge V1 valve current, i_jV2represents a j-bridge V2 valve current, i_jV3represents a j-bridge V3 valve current, i_jV4represents a j-bridge V4 valve current, i_jV5represents a j-bridge V5 valve current, and i_jV6represents a j-bridge V6 valve current.

In this embodiment, twelve valve currents, which are respectively a high-voltage bridge V1 valve current, a high-voltage bridge V2 valve current, a high-voltage bridge V3 valve current, a high-voltage bridge V4 valve current, a high-voltage bridge V5 valve current, a high-voltage bridge V6 valve current, a low-voltage bridge V1 valve current, a low-voltage bridge V2 valve current, a low-voltage bridge V3 valve current, a low-voltage bridge V4 valve current, a low-voltage bridge V5 valve current, and a low-voltage bridge V6 valve current, are obtained.

- (3) The calculating a valve current base value of the j bridge according to absolute values of the three-phase alternating currents of the j bridge specifically includes: selecting half of a maximum value in the absolute values of the three-phase alternating currents of the j bridge as a valve current base value i_jbaseof the j bridge.

In this embodiment, half of a maximum value of absolute values of three-phase alternating currents of a high-voltage bridge is selected as a valve current base value i_Ybaseof the high-voltage bridge, and half of a maximum value of absolute values of three-phase alternating currents of a low-voltage bridge is selected as a valve current base value i_Dbaseof the low-voltage bridge.

At S1022, a ratio of one of the valve currents to the valve current base value is selected as a valve current relative relationship, so as to obtain a plurality of valve current relative relationships.

The formulas of step S1022 and step S1021 (3) in this embodiment are as follows:

${\begin{matrix} S_{jVm} = \frac{i_{jVm}}{i_{jbase}} \\ i_{jbase} = \frac{\max (❘ i_{ja} ❘, ❘ i_{jb} ❘, ❘ i_{jc} ❘)}{2} \end{matrix}$

- where j=Y/D, m=1, 2, 3, 4, 5, 6, S_jVmrepresents a j-bridge Vm valve current relative relationship, i_jbaserepresents a j-bridge valve current base value, |i_ja|, |i_jb|, and |i_jc| represent the absolute values of the three-phase alternating currents of the j bridge, and Max(|i_ja|,|i_jb|,|i_jc|) represents the maximum value of the absolute values of the three-phase alternating currents of the j bridge.

Twelve valve current relative relationships are obtained in this embodiment.

At S1023, a plurality of valve conduction states are obtained according to each valve current relative relationship, and each valve conduction state is integrated to obtain a time width of each valve conduction state.

- (1) Each valve current relative relationship S_jVmis input into a single-phase comparator, and a duty ratio of each valve current is obtained.
- (2) A state in which the duty ratio of the valve current is greater than 1 is selected as a valve conduction state S_jHVm, so as to obtain a plurality of valve conduction states.

$S_{jHVm} = 1; S_{jVm} > 1$

- where j=Y/D, m=1, 2, 3, 4, 5, 6, and S_jHVmrepresents a j-bridge Vm valve conduction state.
- (3) In each power frequency cycle, each valve conduction state S_jHVmis integrated to obtain a time width t_jHVmof each valve conduction state based on the following formula:

$t_{jHVm} = \int_{- T}^{0} S_{jHVm} dt$

- where j=Y/D, m=1, 2, 3, 4, 5, 6, t_jHVmrepresents a time width of the j-bridge Vm valve conduction state, and T represents a time width of a power frequency cycle.

At S1024, the alternating current conduction width is constructed according to the time width of each valve conduction state.

High-voltage and low-voltage bridge alternating current outflow conduction widths are constructed according to time widths of high-voltage bridge and low-voltage bridge common cathode valve conduction states, and high-voltage and low-voltage bridge alternating current inflow conduction widths are constructed according to time widths of high-voltage and low-voltage bridge common anode valve conduction states.

${\begin{matrix} t_{Y_{_bottom}} = t_{YHV 1} + t_{YHV 3} + t_{YHV 5} \\ t_{Y_top} = t_{YHV 2} + t_{YHV 4} + t_{YHV 6} \end{matrix}; {\begin{matrix} t_{D_{_bottom}} = t_{DHV 1} + t_{DHV 3} + t_{DHV 5} \\ t_{D_top} = t_{DHV 2} + t_{DHV 4} + t_{DHV 6} \end{matrix}$

- where t_{Y_bottom}represents the high-voltage bridge alternating current inflow conduction width, t_{Y_top}represents the high-voltage bridge alternating current outflow conduction width, t_{D_bottom}represents the low-voltage bridge alternating current inflow conduction width, t_{D_top}represents the low-voltage bridge alternating current outflow conduction width, t_YHV1, t_YHV3, and t_YHV5represent the time widths of the high-voltage bridge common anode valve conduction state, t_YHV2, t_YHV4, and t_YHV6represent the time widths of the high-voltage bridge common cathode valve conduction state, t_DHV1, t_DHV3, and t_DHV5represent the time widths of the low-voltage bridge common anode valve conduction state, and t_DHV2, t_DHV4, and t_DHV6represent the time widths of the low-voltage bridge common cathode valve conduction state.

In this embodiment, the high-voltage bridge alternating current inflow conduction width and the high-voltage bridge alternating current outflow conduction width are collectively referred to as a high-voltage bridge alternating current conduction width, and the low-voltage bridge alternating current inflow conduction width and the low-voltage bridge alternating current outflow conduction width are collectively referred to as a low-voltage bridge alternating current conduction width.

In this embodiment, the alternating current conduction width includes a high-voltage bridge alternating current conduction width and a low-voltage bridge alternating current conduction width.

At S1025, the direct current conduction width is constructed according to a direct-current high-voltage current amplitude and a direct-current neutral current amplitude.

- (1) The direct-current high-voltage current being greater than i_setis defined as a flow state S_dHof the direct-current high-voltage current, and the direct-current neutral current being greater than i_setis defined as a flow state S_dNof the direct-current neutral current, based on the following formulas:

$S_{dH} = {\begin{matrix} 1; i_{dH} \geq i_{set} \\ 0; i_{dH} < i_{set} \end{matrix}; S_{dN} = {\begin{matrix} 1; i_{dN} \geq i_{set} \\ 0; i_{dN} < i_{set} \end{matrix}$

- where S_dHrepresents the flow state of the direct-current high-voltage current, S_dNrepresents the flow state of the direct-current neutral current, and i_setrepresents a threshold of a direct current flow state.
- (2) Conduction widths of the flow state S_dHof the direct-current high-voltage current and the flow state S_dNof the direct-current neutral current in each power frequency cycle are obtained through an integrator, based on the following formulas:

$t_{dH} = \int_{t - T}^{t} S_{dH} dt; t_{dN} = \int_{t - T}^{t} S_{dN} dt$

- where t_dHrepresents a direct current inflow conduction width, and t_dNrepresents a direct current outflow conduction width.

In this embodiment, the direct current inflow conduction width and the direct current outflow conduction width are collectively referred to as the direct current conduction width.

In this embodiment, the alternating and direct current conduction widths include the alternating current conduction width and the direct current conduction width.

At S103, horizontal and vertical timing features are constructed on a circuit structure of the converter according to the alternating current conduction width and the direct current conduction width.

In this embodiment, the horizontal and vertical timing features are constructed specifically as follows.

As shown in FIG. 3, a, a relationship between the direct current inflow conduction width and the direct current outflow conduction width is defined as a direct-current vertical timing feature; b, a relationship between the high-voltage bridge alternating current outflow conduction width and the high-voltage bridge alternating current inflow conduction width is defined as a high-voltage bridge vertical timing feature; c, a relationship between the low-voltage bridge alternating current outflow conduction width and the low-voltage bridge alternating current inflow conduction width is defined as a low-voltage bridge vertical timing feature; d, a relationship between the high-voltage bridge alternating current inflow conduction width and the low-voltage bridge alternating current outflow conduction width is defined as a double-bridge vertical timing feature; e, a relationship between the direct current inflow conduction width and the high-voltage bridge alternating current outflow conduction width is defined as a high-voltage bridge top horizontal timing feature; f, a relationship between the direct current inflow conduction width and the low-voltage bridge alternating current outflow conduction width is defined as a low-voltage bridge top horizontal timing feature; g, a relationship between the high-voltage bridge alternating current inflow conduction width and the direct current outflow conduction width is defined as a high-voltage bridge bottom horizontal timing feature; and h, a relationship between the low-voltage bridge alternating current inflow conduction width and the direct current outflow conduction width is defined as a low-voltage bridge bottom horizontal timing feature.

In this embodiment, the foregoing timing features at a-h are collectively referred to as the horizontal and vertical timing features, which are described by the following formulas:

- where t_DCVTFrepresents the direct-current vertical timing feature, t_{ACVTF_HB}represents the high-voltage bridge vertical timing feature, t_{ACVTF_LB}represents the low-voltage bridge vertical timing feature, t_{ACVTF_HLB}represents the double-bridge vertical timing feature, t_{THTF_HB}represents the high-voltage bridge top horizontal timing feature, t_{THTF_LB}represents the low-voltage bridge top horizontal timing feature, t_{BHTF_HB}represents the high-voltage bridge bottom horizontal timing feature, and t_{BHTF_LB}represents the low-voltage bridge bottom horizontal timing feature.

At S104, the time width of each valve conduction state is compared with a time width of a normal valve conduction state, and each valve state signal is output.

- (1) In normal operation, three phases and six valves of the j bridge are successively and alternately triggered to conduct at equal phase intervals of 60°. In the meantime, according to the formula of step S1023, the time width of the normal valve conduction state is obtained. The specific formula is as follows:

$t_{HT_normal} = \frac{T}{3}$

- where t_{HVT_normal}represents the time width of the normal valve conduction state.
- (2) The time width t_jHVmof each valve conduction state calculated in step S1023 is compared with the time width t_{HVT_normal}of the normal valve conduction state to determine whether each valve conduction state is abnormal. The specific formula is as follows:

${\begin{matrix} | t_{jHVm} - t_{{HVT}_{normal}} | \leq ε; valve normal \\ | t_{jHVm} - t_{{HVT}_{normal}} | > ε; valve abnormal \end{matrix}$

- where j=Y/D, m=1, 2, 3, 4, 5, 6, and ε represents a threshold.
- (3) An abnormal valve is located according to an output state via a range comparator through the foregoing time width t_jHVmof each valve conduction state calculated in step S1023. The specific formula is as follows:

${cs}_{jHVm} = {\begin{matrix} 1; t_{jHVm} - t_{HVT_normal} > ε \\ 0; - ε \leq t_{jHVm} - t_{HVT_normal} \leq ε \\ - 1; t_{jHVm} - t_{HVT_normal} < - ε \end{matrix}$

- where j=Y/D, m=1, 2, 3, 4, 5, 6, ε represents a threshold, cs_jHVmrepresents a valve state signal, 1 represents that the valve conduction state is overlong, 0 represents that the valve conduction state is normal, and −1 represents that the valve conduction state is shortened.

At S105, valve-level fault location for the converter is implemented according to the time width of each valve conduction state, the alternating current conduction width, the direct current conduction width, the horizontal and vertical timing features, each valve state signal, and the current data.

As shown in FIG. 2, converter faults include internal faults k1-k5, external faults k6-k8, and a line fault k9.

As shown in FIG. 4, the specific steps of step S105 in this embodiment are as follows.

At S1051, it is determined whether the direct current inflow conduction width is less than the power frequency cycle. If yes, it is determined that the fault is the line fault k9. If no, step S1052 is performed.

At S1052, it is determined whether the direct-current vertical timing feature satisfies t_dH−t_dN>Δ, where Δ is a value greater than 0. If yes, step S1053 is performed. If no, step S1054 is performed.

At S1053, it is determined whether the high-voltage bridge vertical timing feature satisfies t_{Y_top}≠t_{Y_bottom}or whether the low-voltage bridge vertical timing feature satisfies t_{D_top}≠t_{D_bottom}. If yes, it is determined that the fault is the external fault k7. If no, it is determined that the faults are the external faults k4 and k5.

At S1054, it is determined whether there is an abnormal valve state signal in twelve converter valves. If yes, step S1055 is performed. If no, step S101 is performed again.

At S1055, it is determined whether three conditions are simultaneously satisfied: (1) a maximum value of the direct-current high-voltage current and the direct-current neutral current is greater than a maximum value of the three-phase alternating currents of the j bridge, (2) commutation fails, and (3) there is no difference in high-voltage bridge or low-voltage bridge top horizontal timing features, if yes, determining that the faults are external faults k6 and k8, and if no, determining that the faults are internal faults k1, k2, and k3.

The specific implementation of the foregoing three conditions in this embodiment is as follows.

- A. A magnitude relationship of an alternating current and a direct current (current data) is constructed based on the following formula:

${\begin{matrix} i_{d \max} - i_{ac} \geq 0 \\ i_{d \max} = \max (i_{dH}, i_{dN}) \\ i_{ac} = \max (i_{acY}, i_{acD}) \\ i_{acY} = \max (i_{Ya}, i_{Yb}, i_{Yc}) \\ i_{acD} = \max (i_{Da}, i_{Db}, i_{Dc}) \end{matrix}$

- where i_dmaxis the maximum value of the direct-current high-voltage current i_dHand the direct-current neutral current i_dN, i_acYis the maximum value of the three-phase alternating currents i_Ya, i_Yb, and i_Ycof the high-voltage bridge, i_acDis the maximum value of the three-phase alternating currents i_Da, i_Db, and i_Dcof the alternating side of the low-voltage bridge, and i_acis the maximum value of i_acYand i_acD.
- B. When the commutation fails, two valves being commutated must have an interlocking relationship of an overlong valve conduction state and a shortened valve conduction state, and a commutation failure criterion is constructed based on the following formula:

${\begin{matrix} {cs}_{jHm} = 1 \\ {cs}_{jHm + 2} = - 1 \end{matrix}$

- where j=Y/D, and m=1, 2, 3, 4, 5, 6.
- C. It is determined whether the high-voltage bridge top horizontal timing feature satisfies t_dH=t_{Y_top}or whether the low-voltage bridge bottom horizontal timing feature satisfies t_dH=t_{D_top}.

As shown in FIG. 5, fault determination is performed using a time window width in this embodiment.

Further, as shown in FIG. 6, according to the internal faults k1-k5 located in steps S1051-S1055, in combination with step S103, data of the horizontal and vertical timing features in the time window width is obtained to determine each internal fault type. The specific steps are as follows.

At S11, horizontal and vertical timing feature data in the time window width

$t \in [\frac{T}{3}, \frac{T}{2}]$

is obtained.

At S12, if it is detected that the difference between the high-voltage bridge or low-voltage bridge top horizontal timing features is less than the time window width t, t_dH−t_{Y_top}<t or t_dH−t_{D_top}<t, it is determined the fault is k1. Otherwise, if it is detected that the difference between the high-voltage bridge or low-voltage bridge top horizontal timing features is greater than the time window width, t_dH−t_{Y_top}>t or t_dH−t_{D_top}>t, it is determined the fault is k2. If not satisfied, it is determined the fault is k3.

At S13, if it is detected that the double-bridge vertical timing feature does not satisfy t_{Y_bottom}>t_{D_top}, it is determined that the faults are k4(1) and k4(3). Otherwise, it is determined whether the low-voltage bridge bottom horizontal timing feature satisfies t_dN=t_{D_bottom}. If yes, it is determined that the faults are k4(2) and k5(1). Otherwise, it is determined that the fault is k5(2).

When the fault is k1, it is determined whether the double-bridge vertical timing feature satisfies t_{Y_bottom}>t_{D_top}. If no, it is determined that the faults are k1(1) and k1(2). If yes, it is determined that the faults are k1(3) and k1(4).

When the fault is k2, it is determined whether the double-bridge vertical timing feature satisfies t_{Y_bottom}>t_{D_top}. If yes, it is determined that the fault is k2(2). Otherwise, it is determined whether the double-bridge vertical timing feature satisfies t_{Y_bottom}<t_{D_top}. If yes, it is determined that the fault is k2(1). Otherwise, it is determined that the fault is k2(3).

When the fault is k3, it is determined whether the double-bridge vertical timing feature satisfies t_{Y_bottom}>t_{D_top}. If yes, it is determined that the fault is k3(1). Otherwise, it is determined that the fault is k3(2).

When the faults are k4(1) and k4(3), it is determined whether the difference between the high-voltage bridge and low-voltage bridge top horizontal timing features is greater than the time window width t_dH−t_{Y_top}>t. If yes, it is determined that the fault is k4(1). Otherwise, it is determined that the fault is k4(3).

When the faults are k4(2) and k5(1), it is determined whether the low-voltage bridge alternating current conduction width satisfies t_{D_bottom}=t+ε, ε is a valve-abnormal threshold. If no, it is determined that the fault is k5(1). If yes, it is determined that the fault is k4(2).

Furthermore, according to internal fault types (valve-level faults at different fault locations) k1, k3, and k5, which are successfully located, in combination with step S1023, data of the time widths of six valve conduction states in a converter bridge where the internal fault types k1, k3, and k5 are located in the time window width is obtained to implement fault valve and fault phase location. The specific steps are as follows.

At S21, time width data of six valve conduction states in the time window width

$t \in [\frac{T}{3}, \frac{T}{2}]$

is obtained.

At S22, a fault phase and a fault valve are located, specifically as follows.

As shown in FIG. 7, when faults k1(1) and k1(2) are located, the fault valve is located according to a valve having the longest time width of the valve conduction state in six valves of a high-voltage bridge. If valve m is equal to 4, it is determined that the fault is k1(1)-V14 short circuit. The location of other different fault valves in the fault type k1 is shown in detail in FIG. 7.

As shown in FIG. 8, when fault k3(1) is located, the fault phase is located according to two valves having the longest conduction width in the six valves of the high-voltage bridge. The location of the fault phase in the fault type k3 is shown in detail in FIG. 8.

As shown in FIG. 9, when fault k5(1) is located, the fault phase is located according to a phase where the valve having the longest conduction width in the six valves of the high-voltage bridge is located. If the valve having the longest conduction width is on V1 or V4, it is determined that phase a of k5(1) is grounded. The location of other different fault phases in the fault type k5 is shown in detail in FIG. 9.

As shown in Table 1, this embodiment describes an example where an inverter-side high-voltage bridge valve V12 short-circuit fault is set at 3.101 s. According to the longest conduction width of V12 in 12 valve conduction widths, it is determined that the fault is k1(1)-V12, where the simulation results are consistent with the fault setting, which verifies the effectiveness of the method of this embodiment.

TABLE 1

Simulation Data

Feature quantity

Area 2

Area 1

max(All

fault

i_dmax≥
t_dH/
t_dN/
t_Y_—_top/
t_Y_—_bottom/
t_D_—_top/
t_D_—_bottom/
(t_jHVm))/
Determination

type
cs_Hm≠ 0
CF
i_ac
ms
ms
ms
ms
ms
ms
ms
result

k1(1)
✓
x
x
20
20
19.35-
19.35-
20
20
11.05
k1(1) −

V12

14.05
14.05

V12

Internal fault
t_dH= t_dN
max(t_dH− t_Y_—_top) = 5.95 < 10, t_Y_—_top< t_D_—_bottom, j = Y, m = 2

The simulation data of the fault location in Table 1 is divided into area 1, area 2, and determination results. In the table header: area 1 represents a criterion feature for fault area determination, where “√” indicates that the criterion is satisfied, and “x” indicates that the criterion is not satisfied; area 2 represents the range of the alternating and direct current conduction widths of fault electrical information in the time window width.

It should be noted that although the method operations of the foregoing embodiment are depicted in the drawings in a particular order, this does not require or imply that the operations must be performed in the particular order, or that all of the illustrated operations must be performed to achieve the desired results. Rather, the depicted steps may change the order of execution. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step for execution, and/or one step may be decomposed into multiple steps for execution.

Embodiment 2

As shown in FIG. 10, this embodiment provides a valve-level fault location system for converters based on horizontal and vertical state differences of valves. The system includes a collection unit 1001, a calculation unit 1002, a construction unit 1003, a comparison unit 1004, and a fault location unit 1005. The specific functions of each unit are as follows.

The collection unit 1001 is configured to collect current data of a converter. The current data includes three-phase alternating currents of a j bridge, a direct-current high-voltage current, and a direct-current neutral current, where j=Y/D, Y represents a high voltage, and D represents a low voltage.

The calculation unit 1002 is configured to calculate a time width of each valve conduction state, an alternating current conduction width, and a direct current conduction width based on the current data.

The construction unit 1003 is configured to construct horizontal and vertical timing features on a circuit structure of the converter according to the alternating current conduction width and the direct current conduction width.