may also include various input devices, including a mechanical or virtual button 116, which may be accessible from the front surface (or display surface) of the device 100. In some cases, the virtual button 116 and/or other features of the device 100 may be implemented using an under-display camera or image sensor. In some cases, an under-display camera or image sensor may occupy a larger area than the area in which the virtual button 116 is implemented (and in some cases an area consonant with or larger than the display 104).

The device 100 may also include buttons or other input devices positioned along the sidewall 118 and/or on a rear surface of the device 100. For example, a volume button or multipurpose button 120 may be positioned along the sidewall 118, and in some cases may extend through an aperture in the sidewall 118. The sidewall 118 may include one or more ports 122 that allow air, but not liquids, to flow into and out of the device 100. In some embodiments, one or more sensors may be positioned in or near the port(s) 122. For example, an ambient pressure sensor, ambient temperature sensor, internal/external differential pressure sensor, gas sensor, particulate matter concentration sensor, or air quality sensor may be positioned in or near a port 122.

In some embodiments, the rear surface of the device 100 may include a rear-facing camera 124 that includes one or more image sensors (see FIG. 1B). A flash or light source 126 may also be positioned on the rear of the device 100 (e.g., near the rear-facing camera). In some cases, the rear surface of the device 100 may include multiple rear-facing cameras.

As described herein, one or more of the cameras or image sensors of the device 100 may be constructed and/or operated to provide an ALS feature.

FIG. 2 shows an architectural view of one example of an image sensor 200, such as an image sensor associated with one of the cameras described with reference to FIGS. 1A and 1B. The image sensor 200 may include an image processor 202 and an imaging area 204 (or more generally, a sensing area). The imaging area 204 may be implemented as an array of pixels 206. The pixels 206 may be same-colored pixels (e.g., for a monochrome imaging area 204) or differently colored pixels (e.g., for a multi-color imaging area 204). In the illustrated embodiment, the pixels 206 are arranged in rows and columns. However, the pixels 206 may alternatively be arranged in any suitable configuration, such as, for example, a hexagonal configuration.

The imaging area 204 may be in communication with a column readout circuit 208 through one or more column output lines 210, and with a row driver circuit 212 through one or more control signal lines 214 (e.g., n≥1 control signal lines, including, for example, a reset (RST) signal line, a charge transfer (TX) signal line, and a row select (RS) signal line). The row driver circuit 212 may selectively control a particular pixel 206 or group of pixels, such as all of the pixels 206 in a certain row, and in some cases may control different pixels 206 or groups of pixels in different ways, so that the different pixels 206 or groups of pixels can perform different operations in parallel. The column readout circuit 208 may selectively receive the data output from a selected pixel 206 or group of pixels 206 (e.g., all of the pixels in a particular row).

The row driver circuit 212 and/or column readout circuit 208 may be in communication with an image processor 202. The image processor 202 may determine how to control the pixels 206; process data from the pixels 206; and receive control information from, or provide processed data to, another processor (e.g., a system processor) and/or other components of a device (e.g., other components of the device 100 described with reference to FIGS. 1A and 1B). The image processor 202 may also receive focus information (e.g., phase-detect auto-focus (PDAF) information) from some or all of the pixels 206 and perform a focusing operation for the image sensor 200.

In some embodiments, the image sensor 200 may be configured as a rolling shutter image sensor, in which different rows or columns of pixels 206 are sequentially enabled and read out. In other embodiments, the image sensor 200 may be configured as a global shutter image sensor, in which all of the pixels 206 are enabled at once, charges integrated by the pixels 206 are locally stored, and then the charges are read out by row or column.

FIGS. 3A-3B show a schematic representation and corresponding operational timing diagram, respectively, of a representative three-transistor pixel 300 in a CMOS image sensor having a plurality of such pixels. As shown in FIG. 3A, the pixel 300 may include a sense node 302, a charge integration circuit 304 electrically coupled to the sense node 302, a readout circuit 306 electrically coupled to the sense node 302, and a reset circuit 308 electrically coupled to the sense node 302. The charge integration circuit 304 may include a photodetector 310 (e.g., a photodiode, D_PD). The photodetector 310 may have terminals that are electrically coupled between ground and the sense node 302. A sense node capacitance 312 (e.g., C_SN) may store a charge that is integrated by the photodetector 310 in response to light impinging on the photodetector 310. The sense node capacitance 312 performs the charge-to-voltage conversion for the pixel 300. The readout circuit 306 may include a source follower transistor (M_SF) 314 and a row select transistor (M_RS) 316, coupled in series via their source and drain terminals between a bias voltage (V_SF) and a column readout line 318. The gate of the source follower transistor 314 may be coupled to the sense node 302, and the gate of the row select transistor 316 may receive a row select (RS) signal. The voltage (V_SN) that is read out of the pixel 300 may be amplified by a column amplifier and digitized by a column analog-to-digital converter (not shown). The reset circuit 308 may include a reset transistor (M_RST) 320, coupled via its source and drain terminals between a reset line 322 and the sense node 302. The gate of the reset transistor 320 may receive a reset (RST) signal. The reset line 322 may be held at a reset voltage (V_RST). The sense node capacitance 312 may include a capacitance of the charge integration circuit 304 (e.g., a capacitance of the photodetector 310), a capacitance of the readout circuit 306 (e.g., a gate capacitance of the source follower transistor 314), and a capacitance of the reset circuit 308 (e.g., a diffusion capacitance of the reset transistor 320), in addition to any parasitic capacitance.

FIG. 3B shows a timing diagram for operation of the pixel 300 (and more particularly, for a pixel in a row i and a column j of an image sensor). During the “SN+PD Reset” phase, a control circuit (and in some cases a control circuit that is operated by a processor, which processor is executing a program that is stored in memory) may assert the RST signal and pull the sense node 302 to V_RST(i.e., to V_SNij=V_RST), thereby resetting the pixel 300 for a new image frame. The control circuit may also assert the RS signal or maintain the RS signal in an asserted state. Following the “SN+PD Reset” phase and during a first part of a Double-Delta Sampling (DDS) Readout phase, the control circuit may de-assert the RST signal, thereby electrically isolating the sense node 302 from the reset line 322. Immediately after the RST signal is de-asserted, a baseline voltage of the sense node 302 (i.e., a reset value plus noise) may be read out to the column readout line 318 through the source follower transistor 314 and the row select transistor 316 (e.g., at the time of Reset Sampling). The reset sample contains noise components due to signal feed-thru and charge injection from the reset transistor 320 and thermal KTC noise. Following the first part of the DDS readout phase and during the “Exposure” phase, the control circuit may de-assert the RS signal, thereby electrically isolating the sense node 302 from the column readout line 318, and a charge may be integrated by the photodetector 310. The integrated charge may be stored on the sense node 302. Following the “Exposure” phase and during a second part of the DDS Readout phase, the control circuit may assert the RS signal and a voltage corresponding to the charge stored on the sense node 302 may be read out to the column readout line 318 through the source follower transistor 314 and the row select transistor 316 (e.g., at the time of Signal Sampling). The reset voltage read out during the first part of the DDS Readout phase may be subtracted from the voltage read out during the second part of the DDS Readout phase to obtain the voltage corresponding to the charge integrated by the photodetector 310. This compensates for all correlated noise components, such as signal feed-thru noise and charge injection nose. It does not compensate for thermal KTC noise, which is uncorrelated between the reset and signal sampling. After the second part of the DDS Readout phase, the control circuit may assert the RST signal, a new “SN+PD Reset” phase may begin, and the pixel 300 may be used to integrate a charge for a next image frame.

Although the pixel 300 is shown to be implemented with n-type metal oxide semiconductor (NMOS) transistors, the pixel 300 may be implemented with p-type metal oxide semiconductor (PMOS) transistors, a combination of NMOS and PMOS transistors, or other types of transistors. The pixel 300 may also be implemented with signals having the opposite polarity (or sense) from what is shown in FIG. 3B.

FIGS. 4A-4B show a schematic representation and corresponding operational timing diagram, respectively, of a representative four-transistor pixel 400 in a CMOS image sensor having a plurality of such pixels. As shown in FIG. 4A, the pixel 400 may include a sense node 402, a charge integration circuit 404 electrically coupled to the sense node 402, a readout circuit 406 electrically coupled to the sense node 402, and a reset circuit 408 electrically coupled to the sense node 402. The charge integration circuit 404 may include a photodetector 410 (e.g., a photodiode, D_PD). The photodetector 410 may have terminals that are electrically coupled between ground and a charge-transfer transistor (M_TG) 424. The charge-transfer transistor 424 may be electrically coupled between the photodetector 410 and the sense node 402 via its source and drain terminals. The gate of the charge-transfer transistor 424 may receive a transfer gate (TG) signal. In the example of FIG. 4A, the sense node 402 serves as a floating diffusion node that can be electrically isolated from the photodetector 410 by the charge-transfer transistor 424. A sense node capacitance 412 (e.g., C_SN) may store a charge that is integrated by the photodetector 410 in response to light impinging on the photodetector 410. The sense node capacitance 412 performs the charge-to-voltage conversion for the pixel 400. The readout circuit 406 may include a source follower transistor (M_SF) 414 and a row select transistor (M_RS) 416, coupled in series via their source and drain terminals between a bias voltage (V_SF) and a column readout line 418. The gate of the source follower transistor 414 may be coupled to the sense node 402, and the gate of the row select transistor 416 may receive a row select (RS) signal. The voltage (V_SN) that is read out of the pixel 400 may be amplified by a column amplifier and digitized by a column analog-to-digital converter (not shown). The reset circuit 408 may include a reset transistor (M_RST) 420, coupled via its source and drain terminals between a reset line 422 and the sense node 402. The gate of the reset transistor 420 may receive a reset (RST) signal. The reset line 422 may be held at a reset voltage (V_RST). The sense node capacitance 412 may include a diffusion capacitance of the charge-transfer transistor 424, a capacitance of the readout circuit 406 (e.g., a gate capacitance of the source follower transistor 414), and a capacitance of the reset circuit 408 (e.g., a diffusion capacitance of the reset transistor 420), in addition to any parasitic capacitance.

FIG. 4B shows a timing diagram for operation of the pixel 400 (and more particularly, for a pixel in a row i and a column j of an image sensor). During the “SN Reset” phase, a control circuit (and in some cases a control circuit that is operated by a processor, which processor is executing a program that is stored in memory) may assert the RST signal and pull the sense node 402 to V_RST(i.e., to V_SNij=V_RST), thereby resetting the sense node 402. Following the “SN Reset” phase and during a first part of a Correlated Double Sampling (CDS) Readout phase, the control circuit may de-assert the RST signal, thereby electrically isolating the sense node 402 from the reset line 422. Immediately after the RST signal is de-asserted, a baseline voltage of the sense node 402 (i.e., a reset value plus noise) may be read out to the column readout line 418 through the source follower transistor 414 and the row select transistor 416 (e.g., at the time of Reset Sampling). The reset sample contains noise components due to signal feed-thru and charge injection from the reset transistor 420 and thermal KTC noise. Following the first part of the CDS readout phase and during the “Transfer” phase, the control circuit may assert the TG signal, thereby transferring a charge integrated by the photodetector 410 to the sense node 402. The transferred charge may be stored on the sense node 402. Following the “Transfer” phase, and during a second part of the CDS Readout phase, the control circuit may de-assert the TG signal, thereby electrically isolating the photodetector 410 from the sense node 402, and a voltage of the sense node 402 (i.e., a voltage corresponding to the charge integrated by the photodetector 410, plus noise) may be read out to the column readout line 418 through the source follower transistor 414 and the row select transistor 416 (e.g., at the time of Signal Sampling). The reset voltage read out during the first part of the CDS Readout phase may be subtracted from the voltage read out during the second part of the CDS Readout phase to obtain the voltage corresponding to the charge integrated by the photodetector 410. All noise components are compensated as they are all correlated in the reset and signal samples. The control circuit may assert the RS signal during each of the “SN Reset”, “Transfer”, and CDS Readout phases, and de-assert the RS signal before and after these phases. Following the second part of the CDS readout phase and during the “SN+PD Reset” phase, the control circuit may assert the RST and TG signals, pulling both the sense node 402 and the photodetector 410 to V_RST(i.e., to V_SNij=V_RST) and resetting the pixel 400 for a new image frame. Following the “SN+PD Reset” phase and during the “Exposure” phase, the control circuit may de-assert the RST and TG signals, thereby electrically isolating the sense node 402 from the reset line 422 and the photodetector 410, and a charge may be integrated by the photodetector 410. Following the “Exposure” phase, the control circuit may assert the RS and RST signals, and a new “SN Reset” phase may begin.

Although the pixel 400 is shown to be implemented with NMOS transistors, the pixel 400 may be implemented with PMOS transistors, a combination of NMOS and PMOS transistors, or other types of transistors. The pixel 400 may also be implemented with signals having the opposite polarity (or sense) from what is shown in FIG. 4B.

FIG. 5 shows a schematic representation of a modified version of the pixel described with reference to FIGS. 4A and 4B. The pixel 500 differs from the pixel described with reference to FIGS. 4A and 4B in that its charge integration circuit 404 includes multiple photodetectors 410 (e.g., a first photodetector 410-1, a second photodetector 410-2, a third photodetector 410-3, and a fourth photodetector 410-4), and each photodetector 410 may be coupled to a shared sense node 402 by a respective charge-transfer transistor 424 (e.g., a first charge-transfer transistor 424-1, a second charge-transfer transistor 424-2, a third charge-transfer transistor 424-3, or a fourth charge-transfer transistor 424-4). The gate of each charge-transfer transistor 424 may receive a respective transfer gate signal (e.g., TG1, TG2, TG3, or TG4). In operation, a charge may be integrated by each of the photodetectors 410 in parallel. The integrated charges may then be transferred to the sense node 402 in parallel, by the control circuit asserting each of TG1, TG2, TG3, and TG4 contemporaneously, during a single “Transfer” phase (i.e., a simultaneous transfer of charges to the sense node 402, such that the charges are summed (or binned) at the sense node 402). Alternatively, the pixel may be operated, during an image frame, with a single “SN+PD Reset” phase and “Exposure” phase, but with per-photodetector “SN Reset”, “Transfer” and CDS Readout phases (i.e., to sequentially (separately) transfer and read out the voltages corresponding to the charges integrated by each of the photodetectors 410.

FIG. 6A shows an example portion of a CMOS image sensor 600 that may be used for image acquisition and ambient light sensing. The image sensor 600 may include a plurality of pixels 602. FIG. 6A shows a set of pixels 602₁, . . . , 602_narranged in one row of the image sensor 600. The image sensor 600 may, in some embodiments, include multiple rows of pixels, as described with reference to FIG. 2. The set of pixels includes at least a first pixel 602₁and a second pixel 602_n. Each of the pixels 602₁, . . . , 602_nmay be a three-transistor pixel, such as the pixel 300 described with reference to FIG. 3A, a four-transistor pixel, such as the pixel 400 described with reference to FIG. 4A, a multiple photodetector pixel, such as the pixel 500 described with reference to FIG. 5, or another type of pixel having a reset circuit. Each of the pixels 602₁, . . . , 602_nmay include a respective sense node 604₁, . . . , 604_n, a respective charge integration circuit (not shown, but shown in other figures), a respective readout circuit 606₁, . . . , 606_n, and a respective reset circuit 608₁, . . . , 608_n, electrically coupled as described in FIG. 3A, 4A, or 5, or in other ways.

The image sensor 600 may further include a reset line 610 for providing a reset voltage to the pixels 602₁, . . . , 602_n, and a switch 612 (e.g., a switching transistor) that is electrically coupled in series with the reset line 610 and operable to couple (and decouple) the reset line 610 to a source 614 of a reset voltage (V_RST). The reset line 610 may be coupled or decoupled to the sense nodes 604₁, . . . , 604_nof one or multiple pixels 602₁, . . . , 602_nby the reset circuits 608₁, . . . , 608_nof the pixels 602₁, . . . , 602_n(e.g., by the reset transistors of the pixels 602₁, . . . , 602_n). In some embodiments, the switch 612 may include a metal oxide semiconductor (MOS) transistor (M_{ISO_ALS}), coupled between the reset line 610 (and by means of the reset line 610, to the reset circuits 608₁, . . . , 608_n) and the source 614 of the reset voltage by its source and drain terminals (e.g., in the embodiment shown in FIG. 6A, in which the switch 612 includes a PMOS transistor, a source terminal of the PMOS transistor may be connected to the source 614 of the reset voltage and a drain terminal of the PMOS transistor may be connected to the reset line 610). The gate of the MOS transistor may receive an ALS isolation control signal (ISO_ALS). The same source 614 may be alternately coupled to different reset lines coupled to different subsets of pixels (e.g., different rows of pixels, different colors of pixels, or other subsets of pixels) within the image sensor 600, via different switches; or different sources of reset voltages may be coupled to different reset lines by different switches.

The type of MOS transistor used for the switch 612 may depend on the type of transistors used in the reset circuits 608₁, . . . , 608_nor the MOS design used for the image sensor 600 as a whole. In some embodiments, in which the reset circuits 608₁, . . . , 608_ninclude NMOS transistors, a switching transistor used in the switch 612 maybe either a PMOS transistor or, alternatively, an NMOS transistor having a gate voltage that is boosted above the reset voltage provided by the reset line 610. In other embodiments, in which the reset circuits 608₁, . . . , 608_ninclude PMOS transistors, the switching transistor may be a PMOS transistor having a gate voltage boosted below the reset voltage provided by the reset line 610. The switch 612 may include an enhancement mode (positive threshold voltage (V_TH)) transistor or, alternatively, a depletion mode (or negative V_TH) transistor.

In some embodiments, a control circuit (and in some cases a control circuit that is operated by a processor, which processor is executing a program that is stored in memory) may be coupled to the pixels 602₁, . . . , 602_nand the switch 612 and determine when the various gate signals provided to the transistors of the image sensor 600 are asserted and de-asserted. The control circuit may be configured to operate the image sensor 600 in various modes of operation. For example, in a first mode, typically after a charge is integrated by each of the pixels 602₁, . . . , 602_nand before the pixels 602₁, . . . , 602_nare reset, the control circuit may turn off the switch 612 to electrically isolate the reset line 610 from the source 614 of the reset voltage, and then turn on the reset transistors of the reset circuits 608₁, . . . , 608_nto electrically couple the sense nodes 604₁, . . . , 604_nof the pixels 602₁, . . . , 602_nto the reset line 610. This enables charge redistribution among the sense nodes 604₁, . . . , 604_nof the pixels 602₁, . . . , 602_n, resulting in each of the sense nodes 604₁, . . . , 604_nhaving the same value (i.e., same average voltage). In a second mode, following the first mode and before the pixels 602₁, . . . , 602_nare reset, the control circuit may turn off the reset transistors of the reset circuits 608₁, . . . , 608_nto electrically isolate the sense nodes 604₁, . . . , 604_nfrom the reset line 610. Contemporaneously, the control circuit may turn off the switch 612 to electrically isolate the reset circuits 608₁, . . . , 608_nfrom the reset line 610. Subsequently, a voltage corresponding to the redistributed charge may be read out from any one of the pixels 602₁, . . . , 602_n, as a voltage value representing an ambient light condition. In a third mode, subsequent to the second mode, the control circuit may turn on the switch 612 and the reset transistors of the reset circuits 608₁, . . . , 608_n, to supply the reset voltage to the sense nodes 604₁, . . . , 604_nof the pixels 602₁, . . . , 602_nthrough the reset line 610 and the reset transistors of the reset circuits 608₁, . . . , 608_n. The third mode may occur after reading out a charge integrated by each of the pixels 602₁, . . . , 602_n, and after reading out a redistributed charge from one of the pixels 602₁, . . . , 602_n.

The switch 612 and control circuit operation described with reference to FIG. 6A can be used to introduce an ALS phase into the timeline described with reference to FIG. 3B or 4B, which enables ambient light sensing after reading out a set of integrated charges from a set of pixels 602₁, . . . , 602_n. During the ALS phase, all of the sense nodes in a set of pixels 602₁, . . . , 602_nare transitioned to a same voltage V_{SN_ALS}as a result of charge redistribution. This means that any one of the pixels 602₁, . . . , 602_nmay be used to determine an ALS value, which in turns means that only a single column of pixels in an image sensor needs to be read if charge is redistributed within each row of pixels in the image sensor. Thus, compared to conventional image capture using a CMOS image sensor, the ALS method described herein consumes significantly less power and can be performed faster than an image (or full image) capture. The analog voltage value read out from a sense node of a pixel, after charge redistribution, may be converted, using an analog-to-digital converter (ADC), to a digital value that correlates with a quantifiable ambient light condition. The digital resolution of the readout can be increased by increasing the number of ADCs in each row of an image sensor and averaging the readouts. The ambient light condition determined from an image frame may be used to determine and/or adjust an exposure time for a next (or subsequent) image frame by, for example, using an auto-exposure algorithm.

Although the reset line 610 may be associated with a parasitic capacitance 616, the parasitic capacitance 616 may be engineered small enough that it does not introduce significant error into the charge rebalance between the sense nodes 604₁, . . . , 604_n. In some embodiments, the parasitic capacitance 616 may introduce a linear systematic error into the charge rebalance, and consequently into the voltage corresponding to the charge rebalance (which voltage is read out of a pixel), and the linear systematic error may be calibrated out.

FIGS. 6B-6C show timing diagrams for operation of a three-transistor pixel, such as the pixel 300 described with reference to FIG. 3A (sec, FIG. 6B), or a four-transistor pixel, such as the pixel 400 described with reference to FIG. 4A (see, FIG. 6C) when a set of such pixels are coupled to a reset line with switch as described in FIG. 6A. In FIG. 6B, the “ALS” phase is introduced after the second part of the DDS Readout phase and before the “SN+PD Reset” phase (both described with respect to FIG. 3B). During the “ALS” phase, the ISO_ALS signal may be temporarily de-asserted, and then the RST signal may be asserted while the RS signal remains asserted and the ISO_ALS signal remains de-asserted. In FIG. 6C, the “ALS” phase is introduced after the second part of the CDS Readout phase and before the “SN+PD Reset” phase (both described with respect to FIG. 4B). During the “ALS” phase, the ISO_ALS signal may be temporarily de-asserted, and then the RST signal may be asserted while the RS signal remains asserted and the ISO_ALS signal remains de-asserted.

After redistributing charge between the sense nodes of a set of pixels, a voltage V_{SN_ALS}appears at the sense node of each pixel involved in the charge redistribution. The voltage V_{SN_ALS}may be read out of a single pixel in the set of pixels (e.g., at Row Average Sampling). A different but similarly generated voltage V