2, the waveform of each of the signals in the time interval T1 and the time interval T2 is repeated such that the first transistor group and the second transistor group perform operation described above in an interlaced manner in the interlaced input mode. It is appreciated that since the first transistor group and the second transistor group are reset by using the reset signal receiving process when the differential signal receiving process is not performed, no additional time is required to reset these transistors. As a result, a time difference between two neighboring input enabling sections (e.g., the input enabling sections IE1 and IE2) of each of the input control signals CI1 and CI2 can be smaller than a predetermined value, even close to 0.

By using the grouping of the transistor, the second transistor group in the configuration of the amplifier circuit 100 in FIG. 3A forms a cascode structure to increase output impedances of the differential output terminals O+ and O−. The amplifier circuit 100 thus provides a gain applied to the first differential input signals VI1+ and VI1− larger than a gain applied to the second differential input signals VI2+ and VI2−. The first transistor group in the configuration of the amplifier circuit 100 in FIG. 3B forms a current source structure. The amplifier circuit 100 thus provides a power supply rejection ratio (PSRR) applied to the second differential input signals VI2+ and VI2− larger than a power supply rejection ratio applied to the first differential input signals VI1+ and VI1−.

Reference is now made to FIG. 4. FIG. 4 illustrates a circuit diagram of an amplifier circuit 400 having reset mechanism according to another embodiment of the present invention. The amplifier circuit 400 includes a pair of upper-half branches 410A and 410B and a pair of lower-half branches 420A and 420B.

The configuration of the upper-half branches 410A and 410B is identical to the configuration of the upper-half branches 110A and 110B in FIG. 1, in which the upper-half branch 410A includes the first P-type transistor MP11 and the second P-type transistor MP12 and the upper-half branch 410B includes the first P-type transistor MP21 and the second P-type transistor MP22. The configuration of the lower-half branches 420A and 420B is identical to the configuration of the lower-half branches 120A and 120B in FIG. 1, in which the lower-half branch 420A includes the first N-type transistor MN11 and the second N-type transistor MN12 and the lower-half branches 120B includes the first N-type transistor MN21 and the second N-type transistor MN22.

However, in FIG. 4, the first transistor group includes the first P-type transistor MP11, the first P-type transistor MP21, the first N-type transistor MN11 and the first N-type transistor MN21. The second transistor group includes the second P-type transistor MP12, the second P-type transistor MP22, the second N-type transistor MN12 and the second N-type transistor MN22.

As a result, in FIG. 4, the input switch SI1 and the reset switch SR1 correspond to the first transistor group. The input switch S12 and the reset switch SR2 still correspond to the second transistor group. The operation of the input switches SI1 and SI2 and the reset switches SR1 and SR2 is identical to those in the previous embodiment and is not described herein.

Reference is now made to FIG. 5A. FIG. 5A illustrates an equivalent circuit diagram of the amplifier circuit 400 under the condition that the first transistor group performs the differential signal receiving process and the second transistor group performs the reset signal receiving process according to an embodiment of the present invention.

The first P-type transistor MP11, the first P-type transistor MP21, the first N-type transistor MN11 and the first N-type transistor MN21 in the first transistor group receive the first differential input signals VI1+ and VI1− through the enabled input switch SI1 and generate the first differential output signals VO1+ and VO1− at the differential output terminals O+ and O−.

The second P-type transistor MP12 and the second P-type transistor MP22 in the second transistor group receive the third reset signal RS3 through the enabled reset switch SR2 and the second N-type transistor MN12 and the second N-type transistor MN22 in the second transistor group receive the fourth reset signal RS4 through the enabled reset switches SR2.

Reference is now made to FIG. 5B. FIG. 5B illustrates an equivalent circuit diagram of the amplifier circuit 400 under the condition that the second transistor group performs the differential signal receiving process and the first transistor group performs the reset signal receiving process according to an embodiment of the present invention.

The first P-type transistor MP11 and the first P-type transistor MP21 in the first transistor group receive the first reset signal RS1 through the enabled reset switch SR1 and the first N-type transistor MN11 and the first N-type transistor MN21 in the first transistor group receive the second reset signal RS2 through the enabled reset switch SR1.

The second P-type transistor MP12, the second P-type transistor MP22, the second N-type transistor MN12 and the second N-type transistor MN22 in the second transistor group receive the second differential input signals VI2+ and VI2− through the enabled input switch SI2 to generate the second differential output signals VO2+ and VO2− at the differential output terminals O+ and O−.

By using the grouping of the transistor, the configuration of the amplifier circuit 100 in FIG. 5A provides a first gain applied to the first differential input signals VI1+ and VI1− and a second gain applied to the second differential input signals VI2+ and VI2−, in which a difference value between the first gain and the second gain is smaller than a predetermined value. In other words, comparing to the configuration in FIG. 3A and FIG. 3B, the gains applied to the first differential input signals VI1+ and VI1− and the second differential input signals VI2+ and VI2− in FIG. 5A are closer. Further, the configuration of the amplifier circuit 100 in FIG. 5B provides a power supply rejection ratio applied to the second differential input signals VI2+ and VI2− larger than a power supply rejection ratio applied to the first differential input signals VI