is connected to the light-exiting surface 111 in the bent manner, and a bend angle defined between the peripheral side surface 112 and the light-exiting surface 111 may be of, but is not limited to, 90° or approximately 90°. In the schematic diagram provided in the implementation, for example, the bend angle defined between the peripheral side surface 112 and the light-exiting surface 111 is of 90°, thereby facilitating manufacturing of the light-emitting layer 11. The light-exiting surface 111 may be, but is not limited to, a circular plane. In the schematic diagram of the implementation, for example, the light-exiting surface 111 is a circular plane, so that the light-emitting layer 11 can provide a uniform light-exiting effect in the spherical light-emitting chip 10. The peripheral side surface 112 is arranged around the light-exiting surface 111, and the peripheral side surface 112 may be, but is not limited to, arranged around the light-exiting surface 111 to define a cylindrical structure, thereby facilitating implementations of flows of the process of the light-emitting layer 11.

The second electrode 13 is disposed at the side of the light-emitting layer 11 away from the light-exiting surface 111, so that a light-exiting area of the light-emitting layer 11 is not reduced, and thus the spherical light-emitting chip 10 can provide a good light-exiting effect.

Referring to FIGS. 1 and 2 again, the alignment guiding layer 14 is disposed at an end of the second electrode 13 away from the light-emitting layer 11, and the alignment guiding layer 14 forms part of an appearance surface of the spherical light-emitting chip 10.

The alignment guiding layer 14 is disposed at the end of the second electrode 13 away from the light-emitting layer 11, that is, the alignment guiding layer 14 is designed to be close to the appearance surface of the spherical light-emitting chip 10, thereby facilitating alignment of the spherical light-emitting chip 10 during transferring. The alignment guiding layer 14 forms part of the appearance surface of the spherical light-emitting chip 10, thereby facilitating alignment of the spherical light-emitting chip 10 during transferring. Compared with a spherical light-emitting chip 10 in which the alignment guiding layer 14 is disposed, the spherical light-emitting chip 10 herein has a stronger adhesive force, and thus the spherical light-emitting chip 10 can be subject to more stable adsorption during transferring.

Referring to FIGS. 1 and 2 again, the first electrode 12 is arranged around the peripheral side surface 112 of the light-emitting layer 11.

The first electrode 12 is arranged around the peripheral side surface 112 of the light-emitting layer 11, thereby not blocking light exited from the light-exiting surface 111 of the light-emitting layer 11, and thus maximizing the light-exiting area of the spherical light-emitting chip 10, and enabling the spherical light-emitting chip 10 to provide a good light-exiting effect.

Referring to FIGS. 1, 2, and 3, FIG. 3 is a schematic cross-sectional structural view of a spherical light-emitting chip in an implementation of the disclosure, taken along line A-A. The spherical light-emitting chip 10 has a sphere-center plane 16 passing through the sphere center of the spherical light-emitting chip 10. The light-emitting layer 11 is disposed on the sphere-center plane 16 of the spherical light-emitting chip 10, and the sphere-center plane 16 is perpendicular to the central axis 15.

The spherical light-emitting chip 10 has the sphere-center plane 16 passing through the sphere center of the spherical light-emitting chip 10. In the schematic diagram of the implementation, for example, the sphere-center plane 16 is perpendicular to the central axis 15. The light-emitting layer 11 is disposed on the sphere-center plane 16 of the spherical light-emitting chip 10. The light-emitting layer 11 may, but is not limited to, partially penetrate the sphere-center plane 16, or the light-exiting surface 111 of the light-emitting layer 11 may be, but is not limited to, in contact with the sphere-center plane 16. In the schematic diagram of the implementation, for example, the light-exiting surface 111 of the light-emitting layer 11 is in contact with the sphere-center plane 16 (referring to FIG. 3), which can maximize the light-exiting area of the spherical light-emitting chip 10, thereby enabling the spherical light-emitting chip 10 to have optimal light-exiting efficiency.

Referring to FIGS. 1 and 2 again, the spherical light-emitting chip 10 may further include a first semiconductor 17, a second semiconductor 18, and an insulation layer 19. The first semiconductor 17 covers and is in contact with the light-exiting surface 111 of the light-emitting layer 11. The first semiconductor 17 is in conduction with the first electrode 12. The second semiconductor 18 is disposed on a surface of the light-emitting layer 11 away from the light-exiting surface 111. The second semiconductor 18 is in conduction with the second electrode 13, and a peripheral side surface 112 of the second semiconductor 18 is spaced apart from the first electrode 12. The insulation layer 19 may include a first insulation portion 191 and a second insulation portion 192 connected to the first insulation portion 191. The first insulation portion 191 is disposed at a periphery of the second insulation portion 192 and is connected to the second insulation portion 192 in a bent manner. One end of the first insulation portion 191 away from the second insulation portion 192 is arranged between the peripheral side surface 112 of the light-emitting layer 11 and the first electrode 12, and the other end of the first insulation portion 191 adjacent to the second insulation portion 192 is arranged between the peripheral side surface 112 of the second semiconductor 18 and the first electrode 12. The second insulation portion 192 surrounds the second electrode 13 and is arranged between the alignment guiding layer 14 and the second semiconductor 18.

The first semiconductor 17 may be, but is not limited to, an N-type semiconductor, and the first semiconductor 17 can inject electrons into the light-emitting layer 11. The first semiconductor 17 may be made of a material including, but not limited to, Gallium Phosphide (GaP), Indium Phosphide (InP), Indium Nitride (InN), or GaN. The first semiconductor 17 is in conduction with the first electrode 12, and the first semiconductor 17 can diffuse electrons to the light-emitting layer 11 under a voltage applied by the first electrode 12. The first semiconductor 17 may be, but is not limited to, hemispherical. In the schematic diagram of the implementation, for example, the first semiconductor 17 is hemispherical. The first semiconductor 17 covers and is in contact with the light-exiting surface 111 of the light-emitting layer 11, so that the first semiconductor 17 can uniformly diffuse electrons to the light-emitting layer 11.

The second semiconductor 18 may be, but is not limited to, a P-type semiconductor, and the second semiconductor 18 can inject holes into the light-emitting layer 11. The second semiconductor 18 may be made of a material including, but not limited to, GaP, InP, InN, or GaN. The second semiconductor 18 is in conduction with the second electrode 13, and the second semiconductor 18 can diffuse holes to the light-emitting layer 11 under a voltage applied by the second electrode 13. Under the voltages applied, the electrons of the first semiconductor 17 are diffused to the light-emitting layer 11, the holes of the second semiconductor 18 are diffused to the light-emitting layer 11, and the electrons and the holes are recombined in the light-emitting layer 11 to generate recombined energy, and release the recombined energy through light emission, so that the spherical light-emitting chip 10 performs light exiting. The second semiconductor 18 may be, but is not limited to, cylindrical. In the schematic diagram of the implementation, for example, the second semiconductor 18 is cylindrical. The second semiconductor 18 is disposed on the surface of the light-emitting layer 11 away from the light-exiting surface 111. The second semiconductor 18 may be, but is not limited to, in contact with the surface of the light-emitting layer 11 away from the light-exiting surface 111, which is conducive for the second semiconductor 18 to uniformly diffuse holes to the light-emitting layer 11. The peripheral side surface 112 of the second semiconductor 18 is spaced apart from the first electrode 12, thereby avoiding interference of the voltage applied by the first electrode 12 on normal operation of the second semiconductor 18, and further ensuring a normal light-exiting effect and operation of the spherical light-emitting chip 10.

The insulation layer 19 may include a first insulation portion 191 and a second insulation portion 192 connected to the first insulation portion 191. The first insulation portion 191 and the second insulation portion 192 may be, but are not limited to, integrally formed. In the schematic diagram of the implementation, for example, the first insulation portion 191 and the second insulation portion 192 are integrally formed, thereby facilitating design and implementation of processes. The first insulation portion 191 is disposed at a periphery of the second insulation portion 192 and is connected to the second insulation portion 192 in a bent manner. A bend angle defined between the first insulation 191 and the second insulation 192 may be of, but is not limited to, 90° or approximately 90°. In the schematic diagram provided in the implementation, for example, the bend angle defined between the first insulation element 191 and the second insulation element 192 is of 90°. It can be understood that the bend angle defined between the first insulation element 191 and the second insulation element 192 may be of other degrees, which shall not be a limit to the spherical light-emitting chip 10 provided in the implementation. The first insulation portion 191 may be, but is not limited to, arranged around the light-emitting layer 11 and the second semiconductor 18. In the schematic diagram of the implementation, for example, the first insulation portion 191 is arranged around the light-emitting layer 11 and the second semiconductor 18. One end of the first insulation portion 191 away from the second insulation portion 192 is arranged between the peripheral side surface 112 of the light-emitting layer 11 and the first electrode 12, thereby reducing an adverse impact of the first electrode 12 on the light-exiting efficiency of the light-emitting layer 11. The end of the first insulation portion 191 away from the second insulation portion 192 may be, but is not limited to, in contact with the light-emitting layer 11 and the first electrode 12, which is conducive for implementation of process design while a good insulation effect is ensured. The other end of the first insulation portion 191 adjacent to the second insulation portion 192 is arranged between the peripheral side surface 112 of the second semiconductor 18 and the first electrode 12, thereby avoiding an adverse impact of the first electrode 12 on normal operation of the second semiconductor 18. The other end of the first insulation portion 191 adjacent to the second insulation portion 192 may be, but is not limited to, in contact with the second semiconductor 18 and the first electrode 12, which is conducive for implementation of process design while a good insulation effect is ensured. The second insulation portion 192 is arranged around the second electrode 13, and the second insulation portion 192 may be, but is not limited to, in contact with a surface of the second electrode 13. The second insulation portion 192 is arranged between the alignment guiding layer 14 and the second semiconductor 18, thereby avoiding interference between the alignment guiding layer 14 and the second semiconductor 18, and further ensuring a transfer yield and normal operation of the spherical light-emitting chip 10.

Referring to FIG. 4, FIG. 4 is a schematic cross-sectional structural view of a spherical light-emitting chip in an implementation of the disclosure, taken along line A-A. The spherical light-emitting chip 10 has a diameter D. A height H₁of the first electrode 12 along the central axis 15 satisfies: H₁<0.5*D. A height H₂of the second electrode 13 along the central axis 15 satisfies H₂<0.5*D.

The height H₁of the first electrode 12 along the central axis 15 may be, but is not limited to, 0.3*D, 0.2*D, or 0.4*D, as long as H₁<0.5*D is satisfied. When the height H₁satisfies: H₁<0.5*D, it is convenient for processing and manufacturing of an electrode layer, a ratio of a volume of the electrode layer to a volume of the light-emitting chip and a ratio of a volume of the electrode layer to a volume of a device where the spherical light-emitting chip 10 is applied are reduced, and maximum light-exiting efficiency of the spherical light-emitting chip 10 and maximum light-exiting efficiency of the device where the spherical light-emitting chip 10 is applied are ensured.

The height H₂of the second electrode 13 along the central axis 15 may be, but is not limited to, 0.3*D, 0.2*D, or 0.4*D, as long as H₂<0.5*D is satisfied. When the height H₂satisfies: H₂<0.5*D, it is convenient for processing and manufacturing of the electrode layer, the ratio of the volume of the electrode layer to the volume of the light-emitting chip and the ratio of the volume of the electrode layer to the volume of the device where the spherical light-emitting chip 10 is applied are reduced, and the maximum light-exiting efficiency of the spherical light-emitting chip 10 and the maximum light-exiting efficiency of the device where the spherical light-emitting chip 10 is applied are ensured.

Referring to FIGS. 5, 6, 7, and 8, FIG. 5 is a schematic structural view of a display device in implementations of the disclosure, FIG. 6 is a schematic cross-sectional structural view of the display device provided in FIG. 5, taken along line B-B, FIG. 7 is a schematic top view of a portion of a display device in an implementation of the disclosure, and FIG. 8 is a schematic cross-sectional structural view of the display device provided in FIG. 7, taken along line C-C. A display device 1 is further provided in implementations of the disclosure. The display device 1 includes a display substrate 20 and the spherical light-emitting chip 10. The display substrate 20 defines multiple recesses 21 each configured to receive one spherical light-emitting chip 10.

The display device 1 may be, but is not limited to, a mobile phone, a watch, a tablet computer, a notebook computer, a television, or a portable electronic device. The display device 1 includes the display substrate 20 and the spherical light-emitting chip 10. The display device 1 may further include, but is not limited to, a power supply, a housing, or other components. It can be understood that other components of the display device 1 shall not be a limit to the display device 1 provided in the implementation.

Specifically, the display substrate 20 may be, but is not limited to, a Complementary Metal Oxide Semiconductor (CMOS) substrate, a Thin Film Transistor (TFT) substrate, or a Liquid Crystal on Silicon (LCOS) substrate. The display substrate 20 may be made of a semiconductor material including, but not limited to, silicon (Si), silicon carbide (SIC), GaN, germanium (Ge), gallium arsenide (GaAs), or InP. The display substrate 20 may be made of a non-conductive material including, but not limited to, glass or sapphire. The display substrate 20 may include, but is not limited to, a driving circuit, where the driving circuit may be configured to drive the spherical light-emitting chip 10. The driving circuit may be an active matrix driving circuit or a passive matrix driving circuit. The display substrate 20 may be configured to carry the spherical light-emitting chip 10 and drive the spherical light-emitting chip 10 to operate. The display substrate 20 may define the multiple recesses 21, where the recess 21 may be formed on a surface of the display substrate 20 and is configured to receive the spherical light-emitting chip 10, thereby facilitating limit of the spherical light-emitting chip 10 during transferring. The recess 21 and the spherical light-emitting chip 10 may be in one-to-one correspondence, that is, a single recess 21 receives a single spherical light-emitting chip 10, thereby facilitating precise limit of the spherical light-emitting chip 10. The recess 21 may be, but is not limited to, hemispherical. In the schematic diagram of the implementation, for example, the recess 21 is hemispherical and is in contact with the appearance surface of the spherical light-emitting chip 10, thereby facilitating reception and fixing of the spherical light-emitting chip 10. It can be understood that the recess 21 may also be designed in other shapes, and the shape of the recess 21 shall not be a limit to the display device 1 provided in the implementation.

The display substrate 20 may include, but is not limited to, a third electrode 23 and a fourth electrode 24. The third electrode 23 may be connected to the first electrode 12 and configured to transmit a voltage to the first electrode 12. The third electrode 23 may be, but is not limited to, partially of an annular shape. In the schematic diagram of the implementation, for example, the third electrode 23 is partially of an annular shape surrounding the spherical light-emitting chip 10, so that the third electrode 23 and the first electrode 12 can be connected uniformly, thereby ensuring stable voltage transmission between the third electrode 23 and the first electrode 12. The fourth electrode 24 may be connected to the second electrode 13 and configured to transmit a voltage to the second electrode 13. A projection of the fourth electrode 24 may be, but is not limited to, circular. In the schematic diagram of the implementation, for example, a projection of a connection between the fourth electrode 24 and the second electrode 13 is circular, thereby facilitating matching between a shape of the fourth electrode 24 and a shape of the second electrodes 13. In this way, the fourth electrode 24 and the second electrodes 13 can be connected uniformly, thereby ensuring stable voltage transmission between the fourth electrode 24 and the second electrode 13.

Referring to FIGS. 5, 6, 7 and 8 again, the display device 1 may include an alignment guiding member 22 disposed on the display substrate 20 and disposed corresponding to the recess 21. The alignment guiding member 22 is configured to position the spherical light-emitting chip 10 through attraction between the alignment guiding member 22 and the alignment guiding layer 14 of the spherical light-emitting chip 10.

The alignment guiding member 22 may be, but is not limited to, formed by charged particles, and precise transferring and alignment of the spherical light-emitting chip 10 are achieved through electrostatic adsorption. Specifically, when the alignment guiding layer 14 of the spherical light-emitting chip 10 consists of positively charged particles, the alignment guiding member 22 consists of negatively charged particles. When the alignment guiding layer 14 of the spherical light-emitting chip 10 consists of negatively charged particles, the alignment guiding member 22 consists of positively charged particles. During transferring of the spherical light-emitting chip 10, a movement posture of the spherical light-emitting chip 10 during transferring is adjusted under an electrostatic adsorption force generated between the alignment guiding layer 14 and the alignment guiding member 22, so that electrodes of the spherical light-emitting chip 10 can be in one-to-one correspondence with electrodes of the alignment guiding member 22. The alignment guiding member 22 may also be made of a magnetic material, for example, an electrical steel, a rare earth alloy, a metal alloy, or a ferrite material, and thus precise alignment and transferring of the spherical light-emitting chip 10 can be achieved through magnetic adsorption.

The alignment guiding member 22 is disposed on the display substrate 20 and disposed corresponding to the recess 21. The alignment guiding member 22 may be, but is not limited to, disposed at a bottom of the recess 21. In the schematic diagram of the implementation, for example, the alignment guiding member 22 is disposed at the bottom of the recess 21, thereby facilitating mutual cooperation between the alignment guiding member 22 and the alignment guiding layer 14 of the spherical light-emitting chip 10. The alignment guiding member 22 is configured to position the spherical light-emitting chip 10, thereby achieving precise transferring of the spherical light-emitting chip 10.

The alignment guiding layer 14 is arranged around the second electrode 13, and the surface of the alignment guiding layer 14 surrounding the second electrode 13 is in contact with the peripheral side surface 112 of the second electrode 13, so that the alignment guiding layer 14 as a whole is arranged close to the central axis 15 of the spherical light-emitting chip 10. Therefore, the spherical light-emitting chip 10 is subject to more stable adsorption during transferring, and imprecise alignment of the spherical light-emitting chip 10 caused by dispersed adsorption force during transferring can be effectively reduced.

Referring to FIGS. 9 and 10, FIG. 9 is a schematic flow chart illustrating a manufacturing method of a spherical light-emitting chip in an implementation of the disclosure, and FIG. 10 is a schematic flow chart illustrating a manufacturing method of a spherical light-emitting chip in an implementation of the disclosure. The manufacturing method of the spherical light-emitting chip 10 includes operations at S101, S102, S103, S104, S105, S106, S107, S108, S109, and S110, and is described in detail as follows.

S101, provide a first bearing substrate 30.

S102, manufacture a light-emitting blank layer 51 on the first bearing substrate 30.

Specifically, the light-emitting blank layer 51 may be made of a material including, but not limited to, GaN or InGaN. The light-emitting blank layer 51 may be manufactured in a manner including, but not limited to, vapor deposition or evaporation. It can be understood that the light-emitting blank layer 51 may also be manufactured through other processes.

S103, perform array segmentation on the light-emitting blank layer 51 to define multiple first through holes 52 that penetrate through the light-emitting blank layer 51 and are arranged at intervals.

Specifically, the array segmentation on the light-emitting blank layer 51 may be implemented in a manner including, but not limited to, laser. The first through hole 52 penetrates through the light-emitting blank layer 51. The first through hole 52 may be in a shape including, but not limited to, a cuboid or a similar cuboid. It can be understood that the shape of the first through hole 52 shall not be a limit to the first through hole 52 provided in the implementation. The first through holes 52 are arranged at intervals, and the first through holes 52 may be spaced apart from each other by a same distance or different distances.

S104, provide an alignment-guiding blank layer 53 at a side of the light-emitting blank layer 51 away from the first bearing substrate 30.

Specifically, the alignment-guiding blank layer 53 may be, but is not limited to, formed by charged particles, and precise transferring and alignment of the spherical light-emitting chip 10 are achieved through electrostatic adsorption. The alignment-guiding blank layer 53 may also be made of a magnetic material, for example, an electrical steel, a rare earth alloy, a metal alloy, or a ferrite material, and thus precise alignment and transferring of the spherical light-emitting chip 10 can be achieved through magnetic adsorption. The alignment-guiding blank layer 53 is disposed at the side of the light-emitting blank layer 51 away from the first bearing substrate 30. The alignment-guiding blank layer 53 may be spaced apart from the light-emitting blank layer 51, so as to avoid an adverse impact on light-emitting efficiency of the light-emitting blank layer 51.

S105, define multiple second through holes 54 penetrating through the alignment-guiding blank layer 53 and multiple third through holes 55 penetrating through the alignment-guiding blank layer 53.

Specifically, the second through hole 54 may be defined in a manner including, but not limited to, etching. The second through hole 54 may penetrate through the alignment-guiding blank layer 53.

The third through hole 55 may be defined in a manner including, but not limited to, etching. The third through hole 55 may penetrate through the alignment-guiding blank layer 53.

S106, dispose a conductive layer 56 on the alignment-guiding blank layer 53. The conductive layer 56 may include first conductive portions 561 each received in one second through hole 54 and second conductive portions 562 each received in one third through hole 55. The first conductive portion 561 is spaced apart from the light-emitting blank layer 51, and the second conductive portion 562 is spaced apart from the light-emitting blank layer 51. The alignment-guiding blank layer 53 surrounds the second conductive portion 562, and a surface of the alignment-guiding blank layer 53 surrounding the second conductive portion 562 is in contact with a peripheral side surface 112 of the second conductive portion 562.

Specifically, the conductive layer 56 may be formed on the alignment-guiding blank layer 53 in a manner including, but not limited to, vapor deposition or evaporation. The conductive layer 56 may be made of a material including, but not limited to, Ni/Au or Cr/Pt/Au. The conductive layer 56 includes the first conductive portion 561 each received in one second through hole 54 and the second conductive portions 562 each received in one third through hole 55. The first conductive portion 561 is spaced apart from the light-emitting blank layer 51, thereby avoiding interference of the first conductive portion 561 on the light-emitting efficiency of the light-emitting blank layer 51. The second conductive portion 562 is spaced apart from the light-emitting blank layer 51, thereby avoiding interference of the second conductive portion 562 on the light-emitting efficiency of the light-emitting blank layer 51. The alignment-guiding blank layer 53 may be arranged around the second conductive portion 562, and the surface of the alignment-guiding blank layer 53 surrounding the second conductive portion 562 may be in contact with the peripheral side 112 of the second conductive portion 562, so that the alignment guiding layer 14 as a whole is arranged close to the center of the spherical light-emitting chip 10, and thus the spherical light-emitting chip 10 is subject to more stable adsorption during transferring.

S107, remove an excess portion of the alignment-guiding blank layer 53, an excess portion of the first conductive portion 561, and an excess portion of the second conductive portion 562 to form a hemispherical light-emitting chip 50.

Specifically, the excess portion of the alignment-guiding blank layer 53, the excess portion of the first conductive portion 561, and the excess portion of the second conductive portion 562 may be removed in a manner including, but not limited to, etching, to form the hemispherical light-emitting chip 50.

S108, provide a second bearing substrate 40 at a side of the hemispherical light-emitting chip 50 away from the first bearing substrate 30.

Specifically, the second bearing substrate 40 may be disposed at the side of the hemispherical light-emitting chip 50 away from the first bearing substrate 30, and the second bearing substrate 40 may be, but is not limited to, in contact with a hemispherical surface of the hemispherical light-emitting chip 50.

S109, peel off the first bearing substrate 30, and manufacture an end of the hemispherical light-emitting chip 50 away from the second bearing substrate 40 to be in a hemispherical shape.

Specifically, the first bearing substrate 30 may be peeled off in a manner including, but not limited to, development stripping, and the end of the hemispherical light-emitting chip 50 away from the second bearing substrate 40 is manufactured to be in the hemispherical shape.

S110, peel off the second bearing substrate 40 to obtain a spherical light-emitting chip 10. The spherical light-emitting chip 10 has a central axis 15 passing through a spherical center of the spherical light-emitting chip 10. The second conductive portion 562 extends in a direction of the central axis 15, and the central axis 15 passes through the second conductive portion 562.

Specifically, the second bearing substrate 40 may be peeled off in a manner including, but not limited to, development stripping, to obtain the spherical light-emitting chip 10. The spherical light-emitting chip 10 has the central axis 15 passing through the sphere center of the spherical light-emitting chip 10. The second conductive portion 562 extends in the direction of the central axis 15, and the central axis 15 passes through the second conductive portion 562. During transferring of the spherical light-emitting chip 10, the spherical light-emitting chip 10 can be precisely transferred to a target position under the guidance of the alignment guiding layer 14, and the alignment guiding layer 14 as a whole is arranged close to the central axis 15 of the spherical light-emitting chip 10, so that the spherical light-emitting chip 10 is more stable in alignment, thereby effectively improving transferring precision and transferring efficiency of the spherical light-emitting chip 10.

Referring to FIGS. 11A, 11B, 12A and 12B, FIGS. 11A and 11B collectively show a schematic flow chart illustrating a manufacturing method of a spherical light-emitting chip in an implementation of the disclosure, and FIGS. 12A and 12B collectively show a schematic flow chart illustrating a manufacturing method of a spherical light-emitting chip in an implementation of the disclosure. In another implementation of the disclosure, a manufacturing method of the spherical light-emitting chip 10 is further provided and includes operations at S201, S202, S203, S204, S205, S206, S207, S208, S209, S210, and S211, which are described in detail as follows.

S201, provide a first bearing substrate 30.

S202, sequentially manufacture a first-semiconductor blank layer 57, a light-emitting blank layer 51, and a second-semiconductor blank layer 58 on the first bearing substrate 30.

Specifically, the first-semiconductor blank layer 57 may be made of a material including, but not limited to, GaP, InP, InN, or GaN. The first-semiconductor blank layer 57 may be manufactured in a manner including, but not limited to, vapor deposition or evaporation. It can be understood that the first-semiconductor blank layer 57 may also be manufactured through other processes. The first-semiconductor blank layer 57 may be, but is not limited to, an N-type semiconductor and is configured to inject electrons into the light-emitting blank layer 51.

The light-emitting blank layer 51 may be made of a material including, but not limited to, GaN or InGaN. The light-emitting blank layer 51 may be manufactured in a manner including, but not limited to, vapor deposition or evaporation. It can be understood that the light-emitting blank layer 51 may also be manufactured through other processes.

The second-semiconductor blank layer 58 may be made of a material including, but not limited to, GaP, InP, InN, or GaN. The second-semiconductor blank layer 58 may be manufactured in a manner including, but not limited to, vapor deposition or evaporation. It can be understood that the second-semiconductor blank layer 58 may also be manufactured through other processes. The second-semiconductor blank layer 58 may be, but is not limited to, a P-type semiconductor and is configured to inject holes into the light-emitting blank layer 51.

S203, perform array segmentation on the second-semiconductor blank layer 58 and the light-emitting blank layer 51 to define multiple first through holes 52 that penetrate through the second-semiconductor blank layer 58 and the light-emitting blank layer 51 and are arranged at intervals.

Specifically, the array segmentation on the second-semiconductor blank layer 58 and the light-emitting blank layer 51 may be implemented in a manner including, but not limited to, laser. The first through hole 52 penetrates through the second-semiconductor blank layer 58 and the light-emitting blank layer 51. The first through hole 52 may be in a shape including, but not limited to, a cuboid or a similar cuboid. It can be understood that the shape of the first through hole 52 shall not be a limit to the first through hole 52 provided in the implementation. The first through holes 52 are arranged at intervals, and the first through holes 52 may be spaced apart from each other by a same distance or different distances.

S204, cover, with an insulation blank layer 59, a surface of the first-semiconductor blank layer 57, a surface of the light-emitting blank layer 51, and a surface of the second-semiconductor blank layer 58, where the insulation blank layer 59 includes an insulation body layer 591 and insulation blank portions 592 each received in one first through hole 52.

Specifically, the insulation blank layer 59 may be manufactured in a manner including, but not limited to, vapor deposition or evaporation. It can be understood that the insulation blank layer 59 may also be manufactured through other processes. The insulation blank layer 59 includes the insulation body layer 591 and the insulation blank portions 592 each received in one first through hole 52. The insulation body layer 591 may be, but is not limited to, part of the insulation blank layer 59 covering the first-semiconductor blank layer 57, and the insulation blank portion 592 may be, but is not limited to, part of the insulation blank layer 59 received in the first through hole 52.

S205, cover an alignment-guiding blank layer 53 on a surface of the insulation blank layer 59.

Specifically, the alignment-guiding blank layer 53 may be manufactured in a manner including, but not limited to, vapor deposition or evaporation. The alignment-guiding blank layer 53 may be, but is not limited to, formed by charged particles, and precise transferring and alignment of the spherical light-emitting chip 10 are achieved through electrostatic adsorption. The alignment-guiding blank layer 53 may also be made of a magnetic material, for example, an electrical steel, a rare earth alloy, a metal alloy, or a ferrite material, and thus precise alignment and transferring of the spherical light-emitting chip 10 can be achieved through magnetic adsorption.

S206, define multiple second through holes 54 penetrating through the alignment-guiding blank layer 53 and the insulation blank portion 592, and define multiple third through holes 55 penetrating through the alignment-guiding blank layer 53 and the insulation body layer 591.

Specifically, the second through hole 54 may be defined in a manner including, but not limited to, etching. The second through hole 54 may penetrate through the alignment-guiding blank layer 53 and the insulation blank portion 592.

The third through hole 55 may be defined in a manner including, but not limited to, etching. The third through hole 55 may penetrate through the alignment-guiding blank layer 53 and the insulation body layer 591.

S207, dispose a conductive layer 56 on the alignment-guiding blank layer 53. The conductive layer 56 may include first conductive portions 561 each received in one second through hole 54 and second conductive portions 562 each received in one third through hole 55.

S208, remove an excess portion of the insulation blank layer 59, an excess portion of the alignment-guiding blank layer 53, an excess portion of the first conductive portion 561, and an excess portion of the second conductive portion 562 to form a hemispherical light-emitting chip 50.

Specifically, the excess portion of the insulation blank layer 59, the excess portion of the alignment-guiding blank layer 53, the excess portion of the first conductive portion 561, and the excess portion of the second conductive portion 562 may be removed in a manner including, but not limited to, etching, to form the hemispherical light-emitting chip 50.

S209, provide a second bearing substrate 40 at a side of the hemispherical light-emitting chip 50 away from the first bearing substrate 30.

S210, peel off the first bearing substrate 30 and remove an excess portion of the first-semiconductor blank layer 57.

Specifically, the first bearing substrate 30 may be peeled off in a manner including, but not limited to, development stripping. The excess portion of the first-semiconductor blank layer 57 may be removed in a manner including, but not limited to, etching. The first-semiconductor blank layer 57 may be manufactured into a semi-spherical shape, thereby obtaining a complete spherical light-emitting chip 10.

S211, peel off the second bearing substrate 40 to obtain the spherical light-emitting chip 10.

Specifically, the second bearing substrate 40 may be peeled off in a manner including, but not limited to, development stripping, to obtain the spherical light-emitting chip 10. The first-semiconductor blank layer 57 forms the first semiconductor 17 of the spherical light-emitting chip 10. The light-emitting blank layer 51 forms the light-emitting layer 11 of the spherical light-emitting chip 10. The second-semiconductor blank layer 58 forms the second semiconductor 18 of the spherical light-emitting chip 10. The insulation blank layer 59 forms the insulation layer 19 of the spherical light-emitting chip 10. The insulation body layer 591 forms the second insulation portion 192 of the spherical light-emitting chip 10. The insulation blank portion 592 forms the first insulation portion 191 of the spherical light-emitting chip 10. The first conductive portion 561 forms the first electrode 12 of the spherical light-emitting chip 10. The second conductive portion 562 forms the second electrode 13 of the spherical light-emitting chip 10. The alignment-guiding blank layer 53 forms the alignment guiding layer 14 of the spherical light-emitting chip 10. Furthermore, the spherical light-emitting chip 10 may have a central axis 15 passing through the sphere center of the spherical light-emitting chip 10. The second electrode 13 extends in the direction of the central axis 15, and the central axis 15 passes through the second conductive portion 562. The alignment guiding layer 14 is arranged around the second electrode 13, and the surface of the alignment guiding layer 14 surrounding the second electrode 13 is in contact with the peripheral side surface 112 of the second electrode 13. During transferring of the spherical light-emitting chip 10, the spherical light-emitting chip 10 can be precisely transferred to the target position under the guidance of the alignment guiding layer 14, and the alignment guiding layer 14 as a whole is arranged close to the central axis 15 of the spherical light-emitting chip 10, so that the spherical light-emitting chip 10 is more stable in alignment, thereby effectively improving transfer precision and transferring efficiency of the spherical light-emitting chip 10.

Referring to FIGS. 13, 14A and 14B, FIG. 13 is a schematic flow chart illustrating a transferring method of a spherical light-emitting chip in an implementation of the disclosure, and FIGS. 14A and 14B collectively show a schematic flow chart illustrating a transferring method of a spherical light-emitting chip in an implementation of the disclosure. A transferring method of the spherical light-emitting chip 10 is further provided in the disclosure and includes operations at S301, S302, S303, S304, and S305, which are described in detail as follows.

S301, provide a spherical light-emitting chip 10. The spherical light-emitting chip 10 includes a light-emitting layer 11, a first electrode