111 formed of a plurality of layers which is in contact with the first active layer 121 of the first thin film transistor 120 may be larger than thicknesses of the lower layer and the intermediate layer of the first buffer layer 111. For example, as illustrated in FIG. 1, when the first buffer layer 111 is a five-layered structure, the 1-e-th buffer layer 111e which is in contact with the first active layer 121 may be the upper layer. Further, the 1-a-th buffer layer 111a which is in contact with the substrate 110 may be the lower layer. Furthermore, the 1-b-th buffer layer 111b, the 1-c-th buffer layer 111c, and the 1-d-th buffer layer 111d which are disposed between the 1-a-th buffer layer 111a and the 1-e-th buffer layer 111e may be intermediate layers. Here, a thickness of the 1-e-th buffer layer 111e which is an upper layer may be larger than the thickness of the 1-a-th buffer layer 111a which is a lower layer and the thicknesses of the 1-b-th buffer layer 111b, the 1-c-th buffer layer 111c, and the 1-d-th buffer layer 111d which are intermediate layers. In an example, the thickness of the 1-e-th buffer layer 111e may be 3000 Å, and the thickness of the 1-a-th buffer layer 111a may be 1000 Å. Further, the thicknesses of the 1-b-th buffer layer 111b, the 1-c-th buffer layer 111c, and the 1-d-th buffer layer 111d may be 1000 Å.

In the first buffer layer 111 formed of a plurality of layers, a plurality of layers other than the upper layer which is in contact with the first active layer 121 of the first thin film transistor 120 may have the same thickness. For example, the thicknesses of the 1-a-th buffer layer 111a, the 1-b-th buffer layer 111b, the 1-c-th buffer layer 111c, and the 1-d-th buffer layer 111d (excluding the 1-e-th buffer layer 111e which is in contact with the first active layer 121) may be equal to each other.

The first thin film transistor 120 may be disposed on the first buffer layer 111. The first thin film transistor 120 may include the first active layer 121, a first gate electrode 124, a first source electrode 122, and a first drain electrode 123. Here, depending on the design of the pixel circuit, the first source electrode 122 may serve as a drain electrode, and the first drain electrode 123 may serve as a source electrode. The first active layer 121 of the first thin film transistor 120 may be disposed on the first buffer layer 111.

The first active layer 121 may include a low temperature poly silicon (LTPS). Such a polysilicon material may have a high mobility (100 cm²/Vs or higher) so that energy power consumption is low and reliability is excellent. Therefore, the polysilicon material may be applied to a gate driver for driving elements which drive thin film transistors for a display element and/or a multiplexer (MUX), and also applied as an active layer of a driving thin film transistor of the display apparatus according to the example embodiment, but is not limited thereto. For example, the polysilicon material may be applied as an active layer of a switching thin film transistor depending on the characteristics of the display apparatus. An amorphous silicon (a-Si) material is deposited on the first buffer layer 111, a dehydrogenation process and a crystallization process are performed to form polysilicon, and the polysilicon is patterned to form the first active layer 121.

The first active layer 121 may include a first channel region 121a in which a channel is formed at the time of driving the first thin film transistor 120, and a first source region 121b and a first drain region 121c at both sides of the first channel region 121a. The first source region 121b refers to a part of the first active layer 121 which is connected to the first source electrode 122, and the first drain region 121c refers to a part of the first active layer 121 which is connected to the first drain electrode 123. The first source region 121b and the first drain region 121c may be configured by ion doping (impurity doping) of the first active layer 121. The first source region 121b and the first drain region 121c may be produced by doping ions into the polysilicon material, and the first channel region 121a may refer to a part that is not doped with ions and remains with the polysilicon material.

The first gate insulating layer 112 may be disposed on the first active layer 121 of the first thin film transistor 120. The first gate insulating layer 112 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multi-layer thereof. In the first gate insulating layer 112, a contact hole may be formed. And, the first source electrode 122 and the first drain electrode 123 of the first thin film transistor 120 are connected to the first source region 121b and the first drain region 121c of the first active layer 121 of the first thin film transistor 120 through the contact hole, respectively.

The first gate electrode 124 of the first thin film transistor 120 and a first capacitor electrode 141 of the storage capacitor 140 may be disposed on the first gate insulating layer 112.

The first gate electrode 124 and the first capacitor electrode 141 may be formed as a single layer or a multi-layer formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chrome (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first gate electrode 124 may be formed on the first gate insulating layer 112 to overlap the first channel region 121a of the first active layer 121 of the first thin film transistor 120. The first capacitor electrode 141 may be omitted based on a driving characteristic of the display apparatus 100 and a structure and a type of the thin film transistor. The first gate electrode 124 and the first capacitor electrode 141 may be formed by the same process. Further, the first gate electrode 124 and the first capacitor electrode 141 may be formed of the same material on the same layer.

The first interlayer insulating layer 113 may be disposed on the first gate insulating layer 112, the first gate electrode 124, and the first capacitor electrode 141. The first interlayer insulating layer 113 may be configured by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multi-layer thereof. A contact hole through which the first source region 121b and the first drain region 121c of the first active layer 121 of the first thin film transistor 120 are exposed may be formed in the first interlayer insulating layer 113.

A second capacitor electrode 142 of the storage capacitor 140 may be disposed on the first interlayer insulating layer 113. The second capacitor electrode 142 may be formed as a single layer or a multi-layer formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chrome (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The second capacitor electrode 142 may be formed on the first interlayer insulating layer 113 to overlap the first capacitor electrode 141. The second capacitor electrode 142 may be formed of the same material as the first capacitor electrode 141. The second capacitor electrode 142 may be omitted based on a driving characteristic of the display apparatus 100 and a structure and a type of the thin film transistor.

The second buffer layer 114 may be disposed on the first interlayer insulating layer 113 and the second capacitor electrode 142. The second buffer layer 114 may be configured as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multi-layer thereof. A contact hole through which the first source region 121b and the first drain region 121c of the first active layer 121 of the first thin film transistor 120 are exposed may be formed in the second buffer layer 114. Further, the contact hole may be formed. And, the second capacitor electrode 142 of the storage capacitor 140 is exposed though the contact hole.

A second active layer 131 of the second thin film transistor 130 may be disposed on the second buffer layer 114. The second thin film transistor 130 may include the second active layer 131, a second gate insulating layer 115, a second gate electrode 134, a second source electrode 132, and a second drain electrode 133. Here, depending on the design of the pixel circuit, the second source electrode 132 may serve as a drain electrode, and the second drain electrode 133 may serve as a source electrode.

The second active layer 131 may include a second channel region 131a in which a channel is formed at the time of driving the second thin film transistor 130, and a second source region 131b and a second drain region 131c at both sides of the second channel region 131a. The second source region 131b refers to a part of the second active layer 131 which is connected to the second source electrode 132, and the second drain region 131c refers to a part of the second active layer 131 which is connected to the second drain electrode 133.

The second active layer 131 may be formed of an oxide semiconductor. The oxide semiconductor material may have a large band gap as compared with a silicon material, so that electrons cannot jump over the band gap in an off state. Therefore, the oxide semiconductor material may have a low off-current. Thus, the thin film transistor including an active layer, which is formed of an oxide semiconductor, may be suitable for a switching thin film transistor which maintains on-time to be short and off-time to be long, but is not limited thereto. Depending on the characteristic of the display apparatus, the oxide semiconductor may be applied as a driving thin film transistor. Further, due to the small off-current, a magnitude of an auxiliary capacitance may be reduced so that the oxide semiconductor may be appropriate for a high resolution display element.

For example, the second active layer 131 may be formed of metal oxide, such as various metal oxides including indium-gallium-zinc-oxide (IGZO). Under the assumption that the second active layer 131 of the second thin film transistor 130 is formed of IGZO, among various metal oxides, it has been described that the active layer is formed based on the IGZO layer, but it is not limited thereto. Therefore, the active layer may be formed of another metal oxide such as indium-zinc-oxide (IZO), indium-gallium-tin-oxide (IGTO), or indium-gallium-oxide (IGO), other than IGZO.

The second active layer 131 may be formed by depositing the metal oxide on the second buffer layer 114, performing a heat treatment for stabilization, and then patterning the metal oxide.

An insulating material layer and a metal material layer are formed in this order on the entire surface of the substrate including the second active layer 131, and a photoresist pattern is formed on the metal material layer. The insulating material layer may be formed using a PECVD method, and the metal material layer may be formed using a sputtering method.

The metal material layer is subjected to the wet etching with a photoresist pattern PR as a mask to form a second gate electrode 134. As a wet etchant for etching the metal material layer, a material which selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chrome (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof, (which configure the metal material layer), but does not etch the insulating material layer, may be used.

The insulating material layer is subjected to the dry etching with the photoresist pattern PR and the second gate electrode 134 as masks to form the second gate insulating layer 115.

The insulating material layer is etched by the dry etching process so that a pattern of the second gate insulating layer 115 may be formed on the second active layer 131. A part of the second active layer 131 exposed through the patterned second gate insulating layer 115 may become conductive when the second gate insulating layer 115 is patterned by the dry etching process.

The second active layer 131, which includes a second channel region 131a that does not become conductive, and a second source region 131b and the second drain region 131c that become conductive at both ends of the second active layer 131, may be formed corresponding to the region where the second gate electrode 134 is formed.

Resistance of the second source region 131b and the second drain region 131c of the second active layer 131 that become conductive is lowered so that the element performance of the second thin film transistor 130 may be improved. Accordingly, the reliability of the display apparatus 100 according to the example embodiment of the present disclosure may be improved.

The second channel region 131a of the second active layer 131 may be disposed to overlap the second gate electrode 134. The second source region 131b and the second drain region 131c of the second active layer 131 may be disposed at both sides of the second channel region 131a. Further, the second gate insulating layer 115 may be disposed between the second gate electrode 134 and the second active layer 131. Further, the second gate insulating layer 115 may be disposed so as to overlap the second gate electrode 134 and the second channel region 131a of the second active layer 131.

The second gate insulating layer 115 and the second gate electrode 134 may be formed to have the same pattern by etching the insulating material layer and the metal material layer using the photoresist pattern PR as a mask. The second gate insulating layer 115 may be disposed on the second active layer 131. The second gate insulating layer 115 may be configured by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or a multi-layer thereof. The second gate insulating layer 115 may be patterned to overlap the second channel region 131a of the second active layer 131. The second gate electrode 134 may be disposed on the second gate insulating layer 115. The second gate electrode 134 may be formed of a single layer or a multi-layer formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chrome (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The second gate electrode 134 may be patterned to overlap the second active layer 131 and the second gate insulating layer 115. Furthermore, the second gate electrode 134 may be patterned to overlap the second channel region 131a of the second active layer 131. And, the second gate insulating layer 115 may be patterned to overlap the second channel region 131a of the second active layer 131.

Therefore, the second gate electrode 134 and the second gate insulating layer 115 may overlap the second channel region 131a of the second active layer 131. The second interlayer insulating layer 116 may be disposed on the second buffer layer 114, the second active layer 131, and the second gate electrode 134. A contact hole through which the first active layer 121 of the first thin film transistor 120 and the second active layer 131 of the second thin film transistor 130 are exposed may be formed in the second interlayer insulating layer 116. For example, a contact hole through which the first source region 121b and the first drain region 121c of the first active layer 121 are exposed from the first thin film transistor 120 may be formed in the second interlayer insulating layer 116. Further, a contact hole through which the second source region 131b and the second drain region 131c of the second active layer 131 are exposed from the second thin film transistor 130 may be formed in the second interlayer insulating layer 116. The second interlayer insulating layer 116 may be configured by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or a multi-layer thereof.

A connection electrode 150, the first source electrode 122 and the first drain electrode 123 of the first thin film transistor 120, and the second source electrode 132 and the second drain electrode 133 of the second thin film transistor 130 may be disposed on the second interlayer insulating layer 116.

The first source electrode 122 and the first drain electrode 123 of the first thin film transistor 120 may be connected to the first active layer 121 of the first thin film transistor 120 through the contact holes formed in the first gate insulating layer 112, the first interlayer insulating layer 113, the second buffer layer 114, and the second interlayer insulating layer 116. Therefore, the first source electrode 122 of the first thin film transistor 120 may be connected to the first source region 121b of the first active layer 121 through the contact holes formed in the first gate insulating layer 112, the first interlayer insulating layer 113, the second buffer layer 114, and the second interlayer insulating layer 116. Further, the first drain electrode 123 of the first thin film transistor 120 may be connected to the first drain region 121c of the first active layer 121 through the contact holes formed in the first gate insulating layer 112, the first interlayer insulating layer 113, the second buffer layer 114, and the second interlayer insulating layer 116.

The connection electrode 150 may be electrically connected to the second drain electrode 133 of the second thin film transistor 130. Further, the connection electrode 150 may be electrically connected to the second capacitor electrode 142 of the storage capacitor 140 through the contact holes formed in the second buffer layer 114 and the second interlayer insulating layer 116. Therefore, the connection electrode 150 may serve to electrically connect the second capacitor electrode 142 of the storage capacitor 140 and the second drain electrode 133 of the second thin film transistor 130 to each other.

The second source electrode 132 and the second drain electrode 133 of the second thin film transistor 130 may be connected to the second active layer 131 through the contact hole formed in the second interlayer insulating layer 116. Therefore, the second source electrode 132 of the second thin film transistor 130 may be connected to the second source region 131b of the second active layer 131 through the contact hole formed in the second interlayer insulating layer 116. The second drain electrode 133 of the second thin film transistor 130 may be connected to the second drain region 131c of the second active layer 131 through the contact hole formed in the second interlayer insulating layer 116.

The connection electrode 150, the first source electrode 122 and the first drain electrode 123 of the first thin film transistor 120, and the second source electrode 132 and the second drain electrode 133 of the second thin film transistor 130 may be formed by the same process. Further, the connection electrode 150, the first source electrode 122 and the first drain electrode 123 of the first thin film transistor 120, and the second source electrode 132 and the second drain electrode 133 of the second thin film transistor 130 may be formed of the same material. The connection electrode 150, the first source electrode 122 and the first drain electrode 123 of the first thin film transistor 120, and the second source electrode 132 and the second drain electrode 133 of the second thin film transistor 130 may be formed as a single layer or a multi-layer formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chrome (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the connection electrode 150, the first source electrode 122 and the first drain electrode 123 of the first thin film transistor 120, and the second source electrode 132 and the second drain electrode 133 of the second thin film transistor 130 may be formed by a three-layer structure of titanium (Ti)/aluminum (Al)/titanium (Ti) formed of conductive metal materials, but are not limited thereto.

The connection electrode 150 may be integrally formed to be connected to the second drain electrode 133 of the second thin film transistor 130.

The first planarizing layer 117 may be disposed on the connection electrode 150, the first source electrode 122, and the first drain electrode 123 of the first thin film transistor 120, the second source electrode 132 and the second drain electrode 133 of the second thin film transistor 130, and the second interlayer insulating layer 116. As illustrated in FIG. 1, a contact hole may be formed in the first planarizing layer 117 to expose the second drain electrode 133, but is not limited thereto. For example, a contact hole may be formed in the first planarizing layer 117 to expose the second source electrode 132 of the second thin film transistor 130. Alternatively, a contact hole may be formed in the first planarizing layer 117 to expose the connection electrode 150 which is electrically connected to the second drain electrode 133 of the second thin film transistor 130. The first planarizing layer 117 may be an organic material layer which planarizes and protects upper portions of the first thin film transistor 120 and the second thin film transistor 130. For example, the first planarizing layer 117 may be formed of an organic material such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

The auxiliary electrode 160 may be disposed on the first planarizing layer 117. The auxiliary electrode 160 may be connected to the second drain electrode 133 of the second thin film transistor 130 through the contact hole of the first planarizing layer 117. The auxiliary electrode 160 may serve to electrically connect the second thin film transistor 130 and the first electrode 170 with each other. The auxiliary electrode 160 may be formed of a single layer or a multi-layer formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chrome (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The auxiliary electrode 160 may be formed of the same material as the second source electrode 132 and the second drain electrode 133 of the second thin film transistor 130.

The second planarizing layer 118 may be disposed on the auxiliary electrode 160 and the first planarizing layer 117. Further, as illustrated in FIG. 1, a contact hole may be formed in the second planarizing layer 118 to expose the auxiliary electrode 160. The second planarizing layer 118 may be an organic material layer which planarizes upper portions of the first thin film transistor 120 and the second thin film transistor 130. For example, the second planarizing layer 118 may be formed of an organic material, such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

The first electrode 170 may be disposed on the second planarizing layer 118. The first electrode 170 may be electrically connected to the auxiliary electrode 160 through the contact hole formed in the second planarizing layer 118. Therefore, the first electrode 170 is electrically connected to the auxiliary electrode 160 through the contact hole formed in the second planarizing layer 118 to be electrically connected to the second thin film transistor 130.

The first electrode 170 may be formed to have a multi-layered structure including a transparent conductive layer and an opaque conductive layer having high reflection efficiency. The transparent conductive layer may be formed of a material having a high work function, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The opaque conductive layer may be formed to have a single layer or a multi-layered structure including Al, Ag, Cu, Pb, Mo, Ti, or an alloy thereof. For example, the first electrode 170 may be formed to have a structure in which a transparent conductive layer, an opaque conductive layer, and a transparent conductive layer are sequentially laminated. However, the first electrode 170 is not limited thereto but may also be formed to have a structure in which the transparent conductive layer and the opaque conductive layer are sequentially laminated.

Because the display apparatus 100 according to the example embodiment of the present disclosure is a top emission display apparatus, the first electrode 170 may be an anode electrode. When the display apparatus 100 is a bottom emission type, the first electrode 170 disposed on the second planarizing layer 118 may be a cathode electrode.

A bank 180 may be disposed on the first electrode 170 and the second planarizing layer 118. An opening may be formed in the bank 180 to expose the first electrode 170. Because the bank 180 defines an emission area of the display apparatus 100, the bank 180 may also be referred to as a pixel definition layer. A spacer 190 may be further disposed on the bank 180. Further, an emission structure 200 including a light emitting layer may be further disposed on the first electrode 170.

The emission structure 200 may be formed such that a hole layer, a light emitting layer, and an electron layer are laminated on the first electrode 170 in this order or a reverse order. Further, the emission structure 200 may include first and second emission structures which are opposite to each other with a charge generating layer therebetween. In this case, any one light emitting layer of the first and second emission structures generates blue light and the other one of the first and second emission structures generates yellow-green light so that white light may be generated by the first and the second emission structures. The white light generated in the emission structure 200 is incident onto a color filter (not illustrated) disposed above the emission structure 200 to implement color images. In addition, individual emission structures 200 generate color light corresponding to individual sub pixels without having separate color filters to implement color images. That is, the emission structure 200 of a red R sub pixel generates red light, the emission structure 200 of a green G sub pixel generates green light, and the emission structure 200 of a blue B sub pixel generates blue light.

The second electrode 210 may be further disposed on the emission structure 200. The second electrode 210 may be disposed on the emission structure 200 to be opposite to the first electrode 170 with the emission structure 200 therebetween. In the display apparatus 100 according to the example embodiment of the present disclosure, the second electrode 210 may be a cathode electrode. The encapsulating unit 220 may be further disposed on the second electrode 210 to suppress moisture permeation.

The encapsulating unit 220 may include a first inorganic encapsulating layer 220a, a second organic encapsulating layer 220b, and a third inorganic encapsulating layer 220c. The first inorganic encapsulating layer 220a of the encapsulating unit 220 may be disposed on the second electrode 210. The second organic encapsulating layer 220b may be disposed on the first inorganic encapsulating layer 220a. Further, the third inorganic encapsulating layer 220c may be disposed on the second organic encapsulating layer 220b. The first inorganic encapsulating layer 220a and the third inorganic encapsulating layer 220c of the encapsulating unit 220 may be formed of an inorganic material, such as silicon nitride (SiNx) or silicon oxide (SiOx). The second organic encapsulating layer 220b of the encapsulating unit 220 may be formed of an organic material such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

FIG. 2 is a cross-sectional view of a display apparatus 100 according to another example embodiment of the present disclosure. The display apparatus according to another example embodiment of the present disclosure will be described with reference to FIG. 1 and repeated description will be omitted or briefly described. For example, the substrate 110, the first buffer layer 111, the first gate insulating layer 112, the first interlayer insulating layer 113, the second gate insulating layer 115, the second interlayer insulating layer 116, the first planarizing layer 117, the second planarizing layer 118, the connection electrode 150, the auxiliary electrode 160, the first electrode 170, the bank 180, the spacer 190, the emission structure 200, the second electrode 210, the encapsulating unit 220, the first thin film transistor 120, and the second thin film transistor 130 may be substantially the same. Therefore, repeated description for the configuration of FIG. 2 which is substantially the same as the configuration of FIG. 1 may be omitted or briefly described.

With reference to FIG. 2, a display apparatus 100 according to another example embodiment of the present disclosure includes a substrate 110, a first buffer layer 111, a first thin film transistor 120, a second thin film transistor 130, a first gate insulating layer 112, a first interlayer insulating layer 113, a second buffer layer 114, a second gate insulating layer 115, a second interlayer insulating layer 116, a first planarizing layer 117, a second planarizing layer 118, a storage capacitor 140, a blocking layer 310, a connection electrode 150, a bank 180, an auxiliary electrode 160, a first electrode 170, a spacer 190, an emission structure 200, a second electrode 210, and an encapsulating unit 220. The first active layer 121 of the first thin film transistor 120 may be formed of LTPS and the second active layer 131 of the second thin film transistor 130 may be formed of an oxide semiconductor.

A first polyimide layer 110a and a second polyimide layer 110c of the substrate 110 of the display apparatus 100 contain impurities and a large amount of hydrogen, which affects the characteristics of the oxide semiconductor of the second active layer 131. For example, the large amount of hydrogen remaining in the first polyimide layer 110a and the second polyimide layer 110c diffuses into the second active layer 131 of the second thin film transistor 130, which due to the oxide semiconductor may cause bright dot defects. Polyimide (PI) used for the substrate 110 contains a large amount of hydrogen. Particularly, when the hydrogen generated in the substrate 110 flows into the second channel region 131a of the second active layer 131 which is configured by the oxide semiconductor, the second channel region 131a of the second active layer 131 may become conductive. When the second channel region 131a of the second active layer 131 becomes conductive, the second thin film transistor 130 is turned on at all the times and loses a function as a thin film transistor. The bright dot defects may be caused by the second thin film transistor 130 which loses the function as a thin film transistor and is turned on.

The blocking layer 310 which is integrally formed by extending the second capacitor electrode 142 of the storage capacitor 140 may be disposed to overlap the second channel region 131a of the second active layer 131. The blocking layer 310 may be formed on the first interlayer insulating layer 113. The blocking layer 310 may be disposed below the second active layer 131 and in an area overlapping the second active layer 131. The blocking layer 310 may be disposed below the second active layer 131 and overlaps the second active layer 131 so that the hydrogen generated in the substrate 110 may be suppressed from diffusing to the second active layer 131 of the second thin film transistor 130.

Charges may be charged in the blocking layer 310 which is connected to the second capacitor electrode 142 to be integrally formed. In order to block the charges charged in the blocking layer 310 from being transmitted to the second active layer 131 of the second thin film transistor 130, the second buffer layer 114 may be formed as a multi-layer. When the second buffer layer 114 is formed as a multi-layer, an uppermost layer of the second buffer layer 114 which is in contact with the second active layer 131 may be formed of a silicon oxide (SiOx) material having a low hydrogen content. For example, the uppermost layer of the second buffer layer 114 may be formed of a silicon dioxide (SiO₂) material. Further, at least one silicon nitride (SiNx) material layer having a high insulation property may be disposed between the uppermost layer formed of a silicon oxide (SiOx) material and the blocking layer 310. For example, as illustrated in FIG. 2, when the second buffer layer 114 is formed as a double layer, the second buffer layer 114 may include a second lower buffer layer 114a disposed on the blocking layer 310 and a second upper buffer layer 114b disposed on the second lower buffer layer 114a. The second upper buffer layer 114b which is in direct contact with a lower surface of the second active layer 131 may have a hydrogen content lower than that of the second lower buffer layer 114a. The second lower buffer layer 114a disposed between the blocking layer 310 and the second upper buffer layer 114b may have a higher insulation property than that of the second upper buffer layer 114b. The second upper buffer layer 114b of the second buffer layer 114 which is in direct contact with the second active layer 131 of the second thin film transistor 130 may be formed of silicon oxide (SiOx). For example, the second upper buffer layer 114b may be formed of silicon dioxide (SiO₂). Further, the second lower buffer layer 114a disposed between the second upper buffer layer 114b and the blocking layer 310 may be formed of silicon nitride (SiNx).

The second lower buffer layer 114a which is formed of silicon nitride (SiNx) having a relatively higher insulating property than that of silicon oxide (SiOx) is disposed on the blocking layer 310 so that the charges charged in the blocking layer 310 may be suppressed from being transmitted to the second active layer 131 of the second thin film transistor 130. Further, the second upper buffer layer 114b which is formed of silicon oxide (SiOx) having a relatively lower hydrogen content than that of the silicon nitride (SiNx) may suppress the diffusion of the hydrogen into the second active layer 131 of the second thin film transistor 130.

Therefore, in the display apparatus 100 according to the example embodiment of the present disclosure, the blocking layer 310, which is integrally formed to be connected to the second capacitor electrode 142 to overlap the second active layer 131 of the second thin film transistor 130, is disposed to suppress the diffusion of the hydrogen generated in the substrate 110 to the second active layer 131. Further, the second buffer layer 114 disposed between the blocking layer 310 and the second active layer 131 may be formed as a multi-layer configured by a second upper buffer layer 114b having a relatively low hydrogen content and a second lower buffer layer 114a having a relatively high insulation property. The second upper buffer layer 114b is disposed to be in contact with the lower surface of the second active layer 131 to suppress the diffusion of the hydrogen to the second active layer 131 of the second thin film transistor 130. Further, the second lower buffer layer 114a is disposed between the blocking layer 310 and the second upper buffer layer 114b so that the charges charged in the blocking layer 310 may be suppressed from being transmitted to the second active layer 131 of the second thin film transistor 130. Therefore, the reliability of the display apparatus 100 according to the example embodiment of the present disclosure may be improved.

FIG. 3 is a cross-sectional view of a display apparatus 100 according to another example embodiment of the present disclosure. The display apparatus according to another example embodiment of the present disclosure will be described with reference to FIG. 2 and repeated description will be omitted or briefly described. For example, the substrate 110, the first buffer layer 111, the first gate insulating layer 112, the first interlayer insulating layer 113, the second buffer layer 114, the second gate insulating layer 115, the second interlayer insulating layer 116, the first planarizing layer 117, the second planarizing layer 118, the connection electrode 150, the auxiliary electrode 160, the first electrode 170, the bank 180, the spacer 190, the emission structure 200, the second electrode 210, the encapsulating unit 220, the first thin film transistor 120, and the second thin film transistor 130 may be substantially the same. Therefore, repeated description for the configuration of FIG. 3 which is substantially the same as the configuration of FIG. 2 may be omitted or briefly described.

With reference to FIG. 3, a display apparatus 100 according to another example embodiment of the present disclosure includes a substrate 110, a first buffer layer 111, a first thin film transistor 120, a second thin film transistor 130, a first gate insulating layer 112, a first interlayer insulating layer 113, a second buffer layer 114, a second gate insulating layer 115, a second interlayer insulating layer 116, a first planarizing layer 117, a second planarizing layer 118, a storage capacitor 140, a blocking layer 310, a connection electrode 150, a bank 180, an auxiliary electrode 160, a first electrode 170, a spacer 190, an emission structure 200, a second electrode 210, and an encapsulating unit 220. The first active layer 121 of the first thin film transistor 120 may be formed of LTPS and the second active layer 131 of the second thin film transistor 130 may be formed of an oxide semiconductor.

The display apparatus 100 according to the example embodiment of the present disclosure may further include a blocking layer 310 in an area which overlaps the second active layer 131 of the second thin film transistor 130 to suppress the diffusion of hydrogen which may deteriorate the characteristics of the second thin film transistor 130. The blocking layer 310 may be formed during the process of forming the first capacitor electrode 141 of the storage capacitor 140. Because the blocking layer 310 is formed by the same process as the first capacitor 141 of the storage capacitor 140, the blocking layer 310 may be integrally formed to be connected to the first capacitor electrode 141. For example, as illustrated in FIG. 3, the blocking layer 310 may be formed by extending the first capacitor electrode 141 of the storage capacitor 140 to overlap the second active layer 131 of the second thin film transistor 130. However, the blocking layer 310 is not limited thereto and may be formed to overlap the second active layer 131 of the second thin film transistor 130 and be separated from the first capacitor electrode 141 of the storage capacitor 140. In this case, the blocking layer 310 may be formed on the same layer on which the first capacitor electrode 141 of the storage capacitor 140 is formed. For example, the blocking layer 310 may be formed on the first gate insulating layer 112.

The blocking layer 310, which is integrally formed by extending the first capacitor electrode 141 of the storage capacitor 140, may be disposed to overlap the second channel region 131a of the second active layer 131. The blocking layer 310 may be formed on the first gate insulating layer 112. The blocking layer 310 may be disposed below the second active layer 131 and in an area overlapping the second active layer 131. The blocking layer 310 is disposed below the second active layer 131 and overlaps the second active layer 131 so that the hydrogen generated in the substrate 110 may be suppressed from diffusing to the second active layer 131 of the second thin film transistor 130.

The blocking layer 310 and the first capacitor electrode 141 may be formed by the same process as the second gate electrode 124 of the first thin film transistor 120. The blocking layer 310 and the first capacitor electrode 141 may be formed of the same material as the second gate electrode 124. The blocking layer 310 may be disposed between the substrate 110 and the second active layer 131 to overlap the second active layer 131.

Therefore, in the display apparatus 100 according to the example embodiment of the present disclosure, the blocking layer 310 which is integrally formed to be connected to the first capacitor electrode 141 to overlap the second active layer 131 of the second thin film transistor 130 is disposed to suppress the diffusion of the hydrogen generated in the substrate 110 to the second active layer 131. Therefore, the reliability of the display apparatus 100 according to the example embodiment of the present disclosure may be improved.

FIG. 4 is a cross-sectional view of a display apparatus 100 according to another example embodiment of the present disclosure.

The display apparatus according to another example embodiment of the present disclosure will be described with reference to FIG. 4 and repeated description will be omitted or briefly described. For example, the substrate 110, the first buffer layer 111, the first gate insulating layer 112, the first interlayer insulating layer 113, the second buffer layer 114, the second gate insulating layer 115, the second interlayer insulating layer 116, the first planarizing layer 117, the second planarizing layer 118, the connection electrode 150, the auxiliary electrode 160, the first electrode 170, the bank 180, the spacer 190, the emission structure 200, the second electrode 210, the encapsulating unit 220, the first thin film transistor 120, and the second thin film transistor 130 may be substantially the same. Therefore, repeated description for the configuration of FIG. 4 that is substantially the same as the configuration of FIG. 2 may be omitted or briefly described.

With reference to FIG. 4, a display apparatus 100 according to another example embodiment of the present disclosure includes a substrate 110, a first buffer layer 111, a first thin film transistor 120, a second thin film transistor 130, a first gate insulating layer 112, a first interlayer insulating layer 113, a second buffer layer 114, a second gate insulating layer 115, a second interlayer insulating layer 116, a first planarizing layer 117, a second planarizing layer 118, a storage capacitor 140, a blocking layer 310, a connection electrode 150, a bank 180, an auxiliary electrode 160, a first electrode 170, a spacer 190, an emission structure 200, a second electrode 210, and an encapsulating unit 220. The first active layer 121 of the first thin film transistor 120 may be formed of LTPS and the second active layer 131 of the second thin film transistor 130 may be formed of an oxide semiconductor.

The display apparatus 100 according to the example embodiment of the present disclosure may further include the blocking layer 310 in an area which overlaps the second active layer 131 of the second thin film transistor 130 to suppress the diffusion of hydrogen, which may deteriorate the characteristics of the second thin film transistor 130. The blocking layer 310 may include a first blocking layer 311 and a second blocking layer 312 disposed below the first blocking layer 311. The first blocking layer 311 may be formed during the process of forming the second capacitor electrode 142 of the storage capacitor 140. The second blocking layer 312 may be formed during the process of forming the first capacitor electrode 141 of the storage capacitor 140. Because the first blocking layer 311 is formed by the same process as the second capacitor electrode 142 of the storage capacitor 140, the first blocking layer 311 may be integrally formed to be connected to the second capacitor electrode 142. Because the second blocking layer 312 is formed by the same process as the first capacitor electrode 141 of the storage capacitor 140, the second blocking layer 312 may be integrally formed to be connected to the first capacitor electrode 141. For example, as illustrated in FIG. 4, the first blocking layer 311 may be formed by extending the second capacitor electrode 142 of the storage capacitor 140 to overlap the second active layer 131 of the second thin film transistor 130. Further, the second blocking layer 312 may be formed by extending the first capacitor electrode 141 of the storage capacitor 140 to overlap the second active layer 131 of the second thin film transistor 130. The first blocking layer 311 and the second blocking layer 312 may be disposed to overlap each other to form a capacitor. However, the first blocking layer 311 and the second blocking layer 312 are not limited thereto, and may be formed to overlap the second active layer 131 of the second thin film transistor 130 and be electrically separated from the second capacitor electrode 142 and the first capacitor electrode 141 of the storage capacitor 140.

The second blocking layer 312, which is integrally formed by extending the first capacitor electrode 141 of the storage capacitor 140, and the first blocking layer 311, which is integrally formed by extending the second capacitor electrode 142 of the storage capacitor 140, may be disposed to overlap the second channel region 131a of the second active layer 131. The first blocking layer 311 may be disposed on the first interlayer insulating layer 113 and the second blocking layer 312 may be disposed on the first gate insulating layer 112. The first blocking layer 311 and the second blocking layer 312 may be disposed below the second active layer 131 and in an area overlapping the second active layer 131. The first blocking layer 311 may be disposed between the second active layer 131 and the second blocking layer 312, and the second blocking layer 312 may be disposed between the first blocking layer 311 and the substrate 110. Further, the first blocking layer 311 and the second blocking layer 312 may be disposed to overlap each other. Further, the first blocking layer 311 and the second blocking layer 312 may be disposed to overlap the second active layer 131. The first blocking layer 311 and the second blocking layer 312 are disposed below the second active layer 131 and overlap the second active layer 131 so that the hydrogen generated in the substrate 110 may be suppressed from diffusing to the second active layer 131 of the second thin film transistor 130.

The second blocking layer 312 and the first capacitor electrode 141 may be formed by the same process as the first gate electrode 124 of the first thin film transistor 120. The second blocking layer 312 and the first capacitor electrode 141 may be formed of the same material as the first gate electrode 124.

Charges may be charged in the first blocking layer 311, which is connected to the second capacitor electrode 142 to be integrally formed. In order to block the charges charged in the first blocking layer 311 from being transmitted to the second active layer 131 of the second thin film transistor 130, the second buffer layer 114 may be formed as a multi-layer. When the second buffer layer 114 is formed as a multi-layer, an uppermost layer of the second buffer layer 114 which is in contact with the second active layer 131 may be formed of a silicon oxide (SiOx) material having a low hydrogen content. For example, the uppermost layer of the second buffer layer 114 may be formed of a silicon dioxide (SiO₂) material. Further, at least one silicon nitride (SiNx) material layer having a high insulation property may be disposed between the uppermost layer formed of a silicon oxide (SiOx) material and the first blocking layer 311. For example, as illustrated in FIG. 4, when the second buffer layer 114 is formed as a double layer, the second buffer layer 114 may include a second lower buffer layer 114a disposed on the first blocking layer 311 and a second upper buffer layer 114b disposed on the second lower buffer layer 114a. The second upper buffer layer 114b, which is in direct contact with a lower surface of the second active layer 131, may have a hydrogen content lower than that of the second lower buffer layer 114a. The second lower buffer layer 114a disposed between the first blocking layer 311 and the second upper buffer layer 114b may have a higher insulation property than that of the second upper buffer layer 114b. The second upper buffer layer 114b of the second buffer layer 114, which is in direct contact with the second active layer 131 of the second thin film transistor 130, may be formed of silicon oxide (SiOx). For example, the second upper buffer layer 114b may be formed of silicon dioxide (SiO₂). Further, the second lower buffer layer 114a disposed between the second upper buffer layer 114b and the first blocking layer 311 may be formed of silicon nitride (SiNx).

The second lower buffer layer 114a, which is formed of silicon nitride (SiNx) having a relatively higher insulating property than that of silicon oxide (SiOx), is disposed on the first blocking layer 311 so that the charges charged in the first blocking layer 311 may be suppressed from being transmitted to the second active layer 131 of the second thin film transistor 130. Further, the second upper buffer layer 114b, which is formed of silicon oxide (SiOx) having a relatively lower hydrogen content than that of the silicon nitride (SiNx), may suppress the diffusion of the hydrogen into the second active layer 131 of the second thin film transistor 130.

Therefore, in the display apparatus 100 according to the example embodiment of the present disclosure, the first blocking layer 311 and the second blocking layer 312, which are integrally formed to be connected to the second capacitor electrode 142 and the first capacitor electrode 141 to overlap the second active layer 131 of the second thin film transistor 130, are disposed to suppress the diffusion of the hydrogen generated in the substrate 110 to the second active layer 131. Further, the second buffer layer 114 disposed between the first blocking layer 311 and the second active layer 131 may be formed as a multi-layer configured by the second upper buffer layer 114b having a relatively low hydrogen content and the second lower buffer layer 114a having a relatively high insulation property. The second upper buffer layer 114b is disposed to be in contact with the lower surface of the second active layer 131 to suppress the diffusion of the hydrogen to the second active layer 131 of the second thin film transistor 130. Further, the second lower buffer layer 114a is disposed between the first blocking layer 311 and the second upper buffer layer 114b so that the charges charged in the first blocking layer 311 may be suppressed from being transmitted to the second active layer 131 of the second thin film transistor 130. Therefore, the reliability of the display apparatus 100 according to the example embodiment of the present disclosure may be improved.

FIG. 5 is a cross-sectional view of a display apparatus 100 according to another example embodiment of the present disclosure.

The display apparatus according to another example embodiment of the present disclosure will be described with reference to FIG. 5 and repeated description will be omitted or briefly described. For example, the substrate 110, the first buffer layer 111, the first gate insulating layer 112, the first interlayer insulating layer 113, the second buffer layer 114, the second gate insulating layer 115, the second interlayer insulating layer 116, the first planarizing layer 117, the second planarizing layer 118, the auxiliary electrode 160, the first electrode 170, the bank 180, the spacer 190, the emission structure 200, the second electrode 210, the encapsulating unit 220, the blocking layer 310, the storage capacitor 140, and the second thin film transistor 130 may be substantially the same. Therefore, repeated description for the configuration of FIG. 5 which is substantially the same as the configuration of FIG. 2 may be omitted or briefly described.

With reference to FIG. 5, a display apparatus 100 according to another example embodiment of the present disclosure includes a substrate 110, a first buffer layer 111, a first thin film transistor 120, a second thin film transistor 130, a first gate insulating layer 112, a first interlayer insulating layer 113, a second buffer layer 114, a second gate insulating layer 115, a second interlayer insulating layer 116, a first planarizing layer 117, a second planarizing layer 118, a storage capacitor 140, a blocking layer 310, a connection electrode 150, a bank 180, an auxiliary electrode 160, a first electrode 170, a spacer 190, an emission structure 200, a second electrode 210, and an encapsulating unit 220. The first active layer 121 of the first thin film transistor 120 may be formed of LTPS and the second active layer 131 of the second thin film transistor 130 may be formed of an oxide semiconductor.

In the display apparatus 100 according to another example embodiment of the present disclosure, the connection electrode 150 may include a first connection electrode 151 and a second connection electrode 152 disposed on the first connection electrode 151. Further, the display apparatus 100 may further include an auxiliary interlayer insulating layer 119 disposed between the second buffer layer 114 and the second capacitor electrode 142.

Further, a first source electrode 122 and a first drain electrode 123 of the first thin film transistor 120 may be disposed below the second buffer layer 114. For example, as illustrated in FIG. 5, the auxiliary interlayer insulating layer 119 may be disposed on the second capacitor electrode 142 of the storage capacitor 140 and the first blocking layer 311 of the blocking layer 310. In the auxiliary interlayer insulating layer 119, a contact hole may be formed. And, the first source electrode 122 and the first drain electrode 123 of the first thin film transistor 120 are connected to the first source region 121b and the first drain region 121c of the first active layer 121 of the first thin film transistor 120 through the contact hole, respectively. Further, in the auxiliary interlayer insulating layer