1 to TX4 may be commonly connected to the single floating diffusion region FD connecting the fourth floating diffusion regions FD1 to FD4 to each other.

The pixel circuit may include a reset transistor RX, first and second driving transistors DX1 and DX2, and a select transistor SX. The reset transistor RX may be controlled by a reset control signal input to the reset gate RG, and the select transistor SX may be controlled by a select control signal input to the select gate SEL. For example, each of the four pixels PX may further include a single transistor, other than the transfer transistor TX. Among the four additional transistors included in the four pixels, two transistors may be connected in parallel to each other to provide first and second driving transistors DX1 and DX2, and one of the remaining two transistors may be provided as a select transistor SX and the other transistor thereof may be configured to provide a reset transistor RX.

The pixel circuit described with reference to FIG. 3B is only an example, and the inventive concepts are not limited to a type of pixel circuit as shown. For example, one of the four additional transistors other than the transfer transistors TX may be assigned as a driving transistor and another transistor thereof may be assigned as a select transistor. In addition, the remaining two transistors may be connected in series to be assigned as first and second reset transistors, and thus an image sensor for adjusting a conversion gain of a pixel may be implemented. Alternatively, the pixel circuit may vary depending on the number of transistors included in each of the pixels PX.

Hereinafter, an image sensor 1 according to example embodiments will be described with reference to FIGS. 4, 5, 6A, 6B, 7A, and 7B.

FIGS. 4 and 5 are schematic plan views of an image sensor according to embodiments of the inventive concepts. FIG. 4 illustrates a plan view of a unit region, and shows a portion of the first pixel region PA1 of the upper chip CH_U of FIG. 2. FIG. 5 illustrates a plan view of a unit region, and shows a portion of the second pixel region PA2 of the first lower chip CH_L1 of FIG. 2.

FIGS. 6A and 6B illustrate schematic cross-sectional views of an image sensor according to embodiments of the inventive concepts. FIG. 6A illustrates a cross-sectional view taken along line I-f of FIGS. 4 and 5, and FIG. 6B illustrates a cross-sectional view taken along line II-If of FIGS. 4 and 5.

FIGS. 7A and 7B illustrate partially enlarged views of an image sensor according to embodiments of the inventive concepts. FIG. 7A illustrates an enlarged view of region “A” of FIG. 6A, and FIG. 7B illustrates an enlarged view of region “B” of FIG. 6B.

Referring to FIGS. 4, 5, 6A, 6B, 7A, and 7B, an image sensor 1 according to example embodiments may include a first chip structure 100 including a first substrate 101, a second chip structure 200 including a second substrate 201, and a third chip structure 300 including a third substrate 301. The second chip structure 200 may be disposed on the first chip structure 100, and the third chip structure 300 may be disposed on the second chip structure 200. In an example embodiment, the first chip structure 100 may be a logic chip, and the second and third chip structures 200 and 300 may be image sensor chips including a plurality of pixels PX. The first chip structure 100 may be the second lower chip CH_L2 of FIG. 2, the second chip structure 200 may be the first lower chip CH_L1 of FIG. 2, and the third chip structure 300 may be the upper chip CH_U of FIG. 2. Similarly to that described with reference to FIGS. 2 and 3, the second chip structure 200 may include a reset transistor RX, a select transistor SX, and a driving transistor DX, and the third chip structure 300 may include a transfer transistor TX.

According to example embodiments, the first chip structure 100 may be a multilayer chip structure including a logic chip and a memory chip.

The first chip structure 100 of the image sensor 1 according to example embodiments may include a first isolation layer 107 defining an active region in the first substrate 101, first circuit devices 110 on the first substrate 101, a first wiring structure 120 electrically connected to the first circuit devices 110, a first bonding structure 130 on the first wiring structure 120, and a first insulating layer 180 covering the first circuit devices 110 and the first wiring structure 120 on the first substrate 101, in addition to the first substrate 101.

The first substrate 101 may be a semiconductor substrate. For example, the first substrate 101 may be a substrate formed of a semiconductor material, such as a single-crystalline silicon substrate. The first circuit devices 110 may include devices such as transistors including a first gate electrode 115 and a first source/drain region 113.

The first wiring structure 120 may apply electrical signals to the first circuit devices 110. The first wiring structure 120 may be electrically connected to the first source/drain region 113, and may also be electrically connected to the first gate electrode 115 in a region not illustrated. The first wiring structure 120 may include lower interconnection lines 121 and 123 disposed as a plurality of layers, and lower vias 122 and 124 disposed between the lower interconnection lines 121 and 123 or between the lower interconnection lines 121 and 123 and the first substrate 101. Each of the lower vias 122 and 124 may have a columnar shape and may have an inclined side surface having a width decreasing in a direction toward the first substrate 101.

In an example embodiment, the first wiring structure 120 may include the first lower interconnection line 121 on (or over) the first substrate 101, the first lower via 122 between the first lower interconnection line 121 and the first substrate 101, the second lower interconnection line 123 on (or over) the first lower interconnection line 121, and the second lower via 124 between first lower interconnection line 121 and second lower interconnection line 123. However, the number of interconnection lines constituting the first wiring structure 120, the number of vias, and an arrangement relationship of the interconnection lines may vary according to example embodiments.

The first bonding structure 130 may be electrically connected to the first wiring structure 120 on the first wiring structure 120. The first bonding structure 130 may include a metal material such as copper (Cu). The first bonding structure 130 may include a lower bonding pad 131 and a first bonding via 132 electrically connected to the first bonding pad 131. The first bonding pad 131 and the first bonding via 132 may be separately formed by a single damascene process, or may be integrally formed by a dual damascene process. The first bonding pad 131 of the first chip structure 100 may serve as a bonding layer to the second chip structure 200, and may provide an electrical connection path to the second chip structure 200. The first bonding pads 131 may be provided in plural. For example, a portion or some of the first bonding pads 131 may not be connected to an underlying first wiring structure 120 and may be disposed for only bonding, as illustrated in FIG. 6A.

The first insulating layer 180 may cover a portion of the first bonding structure 130 while covering the first circuit devices 110 and the first wiring structure 120. The first insulating layer 180 may expose an upper surface of the first bonding pad 131 while covering a lower surface and side surfaces of the first bonding pad 131. For example, an upper surface of the first insulating layer 180 may be coplanar with an upper surface of the first bonding pad 131 or substantially coplanar with an upper surface of the first bonding pad 131. In an example embodiment, the first insulating layer 180 may include a bonding insulating layer (not shown) having a predetermined thickness from the upper surface. The bonding insulating layer may be a layer for dielectric-to-dielectric bonding to the bonding insulating layer of the second chip structure 200. The bonding insulating layer may serve as a diffusion barrier layer of the first bonding pad 231 and may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, or SiOCN.

The second chip structure 200 of the image sensor 1 according to example embodiments may include a second substrate 201 having a first surface S1 facing the first chip structure 100 and a second surface S2 opposing the first surface S1 (see FIG. 7A), a second isolation layer 207 defining the active region ACT in the second substrate 201, second circuit devices 210 on the first surface S1 of the second substrate 201, a second wiring structure 220 electrically connected to the second circuit devices 210, a second lower bonding structure 230 on (or over) the first surface S1 of the second substrate 201, a second upper bonding structure 240 on the second surface S2 of the second substrate 201, a second lower insulating layer 280 on the first surface S1 of the second substrate 201, and a second upper insulating layer 290 on the second surface S2 of the second substrate 201.

The second substrate 201 may be a semiconductor substrate. For example, the second substrate 201 may be a substrate formed of a semiconductor material, for example, a single-crystalline silicon substrate. In the present specification, the second substrate 201 may be referred to as a “lower substrate.”

Referring to FIGS. 5 and 6A, the active region ACT may be defined by the second isolation layer 207 in the second substrate 201. The second source/drain region 213 may be a doped region formed in the active region ACT. In an example embodiment, a portion of a regions partitioned by the second isolation layer 207 may be dummy active regions which do not constitute a transistor. For example, the dummy active region may include a region adjacent to a region in which a landing structure 245 or a third bonding via 242 is formed.

The second circuit devices 210 may include a device such as a transistor including a second gate electrode 215 and a second source/drain region 213. The second gate electrode 215 may include a semiconductor material such as silicon, germanium, or a combination thereof. The second gate electrode 215 may include an N-type or P-type doped layer. Alternatively, the second gate electrode 215 may include an undoped layer. In an example embodiment, the second circuit devices 210 may include a first intermediate device 211, a second intermediate device 212, and a third intermediate device 214 (e.g., see FIG. 5). The first intermediate device 211 may be one of the driving transistors DX1 and DX2 of FIG. 3B, the second intermediate device 212 may be the reset transistor RX of FIG. 3B, and the third intermediate device 214 may be the select transistor SX of FIG. 3B. However, the type and disposition relationship of the second circuit devices 210 may vary. In the present specification, the second circuit devices 210 may be referred to as “lower circuit devices.”

The second wiring structure 220 may be disposed between the second substrate 201 and the first chip structure 100. The second wiring structure 220 may apply electrical signals to the second circuit devices 210. The second wiring structure 220 may be electrically connected to the second source/drain region 213, and may also be electrically connected to the second gate electrode 215 in a region not illustrated. The second wiring structure 220 may include intermediate interconnection lines 221, 223, and 225 disposed as a plurality of layers, and intermediate vias 222, 224, and 226 disposed between the intermediate interconnection lines 221, 223, and 225 or between the intermediate lines 221, 223, and 225 and the second substrate 201. Each of the intermediate vias 222, 224, and 226 may have a columnar shape and may have an inclined side surface having a width decreasing in a direction toward the second substrate 201. In this case, a direction in which side surfaces of the intermediate vias 222, 224 and 226 are inclined may be different from the direction in which the side surfaces of the lower vias 122 and 124 are inclined. However, according to example embodiments, the intermediate vias 222, 224, and 226 and the lower vias 122 and 124 may have side surfaces vertically extending while having a constant width.

In an example embodiment, the second wiring structure 220 may include a first intermediate interconnection line 221 on (or over) the first surface S1 of the second substrate 201, a first intermediate via 222 between the first intermediate interconnection line 221 and the second substrate 201, a second intermediate interconnection line 223 below the first intermediate interconnection line 221, a second intermediate via 224 between the first intermediate interconnection line 221 and the second intermediate interconnection line 223, a third intermediate interconnection line 225 below the second intermediate interconnection line 223, and a third intermediate via 226 between the second intermediate interconnection line 223 and the third intermediate interconnection line 225. However, the number of interconnection lines and vias constituting the second wiring structure 220 may vary according to example embodiments. In the present specification, the second wiring structure 220 may be referred to as a “lower wiring structure.”

In an example embodiment, the second chip structure 200 may further include first and second insulating liners 281 and 282. The first insulating liner 281 may be conformally formed on the first surface S1 of the second substrate 201. The second insulating liner 282 may be disposed between the first insulating liner 281 and the second gate electrode 215, and the second lower insulating layer 280. The second insulating liner 282 may be disposed between the landing structure 245 and the second lower insulating layer 280. For example, the first insulating liner 281 may include a silicon oxide or a low dielectric material, and the second insulating liner 282 may include a silicon nitride. A portion of the first insulating liner 281 may serve as a gate dielectric layer of the second circuit devices 210, and the first and second insulating liners 282 may serve as an etch-stop layer of the second wiring structure 220.

The second lower bonding structure 230 may be electrically connected to the second wiring structure 220 below the second wiring structure 220. The second lower bonding structure 230 may be a structure for bonding to the first chip structure 100. The second lower bonding structure 230 may include a metal material such as copper (Cu). The second lower bonding structure 230 may include a second bonding pad 231 and a second bonding via 232 electrically connected to the second bonding pad 231. The second bonding pad 231 and the second bonding via 232 may be separately formed by a single damascene process, or may be integrally formed by a dual damascene process. The second bonding pad 231 of the second chip structure 200 may be in contact with the first bonding pad 131 of the first chip structure 100. The second bonding pad 231 may serve as a bonding layer and may provide an electrical connection path to the first chip structure 100. The second bonding pad 231 may be provided in plural. For example, as illustrated in FIG. 6A, a portion or some of the second bonding pads 231 may be disposed only for bonding without being electrically connected to the upper second wiring structure 220.

The second lower insulating layer 280 may cover a portion of the second lower bonding structure 230 while covering the second circuit devices 210 and the second wiring structure 220 on the first surface S1 of the second substrate 201. The second lower insulating layer 280 may expose a lower surface of the second bonding pad 231 while covering upper and side surfaces of the second bonding pad 231. For example, a lower surface of the second lower insulating layer 280 may be substantially coplanar with the lower surface of the second bonding pad 231. In an example embodiment, the second lower insulating layer 280 may include a bonding insulating layer (not shown) having a predetermined thickness from the lower surface thereof. The insulating bonding layer may be a layer for dielectric-to-dielectric bonding to the insulating bonding layer of the first chip structure 100.

The second upper bonding structure 240 may be a structure for bonding to the third chip structure 300. The second upper bonding structure 240 may include a third bonding pad 241 on (or over) the second surface S2 of the second substrate 201 and a landing structure 245 disposed on the first surface S1 of the second substrate 201, and a third bonding via 242 disposed between the third bonding pad 241 and the landing structure 245. The third bonding pad 241 may include a metal material such as copper (Cu), and the third bonding via 242 may include a metal material such as copper (Cu) or tungsten (W). The third bonding pad 241 may include the same metal material as the third bonding via 242, but example embodiments are not limited thereto.

The third bonding pad 241 may be spaced apart from the second substrate 201 on the second surface S2 of the second substrate 201. The third bonding via 242 may be a through-via penetrating through the second substrate 201. An upper end of the third bonding via 242 may be in contact with the third bonding pad 241, and a lower end of the third bonding via 242 may be in contact with the landing structure 245. In the present specification, a “lower end” may refer to one end in a direction toward the first substrate 101, and an “upper end” may refer to one end in a direction away from the first substrate 101. The upper end of the third bonding via 242 may be disposed at a level higher than a level of the second surface S2 of the second substrate 201, and the lower end of the third bonding via 242 may be disposed at a level higher than a level of the lower end of the first intermediate via 222. In the present specification, a “level” may refer to a distance from an upper surface of the first substrate 101. A lower end of the third bonding via 242 may be disposed at a level higher than a level of a lower surface of the second gate electrode 215. The third bonding via 242 may have a columnar shape having a side surface extending vertically and having a constant width. However, according to example embodiments, the third bonding via 242 may have a shape in which a width decreases in a direction toward the end upper end from the lower end, and may have a pillar shape having an inclined side surface. In the present specification, the third bonding pad 241 may be referred to as a “lower bonding pad” and the third bonding via 242 may be referred to as a “lower bonding via”.

In an example embodiment, the second upper bonding structure 240 may further include an insulating spacer 244 between the third bonding via 242 and the second substrate 201. The third bonding via 242 may be spaced apart from the second substrate 201 by the insulating spacer 244. An external side surface of the insulating spacer 244 may be surrounded by the second substrate 201, and a lower surface of the insulating spacer 244 may be covered with the landing structure 245. A lower surface of the insulating spacer 244 may be coplanar with the first surface S1 of the second substrate 201.

As illustrated in FIG. 5, the landing structure 245 may have a planar area larger than a planar area of the third bonding via 242. In an example embodiment, the landing structure 245 may have a planar area larger than a planar area of the third bonding pad 241. However, example embodiments are not limited thereto, and the land structure 245 may have a planar area smaller than a planar area of the third bonding pad 241.

The landing structure 245 may be disposed at a level higher than a level of the first intermediate interconnection line 221. For example, the landing structure 245 may be disposed to be closer to the second substrate 201 than to the first intermediate interconnection line 221. A lower surface of the landing structure 245 may be disposed at a level higher than a level of a lower surface of the first intermediate via 222. The landing structure 245 may include a portion overlapping at least a portion of the second circuit devices 210 in a horizontal direction. In an example embodiment, the landing structure 245 may be disposed to be parallel to the second circuit devices 210 on the same level as the second gate electrode 215 of the second circuit devices 210 or on substantially the same level as the second gate electrode 215 of the second circuit devices 210. Accordingly, a length of the landing structure 245 may be the same as a length of the second gate electrode 215 of the second circuit devices 210 in a vertical direction perpendicular to the first substrate 101, or may be substantially the same as a length of the second gate electrode 215 of the second circuit devices 210 in a vertical direction perpendicular to the first substrate 101. For example, a thickness of the landing structure 245 and a thickness of the second circuit devices 210 in the vertical direction may be substantially the same.

The landing structure 245 may include a semiconductor material. The landing structure 245 may include the same material as the second gate electrode 215 of each of the second circuit devices 210. The landing structure 245 may include, for example, polycrystalline silicon.

The landing structure 245 may be a region formed in the same process as the second gate electrode 215 of the second circuit devices 210 and separated from the second circuit devices 210 by patterning. Accordingly, the landing structure 245 may have the same material and the same height as the second gate electrode 215.

In an example embodiment, the landing structure 245 may be spaced apart from the second circuit devices 210, but example embodiments are not limited thereto.

Referring to FIGS. 5, 6A, and 6B, the landing structure 245 is disposed on a level different from a level of the first intermediate interconnection line 221, for example a level higher than a level of the first intermediate interconnection line 221, so that a degree of freedom in wiring of the first intermediate interconnection line 221 may be improved. The degree of freedom in wiring may refer to, for example, a degree of closeness between wirings in a layout operation for wiring arrangement or a process margin in an operation for wiring formation. Accordingly, the image sensor 1 having an increased degree of integration may be realized in accordance with embodiments of the inventive concepts.

In the image sensor 1 according to example embodiments, the landing structure 245 may be disposed on a level different from a level of the first intermediate interconnection line 221, to thus reduce parasitic capacitance which may be formed in cases that the landing structure 245 is formed at the same level as the intermediate interconnection line 221. For example, an image sensor 1 having improved electrical characteristics may be provided using the landing structure 245 according to the present embodiment, rather than a landing wire disposed at the same level as the first intermediate interconnection line 221 and having a plane area corresponding to the area of the landing structure 245 of FIG. 5. In addition, the lower end of the third bonding via 242 may be disposed at a level higher than a level of the first intermediate interconnection line 221, to thus reduce parasitic capacitance between the third bonding via 242 and the second wiring structure 220. Accordingly, the image sensor 1 having improved electrical characteristics may be provided.

The second upper insulating layer 290 may cover the second substrate 201 on the second surface S2 of the second substrate 201. The second upper insulating layer 290 may expose an upper surface of the third bonding pad 241 while covering the lower and side surfaces of the third bonding pad 241. For example, an upper surface of the second upper insulating layer 290 may be substantially coplanar with the upper surface of the third bonding pad 241. In an example embodiment, the third lower insulating layer 290 may include a bonding insulating layer (not shown) having a predetermined thickness from the upper surface thereof. The bonding insulating layer may be a layer for dielectric-to-dielectric bonding to the bonding insulating layer of the third chip structure 300.

The third chip structure 300 of the image sensor 1 according to example embodiments may include the third substrate 301 having a third surface facing the second chip structure 200 and a fourth surface opposing the third surface, a third isolation layer 307 disposed on the third surface of the third substrate 301 and defining an active region, third circuit devices 310 disposed on the third surface of the third substrate 301, a third wiring structure 320 electrically connected to the third circuit devices 310, a third bonding structure 340 below the third wiring structure 320, and a third insulating layer 380 covering the third circuit devices 310 and the third wiring structure 320 between the third surface of the third substrate 301 and the second chip structure 200.

In an example embodiment, the third chip structure 300 may include a horizontal insulating layer 391 disposed on the fourth surface of the third substrate 301, a grid pattern 392 on the horizontal insulating layer 391, horizontal color filters 393 covering the insulating layer 391 and the grid pattern 392, and microlenses 395 on the color filters 393.

The third substrate 301 may be a semiconductor substrate. For example, the third substrate 301 may be a substrate formed of a semiconductor material, for example, a single-crystalline silicon substrate. The third surface of the third substrate 301 may be in contact with the third insulating layer 380.

Photoelectric conversion devices PD may be disposed in the third substrate 301. The photoelectric conversion devices PD may generate and accumulate charges corresponding to incident light. For example, the photoelectric conversion devices PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), and/or a combination thereof. In the present specification, the third substrate 301 may also be referred to as an “upper substrate.”

In an example embodiment, the third chip structure 300 may further include a separation structure PI. The separation structure PI may be disposed to surround each of the photoelectric conversion devices PD. At least a portion of the separation structure PI may penetrate through the third substrate 301. In some embodiments the separation structure PI may be connected to the third isolation layer 307. The separation structure PI may include a separation pattern of polycrystalline silicon and a separation insulating layer of a silicon oxide surrounding side surfaces of the separation pattern, but materials forming the separation structure PI and the number of layers thereof are not limited thereto and may vary according to example embodiments.

The third isolation layer 307 may be disposed on the third surface of the third substrate 301 and may define an active region. A portion of the active region may include a floating diffusion region FD. The floating diffusion region FD may perform functions the same as or similar to the functions of the floating diffusion region FD of FIG. 3B.

Each of the third circuit devices 310 may include a third gate electrode 315 and a gate dielectric layer 312 between the third gate electrode and the third substrate 301. Each of the third circuit devices 310 may transfer charges from an adjacent photoelectric conversion device PD to an adjacent floating diffusion region PD. In an example embodiment, each of the third circuit devices 310 may be the transfer transistor TX of FIG. 3B. In the present specification, the third circuit devices 310 may be referred to as “upper circuit devices.”

The third wiring structure 320 may apply electrical signals to the third circuit devices 310. The third wiring structure 320 may include upper interconnection lines 321 and 323 and upper vias 322 and 324 disposed on different height levels. The upper vias 322 and 324 may have a column shape. Each of the upper vias 322 and 324 may have an inclined side surface having a width decreasing in a direction toward the third substrate 301, but may have a side surface extending vertically with a constant width.

In an example embodiment the third wiring structure 320 may include a first upper interconnection line 321 on (or over) the third surface of the third substrate 301, a first upper via 322 between the first upper interconnection line 321 and the third substrate 301, a second upper interconnection line 323 below the first upper interconnection line 321, and a second upper via 324 between the first upper interconnection line 321 and the second upper interconnection line 323. However, the number of interconnection lines and vias constituting the third wiring structure 320 may vary according to example embodiments. In the present specification, the third wiring structure 320 may be referred to as an “upper wiring structure.”

The third bonding structure 340 may be electrically connected to the third wiring structure 320 below the third wiring structure 320. The third bonding structure 340 may be a structure for bonding to the second chip structure 200. The third bonding structure 340 may include a fourth bonding pad 341 and a fourth bonding via 342 electrically connected to the fourth bonding pad 341. The fourth bonding pad 341 may include a metal material such as copper (Cu), and the fourth bonding via 342 may include a metal material such as copper (Cu) or tungsten (W). The fourth bonding pad 341 may include the same metal material as the fourth bonding via 342, but example embodiments are not limited thereto. In the present specification, the fourth bonding pad 341 may be referred to as an “upper bonding pad” and the fourth bonding via 342 may be referred to as an “upper bonding via.”

The fourth bonding pad 341 may be in contact with the third bonding pad 241. The fourth bonding pad 341 may serve as a bonding layer and may provide an electrical connection path to the second chip structure 200.

The third insulating layer 380 may cover a portion of the third bonding structure 340 while covering the third circuit devices 310 and the third wiring structure 320 on the third surface of the third substrate 301. The third insulating layer 380 may expose a lower surface of the fourth bonding pad 341 while covering upper and side surfaces of the fourth bonding pad 341. In an example embodiment, the third insulating layer 380 may include a bonding insulating layer having a predetermined thickness from a lower surface thereof.

The horizontal insulating layer 391 may cover the third substrate 301 on the fourth surface of the third substrate 301. The horizontal insulating layer 391 may cover the separation structure PI.

In an example embodiment, the horizontal insulating layer 391 may include a plurality of layers (not shown) stacked sequentially. The horizontal insulating layer 391 may include an antireflection layer for preventing reflection of light which may occur due to a rapid change in refractive index on the fourth surface of the third substrate 301 which may be formed of silicon. For example, the horizontal insulating layer 391 may include at least two layers, among an aluminum oxide layer, a hafnium oxide layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon nitride layer. For example, the horizontal insulating layer 391 may include first to fourth layers stacked sequentially. The first layer may be an aluminum oxide layer, each of the second and fourth layers may be a hafnium oxide layer, and the third layer may be a silicon oxide layer.

The grid pattern 392 may be disposed on the horizontal insulating layer 391. In plan view, the grid pattern 392 may be disposed between the plurality of pixels PX. At least a portion of the grid pattern 392 may vertically overlap the separation structure PI. The grid pattern 392 may include an oxide or nitride including an insulating material such as a low refractive index (LRI) material such as Si, Al, or a combination thereof. Also, the grid pattern 392 may include a porous silicon oxide or silica nanoparticles having a network structure.

The color filters 393 may be disposed on the horizontal insulating layer 391 to cover the horizontal insulating layer 391 and the grid pattern 392. The color filters 393 may pass light having a specific wavelength to reach the photoelectric conversion devices PD. Each of the color filters 393 may vertically overlap each of the pixels PX. The color filters 393 may be formed of, for example, a material obtained by mixing a resin with a pigment containing a metal or a metal oxide.

The color filters 393 may include first to third color filters including color filters 393a and 393b shown in FIGS. 6A and 6B, and third color filters (not shown), having different colors. The first to third color filters including color filters 393a and 393b, and the third color filters (not shown), may include first color filters 393a having a first color, second color filters 393b having a second color different from the first color, and third color filters having a third color different from the first and second colors. For example, the first color may be a green color, the second color may be a red color, and the third color may be a blue color.

The microlenses 395 may be disposed on the color filters 393. Each of the microlenses 395 may have a convex shape in a direction away from the first chip structure 100. The microlenses 395 may condense incident light into the photoelectric conversion devices PD. The microlenses 395 may be formed of a transparent photoresist material or a transparent thermosetting resin material. For example, the microlenses 395 may be formed of a TMR-based resin (manufactured by Tokyo Ohka Kogo, Co.) or an MFR-based resin (manufactured by Japan Synthetic Rubber Corporation), but example embodiments are not limited to such materials.

In an example embodiment, each of the microlenses 395 may vertically overlap each of the color filters 393.

Hereinafter, various modified examples of the components of the above-described image sensor will be described.

FIG. 8 illustrates a schematic plan view of an image sensor according to embodiments of the inventive concepts. FIG. 8 illustrates a plan view showing a region corresponding to FIG. 5.

FIGS. 9A and 9B illustrate schematic cross-sectional views of an image sensor according to embodiments of the inventive concepts. FIG. 9A illustrates a cross-sectional view taken along line II-If of FIG. 8, and FIG. 9B illustrates a cross-sectional view taken along line of FIG. 8. In the following, description of structural features in FIGS. 8, 9A and 9B that are similar as shown in FIGS. 5, 6A and 6B may be omitted for the sake of brevity, and the description will focus on differences between the embodiment of FIGS. 8, 9A and 9B with respect to the embodiment shown in FIGS. 5, 6A and 6B.

Referring to FIGS. 8 to 9B, an image sensor 2 according to example embodiments may include a landing structure 245′ and a second wiring structure 220′ different from those of the image sensor 2 of FIGS. 4 to 7B.

The landing structure 245′ may include a pad portion 245PP and a connection portion 245CP extending from the pad portion 245PP. The pad portion 245PP may have features the same as or similar as those of the landing structure described with reference to FIGS. 4 to 7B. The connection portion 245CP may connect the pad portion 245PP and at least a portion of second circuit devices 210, for example a first intermediate device 211. The connection portion 245CP may be integrally connected to the second gate electrode 215 of the first intermediate device 211. In an example embodiment, the pad portion 245PP, the connection portion 245CP, and the gate electrode 215 of the first intermediate device 211 may be disposed at substantially the same level and may have the same length (i.e., thickness) in a vertical direction. For example, the first intermediate device may be the driving transistor DX of FIG. 3B.

The second interconnection structure 220′ may include a first intermediate interconnection line 221′ and the first wiring via 222′ having structures different from those of FIGS. 4 to 7B. In plan view, the first intermediate interconnection line 221′ and the first intermediate via 222′ do not overlap the first intermediate device 211. The first intermediate device 211 may be electrically connected to the third chip structure 300 through a connection portion 245CP, so that an additional wiring structure between the pad portion 245PP and the first intermediate element 211 may be omitted. Accordingly, as compared with the image sensor 1 of FIGS. 4 to 7B, an image sensor 2 may have an increased degree of integration and improved electrical characteristics, such as a relatively increased degree of freedom in wiring of the second wiring structure 220′ or relatively reduced parasitic capacitance.

FIG. 10 illustrates a schematic cross-sectional view of an image sensor according to embodiments of the inventive concepts. FIG. 10 illustrates a cross-section corresponding to FIG. 6A. In the following, description of structural features in FIG. 10 that are similar as shown in FIG. 6A may be omitted for the sake of brevity, and the description will focus on differences between the embodiment of FIG. 10 with respect to the embodiment shown in FIG. 6A.

Referring to FIG. 10, in the image sensor 3 according to example embodiments, the third bonding via 242 may be in contact with the second isolation layer 207. As compared with FIG. 6A, a second isolation layer 207 may be disposed in the second substrate 201 in a region adjacent to the landing structure 245. In an example embodiment, the second isolation layer 207 may be formed to overlap the entire landing structure 245 in a plan view, but example embodiments are not limited thereto. The second isolation layer 207 may allow the third bonding via 242 and the second substrate 201 to be spaced apart from each other, together with the insulating spacer 244.

FIG. 11 illustrates a schematic flowchart of a method of manufacturing an image sensor according to embodiments of the inventive concepts.

FIGS. 12A, 12B, 12C, 12D, 12E, 12F and 12G are cross-sectional views illustrating a method of manufacturing an image sensor according to example embodiments. FIGS. 12A to 12G illustrate a region corresponding to FIG. 6A.

Referring to FIGS. 11 and 12A, in operation S101, a first chip structure 100 and a second chip structure 200 are bonded to each other.

The first chip structure 100 is formed. The forming of the first chip structure 100 may include preparing a first substrate 101, forming a first device isolation layer 107 to define an active region on the first substrate 101, forming first circuit devices 110 on a first substrate 101, and forming a first wiring structure 120 electrically connected to the first circuit elements 110 on the first substrate 101, a first bonding structure 130 on the first wiring structure 120, and a first insulating layer 180 covering the first circuit devices 110 and the first wiring structure 120. A planarization process is performed such that an upper surface of the first insulating layer 180 and an upper surface of the first bonding pad 131 of the first bonding structure 130 are substantially coplanar with each other.

A second chip structure 200 is formed. The forming the second chip structure 200 may include preparing a second substrate