>In an example assembly process, the DIP IPM devices 212 are mounted to the second side 253 of the board 250 by inserting the device leads 255 into through holes that extend through the board 250. The leads 255 are then soldered to conductive plating in the through holes to make electrical and mechanical connection to the board 250. Solder joints can be formed using a solder wave process to apply molten solder to the first side 251 of the printed circuit board 250 opposite the second side 253. Surface mount devices (SMDs) 252 are then mounted to the first side 251 of the board 250 using surface mount technology. In the example process, the SMDs 252 are mounted after the first solder wave process mounts the DIPs 212 on the second side 253. The SMDs 252 can include passive components such as capacitors, inductors and resistors. The SMDs 252 can be surface mounted using a solder reflow process.

Through hole device 256, which can be a large value capacitor, inductor, coil or other passive component, is then mounted on the first side 251 of the printed circuit board 250 using a second solder wave process to electrically couple and mechanically attach terminals 258 to the second side 253 of the board 250. To perform the second solder wave process, the DIP packages 212 (already mounted by the first solder wave process) have to be covered by a cap, well or reservoir that excludes the liquid solder of the second solder wave process from the DIP packages 212.

Heat sink 218 is then thermally and electrically coupled to thermal pads on the DIP packages 212 by die attach material 216, which can be a die attach epoxy or a die attach film. The die attach material 216 is thermally conductive and can be electrically conductive, or alternatively can be an electrically insulating die attach material, depending on the particular requirements of an application.

The printed board assembly process to form system 200 uses two solder wave processes. When the second solder wave process is performed, the DIP packages 212 have to be protected from the molten solder for mounting the through hole device 256. A cap, well or reservoir is used that lies over the DIP devices while molten solder is applied. The solder is applied to leads 258 to make a solder joint with board 250 and leads 258. This second solder wave process creates a maximum process distance, labeled “Dpd” in FIG. 2A, that requires a DIP package thickness to ne less than this distance. In an example solder wave process, the maximum process distance Dpd can be between 3.5 and 4 millimeters. A second requirement on the assembly of system 200 using the DIP packages 212 is a clearance distance labeled “Dclr.” For integrated power modules (IPMs) carrying voltages that are greater than 20 volts, and up to several hundred or more volts, a minimum clearance distance is needed from the heat sink 218 (which is a conductor attached to thermal pads on the top side of the IPMs in DIP packages 212, and which can be at a ground or other fixed potential in operation) to the nearest exposed lead 255. The minimum clearance is necessary to prevent arcing or unwanted leakage current. Arcing can occur when a lead at a high voltage is too close to a conductor at another potential, for example a ground potential, and the air or liquid between the two surfaces undergoes dielectric breakdown, allowing an arc to form between the surfaces and providing an unwanted current path. Damage can occur to a semiconductor device package or to the other devices in the package under arcing. To prevent arcing or unwanted leakage current, the two conductive surfaces have to be spaced from one another by at least the minimum distance Dclr. The need for a minimum clearance distance and for a maximum package thickness in the same assembly creates conflicting requirements in some printed board assembly processes. When DIP packages that are 5.5 millimeters thick, for example, are used to form the power system 200 in a printed board assembly process, the devices cannot meet the maximum production distance Dpd (necessitated by the second solder wave process), while when thin DIP packages that are 4 millimeters thick or less, for example, the packaged devices may meet the maximum production distance Dpd, but cannot also meet the minimum clearance distance Dclr. In an example Dclr is 3.87 millimeters, a minimum distance measured from the heat sink to the exposed leads. Thus, the requirements for production of the power system 200 and board 250 are difficult if not impossible to meet with existing DIP packaged IPM devices.

FIG. 2B illustrates an alternative power system 202 in another side view. The common elements of FIGS. 2A and 2B are given like reference numerals in FIG. 2B. For example, the two terminal through hole device 256, which can be a large value capacitor, resistor, or inductor, is the same as in FIG. 2A. The printed circuit board 260 is similar to board 250 in FIG. 2A, however board 260 is arranged for the use of press fit modules 213. The press fit modules 213 are integrated power modules and may contain, for example, semiconductor dies (not visible in FIG. 2A) similar to 105 in FIG. 1B. The press fit power modules 213 can include power FET semiconductor dies such as silicon carbide (SiC) FET or gallium nitride (GaN) FET devices and associated circuitry. A circuit substrate board is used to mount the semiconductor devices in a press fit module case, which can be of ABS, ASA, nylon, or another thermoplastic, metal, plastic or ceramic. The module case provides protection for the semiconductor dies within it, and can be filled with a thermal rated silicone gel to provide additional thermal protection. The case also carries the press fit terminals 254.

To form the power system 200 using the press fit IPMs, a printed board assembly process is used that varies from the one used above. The surface mount devices 252 are mounted to the first side 261 of the circuit board 260 using a solder reflow process for surface mounting. The through hole device 256 is mounted to the printed circuit board 260 on the first side 261 with the terminals 258 extending through printed circuit board 260, and terminals 258 are electrically coupled and mechanically connected to the printed circuit board 260 using a solder wave process on the second side 263 of the printed circuit board 260.

The press fit integrated power modules 213 are then installed on the second side 263 of the circuit board 260 using mechanical pressure. The press fit terminals 254 are shaped to engage with and mechanically connect to plated through holes in the printed circuit board 260, and to make the electrical connections to the press fit modules 213. Because the press fit modules 213 are installed without solder, a second solder wave process is not needed, which eliminates the need for a maximum process distance (see distance Dpd in FIG. 2A). The press fit modules 213 can then be of greater thickness than a conventional DIP package, so that the minimum clearance distance Dclr can be met, for example a case module for an IPM can be 10-12 millimeters in thickness, easily meeting the minimum clearance distance parameter Dclr of 3.87 millimeters for an example PBA for a power system.

However, the press fit modules 213 include circuit boards mounted inside case packages that may be filled with a thermal silicone gel. The press fit terminals of the modules have to be inserted into a module case and soldered or welded. The assembly processes for the press fit modules 213 is low in volume and has low production rates, and requires several pieces to be assembled together, so that the press fit modules 213 are undesirably expensive.

FIG. 3 illustrates, in a cross sectional view, a press fit semiconductor device package 312 of an example arrangement. In FIG. 3, semiconductor device package 312 includes semiconductor dies 305 that are similar to the semiconductor die 105 shown in FIG. 1B. The semiconductor dies 305 can be power FET devices, such as a SiC FET or a GaN FET, and can include associated circuitry. In an example a gate driver semiconductor device can be coupled to a power FET within a semiconductor device package. Other arrangements can include multiple power FET devices in one semiconductor device package. Additional semiconductor dies, or additional components such as passive devices (not shown for simplicity of illustration), can be included in the semiconductor device package 312.

The semiconductor device package 312 includes a package substrate 301. The package substrate 301 can be a direct bonded copper (DBC) substrate or other ceramic or laminate material coated with copper or another conductor on opposing sides. Through vias can be used to couple traces on the two sides where needed. The copper can be a thick foil, or can be plated or otherwise deposited, and can be patterned to provide traces. Semiconductor dies 305 are shown mounted on a device mount surface 302 of the package substrate 301. The opposite surface 304, which is the bottom of the semiconductor device package 312 as it is oriented in FIG. 3, has a conductive layer that forms a thermal pad.

Leads 355 are shown attached to the device mount surface 302 of the package substrate 301. Leads 355 are coupled to the semiconductor dies 305 by connections 319, which can be wedge bonded wire or coupled by wire bonds. The leads 355 extend through the mold compound 303 forming the body of semiconductor device package 312 and after some bends, extend away from the board side surface 311 of the semiconductor device package 312 in a vertical (as the elements are oriented in FIG. 3) direction, or in a direction that is approximately normal to a plane of a board side surface 311 of the semiconductor device package 312. The portion 377 of the leads 355 that is exposed from the semiconductor device package 312 forms press fit terminals or pins, emerging from the semiconductor device package 312 on the board side surface 311. This is in sharp contrast to the terminals of a conventional DIP package, which emerge at a midpoint on the sides of the package body. Because the leads 355 extend through the entire thickness of the mold compound 303 that forms the package body for the semiconductor device package 312 before being exposed from the mold compound 303, the minimum clearance distance from the thermal pad 304 of the package substrate 301 on the bottom surface of the semiconductor device package 312 to the exposed portions of the leads 355 is increased.

As is further described below, the leads 355 and the package substrate 301 can be provided as a leadframe, and multiple unit leadframes can be provided in an array, strip or grid form to enable multiple semiconductor device packages to be produced in a single production run. The mold compound 303 can be an epoxy mold compound (EMC) or other dielectric, and resins, epoxies, and plastics can be used. Epoxy mold compound can be a thermoset epoxy resin provided as a room temperature solid which is then heated to a liquid state and forced under pressure into mold chases that hold and surround the package substrate 301, and allowed to cure to form mold compound 303. The leads 355 and package substrate 301, when provided as a leadframe, can be described as a “deep downset” leadframe because the package substrate 301 sits at a bottom surface of the mold compound 303, and leads 355 extend down to the package substrate from a board side surface of the mold compound 303. The use of the deep downset leadframe helps provide the clearance distance needed for power devices, because prior to emerging from the mold compound 303, the leads 355 extend through the entire thickness of the semiconductor device package 312.

FIGS. 4A-4G illustrate, in a series of views, selected steps for forming semiconductor device packages incorporating the arrangements. In FIG. 4A, a process starts with a downset leadframe 320 having leads 355 attached to a device mount surface 302 of a package substrate 301. The package substrate 301 can be a direct bonded copper substrate with a copper foil bonded on either side (first side 302 is a device mount surface, and second side 304 can be a thermal pad) of a ceramic core, such as aluminum oxide or aluminum nitride. Other laminates and cores with copper traces can be used, printed circuit board materials such as BT resin or fiber reinforced glass such as FR4 with copper layers patterned on opposite sides. The leads 355 can be copper or copper alloy and are attached to the device mount surface 302 of the package substrate 301 by solder or brazing, for example.

The leadframe 320 illustrated in FIG. 4A is a single leadframe unit, but in a production process the leadframes can be provided in an array, grid or strip unit leadframes (not shown) with the leads coupled temporarily by tie bars that connect between the leads and between unit leadframes. The tie bars (not shown) can be removed after molding.

Leads 355 have several portions connected by bends. Base portion 361 is parallel to the device mount surface 302 of the package substrate 301 and is attached to the package substrate 301. An internal lead section 367 (which, when the molding process is complete, will be internal to the semiconductor device package) extends from the base portion 361 from a first bend 365. The internal lead section 367 extends away from the base portion at a first angle 363. The first angle is an obtuse angle in the illustrated example, of about 115 degrees, and can be in a range from 90 degrees (normal) to 160 degrees with respect to the base portion 361.

A second bend 369 connects a remaining portion of the lead 355 to the internal section 367. The remaining portion is in a plane that is parallel to the device mount surface 302 of the package substrate 301 (a horizontal plane as the elements are oriented in FIG. 4A.)

FIG. 4B illustrates the downset leadframe 320 after additional processing. The semiconductor device dies 305 are shown mounted on the device mount surface 302 of package substrate 301. The semiconductor device dies 305 can be mounted by dispensing die attach material on the package substrate 301, such as die attach epoxy or die attach film, and then mounting the dies 305 on the package substrate 301 using the die attach material. The die attach material can be thermally conductive to couple the backside surface of the semiconductor dies 305 to a bottom surface of the package substrate 301, which is a thermal pad. The die attach material and the copper on the package substrate 301 can also electrically couple the thermal pad on the backside surface of the package substrate 301 to the backside of semiconductor dies 305, to provide a ground or other potential to the semiconductor dies 305.

FIG. 4C illustrates the elements of FIG. 4B after an additional process step. In FIG. 4C, bond wire connections 319 are shown coupling the semiconductor dies 305 to the leads 355, and to one another. In an example arrangement, aluminum wires can be wedge bonded to form the wire connections 319 between bond pads (not shown in FIG. 4C) on the semiconductor dies 305 and the leads 355, and between the semiconductor dies 305. In an alternative arrangement, a single semiconductor die 305 can be used. In an further alternative arrangement, copper wire, and copper wedge bonding, can be used to form wire connections 319. Further, in some example arrangements, ball and stitch wire bonding can be used with copper, aluminum, plated copper, gold, silver or other bond wires used in semiconductor packaging. The aluminum or copper wire coupled with wedge bonding is particularly appropriate for high power devices, such as semiconductor dies including SiC FETs and GaN FETs, and for large currents greater than 1 Ampere, for example. The wedge bond wires can have gauges such as XX-YY (or diameters?) For lower power devices such as digital semiconductor dies, ball and stitch wire bonding can be used with finer bond wires as shown in FIG. 4C. If wire bond connections are used for connections 319, gold, copper, silver, or aluminum bond wire can be used, and palladium coated copper bond wire can be used.

FIG. 4D illustrates the elements of FIG. 4C in a further process. In FIG. 4D, a molding process begins with the package substrate 301 and the leads 355 positioned in a mold tool with a top chase 324 and a bottom chase 322. The package substrate 301 is positioned at the bottom of cavity in the bottom chase 322 ready for transfer molding. The top chase 324 defines a board side surface and is over and contacting the leads 355, after molding the leads 355 which will be coplanar with a board side surface of the mold compound. The thermal pad 304 of the bottom of the package substrate 301 is positioned at the bottom of the cavity in the mold tool so that it will not be covered by mold compound during molding.

FIG. 4E illustrates in another cross sectional view the leadframe 320 and the other elements shown in FIGS. 4C and 4D after the molding process of FIG. 4D is complete. Mold compound 303 covers the device mount surface 302 of the package substrate 301, while the bottom surface of the package substrate 301 is exposed from the mold compound 303 to form a thermal pad 304. The semiconductor dies 305 (two are shown but in additional arrangements there could be more, or only one) are covered by the mold compound 303, as are the wire bond connections 319. The leads 355 have portions covered by the mold compound 303 that extend from the device mount surface 302 of the package substrate 301, through the mold compound 303, and the leads 355 have portions that emerge from the mold compound 303 at the board side surface of the mold compound 303.

FIG. 4F illustrates, in a cross sectional view, the package substrate 301 and the other elements of FIG. 4E after an additional process in a form tool 374. In the transition from FIG. 4E to FIG. 4F, after molding, trim form tools are used first to trim away tie bars or other unwanted metal and mold compound flash between leads (not shown for simplicity of illustration) that may result from molding, and then the trim form tool is used to form the leads. In FIG. 4F, the leads 355 are shown being formed by form tool 374 to form terminals or pins that are extend at an approximately normal angle from the board side surface 311 of the mold compound 303 that forms the package body. The leads 355 are clamped by the form tool 374 on the inside and are formed by arms of the forming tool on the outside edge, to push the leads 355 away from the mold compound 303 to form the terminals that extend at a normal angle or at a similar angle, example angles range from 85 to 95 degrees with respect to the board side surface 311 of the mold compound 303, at a third bend 375 (see FIG. 4A that shows first bend 365 and second bend 369). The terminals or pins can be arranged for press fit assembly, alternatively the terminals can be arranged for solder in a through hole printed board assembly to mount the semiconductor device package.

FIG. 4G illustrates additional details of an example lead 355 of a completed semiconductor device package used for an example arrangement. The lead 355 has a base portion 361, in the arrangements this base portion is in a plane parallel to the device mount surface of the package substrate (see device mount surface 302 and package substrate 301 in FIG. 4E, for example) and is attached to it by brazing or solder. A first bend 365 is shown. An internal lead section 367 is shown extending from the base portion 361 at the first bend 365, forming an angle 363. The angle 363 can vary but in the illustrated arrangements is an obtuse angle of about 90 to 160 degrees with respect to the base portion 361. The internal lead section 367 in the arrangements extends through the thickness of the mold compound (see mold compound 303 in FIG. 4F). A horizontal section 373 extends from the internal section 367 from a second bend 369 to the third bend 375 and is arranged to be parallel to the board side surface of the mold compound 303 in the arrangements. In an example arrangement the horizontal section 373 is amount 0.X millimeters long, and at least a board side surface of the horizontal section is coplanar with the mold compound formed in the arrangements. This is because as the package substrate 301 is placed in the mold tool, the top of the cavity, formed by an upper mold chase, is placed on the horizontal portion of the leads 355 and so that during molding, the mold compound stops at the same plane as the board side surface of the lead 355.

External section 377 extends from the third bend