330 of FIG. 3A). A resulting peak signal 305 is compared to a threshold 315. As shown, threshold 315, which is based on peak signal 305, varies (according to the RC filter characteristics). The resulting comparison output is thus a single bit sample at the clock rate of the clock that drives a flip-flop (such as flip-flop 340). A clock signal of 1 MHz results in an oversampling of 8. This 1-bit signal stream is thus the input to digital circuit 350. Digital circuit 350 may perform a timing acquisition based on this signal.

Referring now to FIG. 3C, shown is a block diagram of a multi-radio arrangement in accordance with an embodiment. In FIG. 3C, radio 300 is shown primarily with receive components (although it is to be understood that transmit components also may be present), and includes circuitry both for a wake-up radio in accordance with an embodiment as well as a main radio, such as a Bluetooth radio.

As illustrated with regard to WuR digital circuit 350, multiple constituent components are included. A scheduler 352 controls scheduling of operations within the digital circuitry, and couples to a core circuit 354 and an interface circuit 358 (which may include a plurality of registers and a bus interface). As shown, circuit 358 couples to a bus 355, which may be in communication with a host processor. In an embodiment, bus 355 may be implemented as an Advanced Peripheral Bus (APB).

In an embodiment, scheduler 352 may include programmable hardware circuitry and may be implemented at least in part with a finite state machine that is configured to enable core circuit 354 for a scan window according to a predetermined interval. As one example, this interval may be a programmable value. At each interval, core circuit 354 and other circuitry can be enabled to scan for an incoming wake-up request for a given duration.

Scheduler 352 may enable operation of core 354 via an enable signal (wur_core_en). In addition, scheduler 352 sends an acknowledge signal (wur_core_syncdet_ack) to core 354. As will be described below, this acknowledge signal may be sent in response to an indication by core 354 of detection of a sync word of a wake-up packet. As further illustrated, scheduler 352 may send a signal (wursched_timesyncdelay_hw) to interface circuit 358, which includes a write enable bit and a write data field, such that this signal includes information regarding the time at which a sync word is found in a time sync mode.

In response to enabling by scheduler 352, core 354 may operate to perform a packet timing acquisition based on an incoming bit stream (namely an MOOK-modulated bit stream). Core 354 further operates to capture incoming data timing acquisition. Further details of such operation are described below. As further illustrated, when a sync word is validly detected in core 354, it issues a detection signal (wur_core_syncdet) both to scheduler 352 and to a PDU processor 356. Core 354 also sends a write enable signal (wur_core_data_wen) to PDU processor 356. This signal may be sent in conjunction with decoded and demodulated data (wur_core_data) output from core 354.

PDU processor 356 may be configured to process incoming data bits of a data packet to determine whether a valid wake-up event has been received. Such operations include performing a CRC check on the incoming data to ensure that a given packet was correctly received in response to detection of a wake-up packet. In an embodiment, PDU processor 356 processes the message if the following conditions are met: WM and Length fields are valid options; the Address matches the wake-up radio's configured address and/or a valid broadcast address; Token matches one of the wake-up radio's configured tokens; and CRC passes.

In accordance with an embodiment, PDU processor 356 sends an interrupt signal to additional circuitry of radio 300. More specifically as shown, this interrupt signal (srw_wur_irq) is sent to an energy management unit (EMU) circuit 362 of a control circuit 360 and is also sent to a digital radio circuit 374 of a Bluetooth radio 370.

Thus when a valid wake-up packet is received, receive operations may be initiated within radio 370 as further controlled in response to receipt of a wake-up signal from a system real time clock circuit 364.

As further illustrated, PDU processor 356 sends a payload of a wake-up packet to interface circuit 358, which can send it, in turn, to a host processor for handling. Also PDU processor 356 sends a set signal (wake-upif_hw_set), which causes interface circuit 358 to set a register. In response, interface circuit 358 sends an acknowledgement signal (wake-upif_hw_ack) back to PDU processor 356.

Still with reference to FIG. 3C, Bluetooth radio 370 includes, in addition to digital radio circuit 374, an analog receiver 372. Analog receiver 372 may be configured to receive an incoming RF signal (e.g., a BLE communication) which it processes in an analog front end to amplify, filter, downconvert, and convert the downconverted signal to a digital signal for sending to digital radio circuit 374.

Referring now to FIG. 4, shown is a block diagram of a core circuit in accordance with an embodiment. Core circuit 400 is an implementation of core circuit 352 of FIG. 3C. As shown, an incoming bit stream is received and stored into a buffer 410, implemented as a first in first out (FIFO) buffer. Under control of a state controller 450, details of which are discussed further below, the bit stream is output from buffer 410 to a first correlator 420₁and a second correlator 420₂(when enabled).

In embodiments herein, correlators 420 may be configured as single-bit correlators. As will be described, with an oversampled bit stream (e.g., 8× oversampling), correlators 420 may be configured to perform correlations on 8 bits at a time (corresponding to a single-bit MOOK-modulated data). In an embodiment, correlators 420 each may be configured to perform 128-sample single-bit correlations that are used for timing acquisition, as well as for performing sync word decoding after timing is acquired. By use of single-bit correlators, power consumption may be substantially reduced.

Specifically correlators 420 are configured to perform a correlation between the incoming bit stream and a known sequence stored in a sequence register 405. In embodiments herein, this known sequence may be at least a portion of a sync word of a wake-up packet. In one particular embodiment, this sync word may have a value of 0x8E89BED6. At a high level, a two-step single bit correlation detection is performed on at least a portion of sync word. In a particular embodiment, a 256 sample, single bit correlation is performed to find fine timing, where first correlator 420₁operates first and then second correlator 420₂operates, such that together they act as a 256-sample correlator.

State controller 450 may maintain track of each processing stage within core circuit 400. In addition, state controller 450 may control correlators 420 and an averager circuit 430 for particular task durations and operating modes. In operation under control of state controller 450, in a first state, first correlator 420₁is enabled. In first correlator 420₁, when a value of a correlation result exceeds a threshold level, it sends a feedback signal to state controller 450. In response to this feedback signal, state controller 450 enables second correlator 420₂, which similarly performs a correlation on another portion of the sync word. More specifically, first correlator 420₁operates on 128 bits to detect the first 8 bits of a sync word (with 8× oversampling and Manchester encoding, these 8 sync word bits corresponds to 128 bits of the incoming bitstream). As shown, correlator 420₁also provides its correlation result to second correlator 420₂, which in turn generates a correlation sum from this first correlation result and a second correlation result calculated in second correlator 420₂.

When this correlation sum exceeds another (higher) threshold level, state controller 450 enables averager circuit 430. In an embodiment, averager circuit 430 may be configured to decode incoming samples into data bits. In operation, averager circuit 430 may perform an averaging function on incoming bits of the bit stream to generate an output data stream corresponding to a received packet. When a wake-up packet is received, averager circuit 430 generates a wake-up request, which it sends to a PDU processor. Understand while shown at this high level in the embodiment of FIG. 4, many variations and alternatives are possible.

Referring now to FIG. 5A, shown is a timing diagram illustrating a two-step single-bit correlation detection operation in accordance with an embodiment. As shown in FIG. 5A, an incoming bit stream (ook_out stream) is provided to a first correlator, which is enabled (corr1_en). As shown, a correlation operation is performed on the eight most significant bits (MSBs) of a sync word (sync_bits[31:24]). During this first correlator operation a positive result is returned when a correlation result for this incoming bit stream exceeds a threshold level (shown in the graphical illustration when the correlation result exceeds a threshold). When this occurs, the second correlator also is enabled and performs a correlation on another portion of the incoming sync word (namely, sync_bits[23:16]).

In turn, these correlation results are summed. When it is determined that the sum exceeds a second threshold, timing is acquired. At this point, an averager circuit is enabled to decode remaining samples of the incoming bit stream (including sync_bits[15:0]). In addition, note that the correlators remain enabled to perform a sync check by performing correlations again on the already arrived bits to confirm valid detection. Note that this sync check operation is a fast sync check, which is performed on the already arrived bits and in which the correlators operate as if processing a new incoming sequence. At the same time, the averager circuit is enabled to perform a slow sync check to check the arriving bits (sync_bits[15:0]).

Referring now to FIG. 5B, shown are timing diagrams illustrating operation of an averager circuit in accordance with an embodiment. As illustrated, the averager circuit receives incoming oversampled bits of the bit stream (ook_out stream). With 8× oversampling and Manchester encoding of the OOK data stream, there are two chips per bit, with each chip being formed of 8 bits. Note that the averager circuit operates by discarding the first bit of each chip (as a don't care). Thus, the averager circuit operates to add the relevant bits of the two chips to output a single-bit value of the data stream. With the Manchester encoding, a logic one value of the first bit (PDU_bit[0]) results from positive values for the first chip and negative values for the second chip. At a conclusion of the two chips, a maximum likelihood (ML) decision may be made during the first sample of the first chip of a next incoming bit of the data packet. Although shown at this high level in the embodiment of FIG. 5B, many variations and alternatives are possible.

Referring now to FIG. 6A, shown is a flow diagram of a method for operating a state controller in accordance with an embodiment. More specifically as shown in FIG. 6A, method 600 is a method for controlling a timing acquisition process performed in a core circuit. In one or more embodiments, method 600 may be performed by a state machine of the state controller such as a core finite state machine (FSM). As illustrated, method 600 begins in an idle state (state 605) in which circuitry of the core circuit is in an idle state. Control passes to state 610 when an incoming packet begins to be received. At state 610, a first correlator search process is enabled. As discussed above, this first correlator may be configured to perform correlations between a first portion of a sync word (e.g., MSBs of the sync word) and a known pattern.

When the correlation result exceeds a threshold, control passes to state 615 where a second correlator search process may be enabled. In state 615, this second correlator may be configured to perform correlations between a second portion of the sync word (e.g., lesser MSBs of the sync word) and a known pattern. If the second correlator does not generate a correlation result (the sum of the 2 correlations) that exceeds the second threshold, the correlation at state 615 fails, and control passes back to block 610 for further searching for a sync word portion within the incoming bit stream in the first correlator.

Still with reference to FIG. 6A, instead if the second correlator succeeds in finding another sync word portion (when a sum of the correlation result to the two correlation results exceeds a second threshold), control passes to state 620 in which a sync check (both fast and slow sync checks) is performed. As discussed above, this sync check may be performed on the already arrived bits in the two correlators. At this time, the averager circuit is configured to perform a slow sync check on arriving bits of the sync word (e.g., the 16 LSBs). Should this operation fail, control passes back to state 610.

Otherwise, when the sync check passes such that a valid sync word is identified, control passes to state 625. At state 625, the averager circuit is controlled to perform averaging of Manchester encoded bits of the bit stream as discussed above to decode incoming bits, including the various fields of the wake-up packet. Note that at this point after the sync check completes at state 620, the correlators may be placed into an idle state to reduce power consumption.

Referring now to FIG. 6B, is a flow diagram of a method for operating a state controller in accordance with another embodiment. More specifically as shown in FIG. 6B, method 650 is a method for controlling a sync check process performed in a core circuit. In one or more embodiments, method 650 may be performed by a state machine of the state controller such as a core FSM.

As illustrated, method 650 begins at an idle state