5 and 6, and the details thereof are omitted for the sake of brevity.

Referring to FIG. 1 and the example illustrated in FIGS. 8 and 9, the method 100 proceeds to step 108, where a plurality of liners and a plurality of interconnect structures are formed. A plurality of liners 22 are formed in the openings 21, respectively, and a plurality of interconnect structures 23 are formed on the liners 22, respectively. In some embodiments, the liners 22 may include, for example, but not limited to, cobalt (Co), ruthenium (Ru), tantalum (Ta), titanium (Ti), cobalt nitride (CoN), ruthenium nitride (RuN), tantalum nitride (TaN), titanium nitride (TiN), or the like, or combinations thereof. Other suitable liner materials are within the contemplated scope of the present disclosure. In some embodiments, the liners 22 may be formed by conformally depositing a liner layer using a suitable deposition process as is known in the art of semiconductor fabrication, such as PVD, CVD, ALD, PEALD, thermal ALD, PECVD, or the like, and then removing excess of the liner layer over the second etch stop layer 15 by a planarization process (for example, but not limited to, CMP process, or the like). A metal material is then filled into the remaining volume of each of the openings 21 by a suitable deposition process as is known to those skilled in the art of semiconductor fabrication (for example, but not limited to, CVD, PECVD, ALD, PEALD, PVD, ELD, ECP, or the like) at a temperature ranging from about 200° C. to about 450° C., and a planarization process (for example, but not limited to, a CMP process) is then conducted to remove excess of the metal material over the second etch stop layer 15 so as to form the interconnect structures 23. In some embodiments, the metal material may include, for example, but not limited to, copper (Cu), aluminum (Al), gold (Au), silver (Ag), tungsten (W), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), nickel (Ni), palladium (Pd), osmium (Os), molybdenum (Mo), or the like, or alloys thereof, which have good conductivity. Other suitable conductive materials are within the contemplated scope of the present disclosure. An interconnect layer 24 is thus formed on the interconnect layer 12. In some embodiments, the interconnect layer 24 may serve as a metal layer, and the interconnect structures 23 may serve as metal lines.

Referring to FIG. 1 and the example illustrated in FIG. 10, the method 100 proceeds to step 109, where a capping layer is selectively formed on the interconnect structures and the liners. FIG. 10 is a schematic view illustrating selective formation of a capping layer 25 on the interconnect structures 23 and the liners 22. The capping layer 25 includes a plurality of capping portions 251, each of which is deposited on a corresponding one of the interconnect structures 23 and a corresponding one of the liners 22. The capping layer 25 may be selectively formed on the interconnect structures 23 and the liners 22 by a suitable selective deposition process as is known to those skilled in the art of semiconductor fabrication, for example, but no limited to, selective CVD, selective ALD, selective electroless deposition (ELD), or the like. Other suitable techniques are within the contemplated scope of the present disclosure. In some embodiments, the capping layer 25 may include, for example, but not limited to, graphene, metal (for example, but not limited to, Co, Al, Ru, W, Mo, Ta, Cu, Fe, Rh, Ir, Pd, Pt, or the like), alloys of the metals, silicides, nitrides, or oxides of the metals or alloys thereof. Other suitable materials are within the contemplated scope of the present disclosure.

Thereafter, another interconnect layer (not shown) may be formed on the interconnect layer 24. The another interconnect layer may serve as a via layer and includes an interconnect structure, which serves as a via contact and which extends through an IMD layer (not shown) of the another interconnect layer so as to be electrically connected to a corresponding one of the interconnect structures 23 of the interconnect layer 24 through a corresponding one of the capping portions 251.

Referring to the example illustrated in FIG. 9, a semiconductor device in accordance with some embodiments of the present disclosure includes the interconnect layer 24 disposed on the interconnect layer 12. The interconnect layer 24 includes the dielectric layer 14 serving as an IMD layer; the first etch stop layer 13 disposed on a lower surface of the dielectric layer 14; the second etch stop layer 15 disposed on an upper surface of the dielectric layer 14; a plurality of the interconnect structures 23 extending downwardly through the second etch stop layer 15 and the dielectric layer 14 and spaced apart from each other; a plurality of the liners 22 each covering a bottom surface and a lateral surface of a corresponding one of the interconnect structures 23; and a plurality of the thermal dissipation features 20 extending downwardly through the second etch stop layer 15 and the dielectric layer 14 to be in contact with the first etch stop layer 13. As described above, the dielectric layer 14 includes a low-k dielectric material which includes silicon carbonitride (SiCxNy) having a high carbon content that ranges from about 30 atomic % to about 45 atomic %. The dielectric layer 14 may have a reduced etching damage, or even may be substantially free of etching damage, after being subjected to the etch process to form the openings 19 as illustrated in FIGS. 5 and 6. The k value of the dielectric layer 14 will not be undesirably increased after the etch process, or may be maintained substantially at the same value before and after the etch process. In addition, a breakdown field (Ebd) of the dielectric layer 14 may be maintained substantially at the same value before and after the etch process. Therefore, the capacitance of the IMD layer (i.e., the dielectric layer 14) formed in the interconnect layer 24 of the configuration shown in FIG. 9 will not be undesirably increased due to the etch process for forming the openings 19 as illustrated in FIG. 6.

In addition, as described above, the first etch stop layer 13 and the second etch stop layer 15 may include aluminum nitride (AlNx) which has a high thermal conductivity ranging from about 150 W/mK to about 200 W/mK. The first etch stop layer 13 and the second etch stop layer 15 may cooperate with the thermal dissipation features 20 to form a thermal dissipation structure, which includes an upper thermal dissipation layer (i.e., the second etch stop layer 15) disposed on an upper surface of the IMD layer (i.e., the dielectric layer 14), a lower thermal dissipation layer (i.e., the first etch stop layer 13) disposed on a lower surface of the IMD layer, and a plurality of the thermal dissipation features 20 disposed to interconnect the upper thermal dissipation layer and the lower thermal dissipation layer. Therefore, heat produced in the semiconductor device, especially in a back-end-of-line (BEOL) structure of the semiconductor device, can be dissipated easily through the thermal dissipation structure. Therefore, thermal-related reliability issues which may be caused by heat accumulation in the BEOL structure of the semiconductor device can be avoided.