, FIG. 8 and FIG. 9, the power supply wiring layer 2 may extend along the active surface 13 of the memory chip 1. That is, the power supply wiring layer 2 is located on the front surface of the memory chip 1, therefore, the power supply wiring layer 2 may be manufactured by using the original back-stage process after the components in the memory chip 1 are manufactured, and the process may be simpler. In addition, the power supply wiring layer 2 may extend only at edges near the upper and lower sides of the memory chip 1 without covering the entire active surface 13 of the memory chip 1. Therefore, the contact area between the power supply wiring layer 2 and the memory chip 1 is small, and the heat of the power supply wiring layer 2 has little influence on the memory chip 1.

The width of the power supply wiring layer 2 in the second direction Y is smaller than the width of the solder bump 51 in the second direction Y. The width of the power supply wiring layer 2 in the second direction Y is smaller than the width of the solder pad 52 in the second direction Y. That is, the solder bump 51 and the solder pad 52 have a larger volume and smaller resistance, and are advantageous in improving the soldering strength. In addition, it is advantageous to increase the contact area of the solder bump 51 and the solder pad 52 with the power supply wiring layer 2, thereby reducing the contact resistance.

It is to be noted that the wireless communication manner does not occupy the space between adjacent memory modules 10. Therefore, it is possible to lay out the wired power supply flexibly even if the area of the opposite side of adjacent memory modules 100 is small.

Referring to FIG. 5, FIG. 6, FIG. 8, and FIG. 9, each memory chip 1 is provided with a power supply signal line 12, and the power supply signal line 12 is electrically connected to the power supply wiring layer 2. The connection relationship between the power supply signal line 12 and the power supply wiring layer 2 will be described in detail below.

Each memory chip 1 is provided with a plurality of power supply signal lines 12, and different power supply signal lines 12 can provide different voltage signals, such as digital signal or analog signal, for the elements in the memory chip 1. The power supply signal line 12 may be a ground signal line 12G or a power source signal line 12P. Different ground signal lines 12G have different voltage signals and different power source signal lines 12P have different voltage signals.

The power supply wiring layer 2 may be a power source wiring layer 2P, a ground wiring layer 2G, or a hybrid wiring layer 2PG. That is, the power supply wiring layer 2 in a memory chip 1 includes a plurality of power supply wiring 20 isolated from each other, and the power supply wiring layer 2 can be divided into the above three categories according to the type of power supply wirings 20 of each power supply wiring layer 2. When the power supply wirings 20 in the power supply wiring layer 2 are all power source wirings 20P, this power supply wiring layer 2 is referred to as a power source wiring layer 2P. When the power supply wirings 20 in the power supply wiring layer 2 are all ground wiring 20G, this power supply wiring layer 2 is referred to as a ground wiring layer 2G. When the power supply wiring layer 2 includes both the ground wiring 20G and the power source wiring 20P, the power supply wiring layer 2 is referred to as a hybrid wiring layer 2PG.

The ground wiring 20G is electrically connected with the ground signal line 12G correspondingly, and the power source wiring 20P is electrically connected with the power source signal line 12P correspondingly. It is to be noted that a plurality of power supply wiring lines 20 in the power supply wiring layer 2 are insulated from each other, such that the power supply signal lines 12 having different voltage signals can be led out separately.

If a memory chip 1 includes a power supply wiring layer 2 itself, at least part of the power supply signal lines 12 of the memory chip 1 can be directly connected to its own power supply wiring layer 2, that is, led out through its own power supply wiring layer 2. If a memory chip 1 does not have a power supply wiring layer 2, the power supply signal line 12 of the memory chip 1 can be led out through the power supply wiring layer 2 of another memory chip 1. In other words, the memory chip 1 can be electrically connected with another memory chip 1 through the conductive via 41 and the bonding part 42, thereby electrically connecting its own power supply signal line 12 with the power supply signal line 12 of another memory chip 1, and further electrically connecting with the power supply wiring layer 2 of another memory chip 1.

It is to be noted that, within the same memory cell 10b, the power supply wirings 20 having the same voltage signal are electrically connected together through the solder pad 52 and the solder bump 51, as such, this voltage signal can be supplied to a plurality of memory chips 1 in the first direction X.

A plurality of memory chips 1 may be stacked in a hybrid bonding manner. For example, the surface of the memory chip 1 is further provided with a dielectric layer 43, and the dielectric layers 43 of adjacent memory chips 1 may be connected together by an acting force, such as a molecular force. Further, the surface of the memory chip 1 may further be provided with a bonding part 42, and adjacent bonding parts 42 are bonded together under a temperature rising condition. That is, the dielectric layer 43 is made of an insulating material and is capable of acting as an isolation. The bonding part 42 is a conductive material and capable of acting as an electrical connection. Further, the dielectric layer 43 exposes the end face of the power supply wiring layer 2 facing or facing away from the logic chip 3 and covers the side surfaces of the power supply wiring layer 2 except the end face.

The relationship between the number of the memory chip 1 and the number of the power supply wiring layer 2 will be described in detail below.

In to first example, referring to FIG. 2 to FIG. 11, each memory chip 1 includes a power supply wiring layer 2, that is, the number of memory chips 1 is the same as the number of power supply wiring layers 2. Since the number of the power supply wiring layers 2 is large, it is possible to provide sufficient led out positions for a plurality of power supply signal lines 12, that is, the process of leading out the power supply signal lines 12 can be simplified. In addition, more power supply wiring layers 2 are also beneficial to improve the stability of power supply, thereby improving the performance of semiconductor structure. In addition, the power supply wiring layers 2 are uniformly disposed in a plurality of memory chips 1, therefore, it is beneficial to unify the manufacturing processes of different memory chips 1, so as to reduce the production cost.

In some embodiments, referring to FIG. 2 to FIG. 9, the memory modules 100 include a plurality of chip sets 10a, each chip set 10a includes two adjacent memory chips 1 bonded with each other. Two power supply wiring layers 2 are disposed between two memory chips 1 of a same chip group 10a, and the two power supply wiring layers 2 are located on surfaces of the two memory chips 1, respectively; each of the two power supply wiring layers 2 is electrically connected with the two memory chips 1. That is, the two memory chips 1 of the chip set 10a are bonded face to face, that is, the active surface faces to the active surface. Two memory chips 1 of the same chip set 10a share two power supply wiring layers 2 located between the two memory chips 1.

Specifically, referring to FIG. 3, a conductive via 41 is provided in the memory chip 1. For example, the conductive via 41 is Through-Silicon Via (TSV). A bonding part 42 is provided between two memory chips 1 of the same chip set 10a, and the bonding part 42 is connected with the conductive via 41 of the two memory chips 1, so as to electrically connect the two memory chips 1. For example, a plurality of conductive vias 41 are spaced from each other in each memory chip 1, and the plurality of conductive vias 41 are connected with a plurality of power supply signal lines 12 in the memory chip 1 one by one. The voltage signals on the plurality of power supply signal lines 12 in the same memory chip 1 are different, and accordingly, the voltage signals on the plurality of conductive vias 41 in the same memory chip 1 are also different. In two memory chips 1 of the same chip set 10a, the conductive vias 41 having the same voltage signal are electrically connected through the bonding part 42, so that the power supply signal lines 12 having the same voltage signal in the two memory chips 1 are electrically connected together.

For example, the conductive via 41 includes a plurality of ground vias 41G and a plurality of power source vias 41P, and the bonding part 42 includes a plurality of ground bonding parts 42G and a plurality of power source bonding parts 42P. The ground via 41G is connected with the ground bonding part 42G, and the power source via 41P is connected with the power source bonding part 42P.

The conductive vias 41 of each memory chip 1 may be spaced in a third direction Z, and the third direction Z is perpendicular to the upper surface of the logic chip 3. For example, the ground vias 41G and the power source vias 41P are alternately arranged in the third direction Z to reduce electromagnetic interference of adjacent conductive vias 41.

FIG. 4 is a bottom view of the memory modules 100, FIG. 5 and FIG. 6 are schematic diagrams of active surfaces 13 of two memory chips 1 of a chip set 10a, respectively, and FIG. 4 to FIG. 7 correspond to a same semiconductor structure. Referring to FIG. 4 to FIG. 7, the chip set 10a includes a first memory chip 1a and a second memory chip 1b. Each memory chip 1 includes a first power supply signal line group 121 and a second power supply signal line group 122. The power supply signal lines 12 of both the first power supply signal line group 121 and the second power supply signal line group 122 include a power source signal line 12P and a ground signal line 12G. The first power supply signal line groups 121 of the two memory chips 1 are led out through the power supply wiring layer 2 of the first memory chip 1a, and the second power supply signal line groups 122 of the two memory chips 1 are led out through the power supply wiring layer 2 of the second memory chip 1b. That is, both power supply wiring layers 2 of the same chip set 10a are hybrid wiring layers 2PG.

Continuing with reference to FIG. 4, in the hybrid wiring layer 2PG, the ground wirings 20G and the power source wirings 20P are alternately arranged in the third direction Z, thereby facilitating the reduction of electromagnetic interference of adjacent power supply wirings 20.

FIG. 7 is a bottom view of the memory modules 100, FIG. 8 and FIG. 9 are schematic diagrams of active surfaces 13 of two memory chips 1 of a chip set 10a, respectively, and FIG. 7 to FIG. 9 correspond to a same semiconductor structure. Referring to FIG. 7 to FIG. 9, the power supply signal lines 12 of the first power supply signal line group 121 are all power source signal lines 12P, and the power supply signal lines 12 of the second power supply signal line group 121 are all ground signal lines 12G. The first power supply signal line groups 121 of the two memory chips 1 are led out through the power supply wiring layer 2 of the first memory chip 1a, and the second power supply signal line groups 122 of the two memory chips 1 are led out through the power supply wiring layer 2 of the second memory chip 1b. That is, two power supply wiring layers 2 of the same chip group 10a are a power source wiring layer 2P and a ground wiring layer 2G, respectively, the first power supply signal line group 121 is electrically connected to the power source wiring layer 2P, and the second power supply signal line group 122 is electrically connected to the ground wiring layer 2G.

So far, based on FIG. 4 to FIG. 9, each memory chip 1 includes a first power supply signal line group 121 and a second power supply signal line group 122. Both the first power supply signal line group 121 and the second power supply signal line group 122 include a plurality of power supply signal lines 12. Two first power supply signal line groups 121 in the same chip set 10a are electrically connected to a power supply wiring layer 2, and two second power supply signal line groups 122 in the same chip set 10a are electrically connected to another power supply wiring layer 2. That is, the power supply wiring layer 2 is shared by two power supply wiring layers 2 of the same chip set 10a.

The advantages of this design mainly include the following aspects. Firstly, the shared power supply wiring layer 2 is located between two memory chips 1, which can shorten the distance between the power supply wiring layer 2 and the two memory chips 1, thereby reducing the high power consumption generated due to the long distance. Secondly, only the dielectric layer 43 for insulation may be provided between adjacent chip sets 10a, such that the number of bonding parts 42 may be reduced to simplify the production process. Thirdly, the power supply wiring layer 2 is shared by two memory chips 1, and accordingly, the number of power supply wirings 20 is reduced, and the number of solder bumps 51 and solder pads 52 is reduced, thereby facilitating the provision of more sufficient space locations for the solder bumps 51 and avoiding short circuit. Fourthly, only two memory chips 1 in the chip set 10a share the power supply wiring layer 2, that is, the number of memory chips 1 in the chip set 10a is small, which is beneficial for ensuring the stability of power supply.

Referring to FIG. 4 and FIG. 7, there is a first distance d1 between two power supply wiring layers 2 in the same chip set 10a in the second direction Y. The solder bumps 51 connected to different power supply wiring layers 2 in the same chip set 10a have a second distance d2. There is a third distance between solder pads 52 connected to different power supply wiring layers 2 in the same chip set 10a. The ratio of the first distance d1 to the second distance d2 ranges from 1:1 to 1.2:1. The ratio of the first distance d1 to the third distance ranges from 1:1 to 1.2:1. It is to be noted that if the second distance d2 and the third distance are too large, the space between adjacent memory chips 1 may be wasted. If the second distance d2 and the third distance are too small, an erroneous electrical connection may occur between adjacent solder bumps 51 and adjacent solder pads 52. When the distance ratios are kept in the above-mentioned ranges, it is beneficial to balance the above two problems. For example, as illustrated in FIG. 4 and FIG. 7, the first distance d1 may be the same as the second distance d2.

Referring to FIG. 10 and FIG. 11, FIG. 10 is a partial cross-section view and FIG. 11 is a bottom view of the memory module 100 illustrated in FIG. 10. The power supply signal lines 12 in the same memory chip 1 are connected with the power supply wiring layer 2, the power supply wiring layers 2 of different memory chips 1 are independent of each other, and the power supply signal lines 12 of different memory chips 1 are independent of each other. That is, the power supply signal lines 12 of a plurality of memory chips 1 do not need be electrically connected together through the conductive vias 41 and the bonding parts 42, and the power supply signal lines 12 in each memory chip 1 may be led out through the power supply wiring layer 2 of the respective memory chip 1 itself without being led out by the power supply wiring layer 2 of other memory chips 1. Since the power supply signal lines 12 of each memory chip 1 may be led out separately, it is beneficial to improve the stability of power supply. Further, the step of manufacturing the bonding parts 42 and the conductive vias 41 may be omitted, such that the production cost may be reduced.

Continuing with reference to FIG. 11, for example, the power supply wiring layer 2 of each memory chip 1 may be a hybrid wiring layer 2PG, and the power source wiring 20P and the ground wiring 20G are alternately arranged in the third direction Z to reduce electromagnetic interference. Further, a plurality of power supply wiring layers 2 may be formed on the same side of the memory chip 1, thereby unifying the manufacturing process of the power supply wiring layers 2.

Further, the power source wirings 20P of the plurality of memory chips 1 may be aligned in line in the second direction Y, and the ground wirings 20G of the plurality of memory chips 1 may be aligned in line in the second direction Y. Alternatively, the power source wirings 20P and the ground wirings 20G may be alternately arranged in the second direction Y and arranged in line. Therefore, it is beneficial to improve the uniformity of semiconductor structure and the production process is simpler.

In a second example, the number of power supply wiring layers 2 may be more than the number of memory chips 1. For example, referring to FIG. 12 and FIG. 13, FIG. 12 is a partial cross-section view and FIG. 13 is a bottom view of the memory module 100 illustrated in FIG. 12. A power supply wiring layer 2 is provided between two adjacent memory chips 1, and the power supply wiring layer 2 is electrically connected with the memory chips 1 on both sides thereof. One power supply wiring layer 2 is provided on each of two sides of a memory module 100, and is electrically connected with the respective memory chip 1 on the side of the memory module 100. That is, except that the two power supply wiring layers 2 on both sides are not shared by the memory chips 1, each of other power supply wiring layers 2 in the middle is shared by the memory chips 1 on both sides of the respective power supply wiring layer 2. The memory chips 1 on the sides of the memory module 100 may also be understood as the memory chips 1 on the outermost sides of the memory module 100. A power supply wiring layer 2 in the middle is connected to the power supply signal lines 12 of two memory chips 1, such that it is facilitating to reduce the number of solder bumps 51 and the production process is simple. In addition, the distribution locations of the power supply wiring layers 2 in the memory module 100 is relatively uniform, which is beneficial to simplify the production process.

As illustrated in FIG. 13, in some embodiments, the power supply wiring layer 2 includes a power source wiring layer 2P and a ground wiring layer 2G, the power source wiring layer 2P includes a plurality of power source wirings 20P, and the ground wiring layer 2G includes a plurality of ground wirings 20G. The power source wiring layer 2P and the ground wiring layer 2G are alternately arranged in the first direction X. In other embodiments, all power supply wiring layers 2 may also be hybrid wiring layers 2PG, and the voltage signals of power supply signal lines 12 led out from adjacent hybrid wiring layers 2PG are different.

Continuing to refer to FIG. 12 and FIG. 13, the sharing manner of the power supply wiring layer 2 will be described below. The power source wiring layer 2P located at the head side of the memory module 100 may be directly connected to the power source signal line 12P of the first memory chip 1a, therefore, the first memory chip 1a may not include the power source via 41P and the power source bonding part 42P. The first memory chip 1a and the second memory chip 1b share the ground wiring layer 2G, that is, the ground signal lines 12G of the first memory chip 1a and the second memory chip 1b are connected together through the ground via 41G and the ground bonding part 42G, and are led out through the ground wiring layer 2G between the first memory chip 1a and the second memory chip 1b. The second memory chip 1b and the third memory chip 1c share the power source wiring layer 2P, that is, the power source signal lines 12P of the second memory chip 1b and the third memory chip 1c are connected together through the power source via 41P and the power source bonding part 42P and are led out through the power source wiring layer 2P between the second memory chip 1b and the third memory chip 1c. Since the second memory chip 1b and the third memory chip 1c do not share the ground wiring layer 2G, the ground via 41G and the ground bonding part 42G of the second memory chip 1b and the third memory chip 1c will not be electrical connected.

That is, if the power supply wiring layer 2 between two adjacent memory chips 1 is the power source wiring layer 2P, the two memory chips 1 are electrically connected through the power source via 41P and the power source bonding part 42P. Similarly, if the power supply wiring layer 2 between two adjacent memory chips 1 is a ground wiring layer 2G, the two memory chips 1 are electrically connected through a ground via 41G and a ground bonding part 42G.

It is to be noted that since the number of power supply wiring layers 2 is one more than the number of memory chips 1, one of the two power supply wiring layers 2 on the head and tail sides may not extend along the active surface 13 of the respective memory chip 1, that is, be disposed on the back surface of the respective memory chip 1. Other power supply wiring layers 2 are still disposed on the active surface 13 of the memory chips 1.

In a third example, the number of power supply wiring layers 2 may be less than the number of memory chips 1. For example, referring to FIG. 14 and FIG. 15, FIG. 14 is a partial cross-section view and FIG. 15 is a bottom view of the memory module 100 illustrated in FIG. 14. At least two adjacent memory chips 1 are bonded and form a chip set 10a. A power supply wiring layer 2 is provided between two adjacent chip sets 10a, and the power supply wiring layer 2 is electrically connected with the memory chips 1 of the chip sets 10a on both sides of the power supply wiring layer 2. One power supply wiring layer 2 is provided on each of two sides of the memory module 100, and is electrically connected with the respective chip set 10a on the side of the memory module 100.

That is, except that the two power supply wiring layers 2 on both sides are not shared by the chip sets 10a, each of other power supply wiring layers 2 in the middle is shared by the chip sets 10a on both sides of the respective power supply wiring layer 2. A power supply wiring layer 2 in the middle is connected to the power supply signal lines 12 of two chip sets 10a. It is to be noted that the smaller the number of the power supply wiring layers 2, the smaller the number of the solder bumps 51. Therefore, it is advantageous to increase the distance between the solder bumps 51 and the coils in the first wireless communication part 31 and the second wireless communication part 11, thereby reducing electromagnetic interference generated by the solder bumps 51 and the coils, so as to avoid the signal loss.

For example, each chip set 10a includes two memory chips 1, the power supply signal lines 12 having the same voltage signal in the two memory chips 1 are connected together through the conductive vias 41 and bonding parts 42.

Continuing to refer to FIG. 14 and FIG. 15, the sharing manner of the power supply wiring layer 2 will be described below. The first chip set 101 and the second chip set 102 share the ground wiring layer 2G, that is, the ground signal lines 12G of the first chip set 101 and the second chip set 102 are connected together through the ground via 41G and the ground bonding part 42G, and are led out through the ground wiring layer 2G between the first chip set 101 and the second chip set 102. Since the first chip set 101 and the second chip set 102 do not share the power source wiring layer 2P, the power source via 41P and the power source bonding part 42P of the first chip set 101 and the second chip set 102 will not be electrical connected. The second chip set 102 and the third chip set 103 share the power source wiring layer 2P, that is, the power source signal lines 12P of the second chip set 102 and the third chip set 103 are connected together through the power source via 41P and the power source bonding part 42P and are led out through the power source wiring layer 2P between the second chip set 102 and the third chip set 103.

In some embodiments, referring to FIG. 2, FIG. 3, FIG. 10, FIG. 12 and FIG. 14, the surface of the memory module 100 facing the logic chip 3 is further provided with an insulating film 71. The insulating film 71 may also be disposed between adjacent solder bumps 51, such that it can serve to insulate the solder bumps 51. In addition, the insulating film 71 may be made of a material with better adhesion property so as to serve as a fixation of the solder bumps 51. For example, the insulating film 71 may be a polyimide film. The polyimide film has properties of excellent high and low temperature resistance, electrical insulation and adhesion.

In some embodiments, there is also a filling adhesive layer 72 between the logic chip 3 and the memory chip 1, and the filling adhesive layer 72 covers the solder bumps 51. In addition, the filling adhesive layer 72 may cover the insulating film 71 and the solder pads 52. The filling adhesive layer