164b is electrically connected to the first amplifying element 161 and the balanced terminal 164c is electrically connected to the second amplifying element 162.

The interstage balun circuit 164 further includes a primary coil L10 and a secondary coil L11. One end of the primary coil L10 is electrically connected to the unbalanced terminal 164a. The other end of the primary coil L10 is electrically connected to ground. One end of the secondary coil L11 is electrically connected to the balanced terminal 164b and the other end of the secondary coil L11 is electrically connected to the balanced terminal 164c. Incidentally, the primary coil L10 and the secondary coil L11 may be formed of conductor pattern portions.

The high-frequency signals (transmission signals) outputted from the RF signal processing circuit 202 and amplified by the third amplifying element 163 are inputted into the unbalanced terminal 164a. The interstage balun circuit 164 carries out unbalanced-balanced transformation for the signals inputted into the unbalanced terminal 164a, outputs one signal of two signals having phases inverted to each other (two signals having phases shifted by 180 degrees relative to each other) to the first amplifying element 161, and outputs the other signal to the second amplifying element 162.

The first amplifying element 161 and the second amplifying element 162 each includes a heterojunction bipolar transistor (HBT) as a bipolar transistor, for instance.

The first amplifying element 161 includes a first input terminal 161a and a first output terminal 161b. The first input terminal 161a of the first amplifying element 161 is electrically connected to the balanced terminal 164b of the interstage balun circuit 164. The first output terminal 161b of the first amplifying element 161 is electrically connected to the output matching circuit 166 with the first wiring R1 interposed therebetween. The first amplifying element 161 amplifies the signals outputted from the balanced terminal 164b and outputs the signals to the output matching circuit 166.

The second amplifying element 162 includes a second input terminal 162a and a second output terminal 162b. The second input terminal 162a of the second amplifying element 162 is electrically connected to the balanced terminal 164c of the interstage balun circuit 164. The second output terminal 162b of the second amplifying element 162 is electrically connected to the output matching circuit 166 with the second wiring R2 interposed therebetween. The second amplifying element 162 amplifies the signals outputted from the balanced terminal 164c and outputs the signals to the output matching circuit 166.

The first wiring R1 is formed of a conductor pattern portion. One end of the first wiring R1 is electrically connected to the first output terminal 161b of the first amplifying element 161. The other end of the first wiring R1 is electrically connected to the output matching circuit 166.

The second wiring R2 is formed of a conductor pattern portion. One end of the second wiring R2 is electrically connected to the second output terminal 162b of the second amplifying element 162. The other end of the second wiring R2 is electrically connected to the output matching circuit 166.

The series circuit 165 is electrically connected between the first wiring R1 and the second wiring R2. The series circuit 165 includes an inductor Lc1 (first inductor), an inductor Lc2 (second inductor), and a capacitor C1 (first capacitor). The capacitor C1 is a chip capacitor, for instance. The inductor Lc1 and the inductor Lc2 are formed of conductor pattern portions. Inductance values of the inductor Lc1 and the inductor Lc2 are identical. The inductor Lc1 and the inductor Lc2 are mounted (placed) so as to be in line symmetry with respect to a specified axis, for instance. Thus, the inductance values of the inductor Lc1 and the inductor Lc2 can be made identical. Herein, “inductance values of the inductor Lc1 and the inductor Lc2 are identical” encompasses presence of the inductance value of the inductor Lc2 in ±20% range based on the inductance value of the inductor Lc1, other than complete coincidence between the inductance value of the inductor Lc1 and the inductance value of the inductor Lc2.

One end of the inductor Lc1 is electrically connected to the first wiring R1. The other end of the inductor Lc1 is connected to one end of the capacitor C1. The other end of the capacitor C1 is electrically connected to one end of the inductor Lc2. The other end of the inductor Lc2 is electrically connected to the second wiring R2. The series circuit 165 is not connected to the ground.

The series circuit 165 is a serial resonance circuit having an above configuration and attenuates an odd-order harmonic component, such as a third-order harmonic component, of a frequency of the transmission signals. The series circuit 165 attenuates harmonic components between a first value that is three times a lower limit of a communication band to which the transmission signals belong and a second value that is three times an upper limit of the communication band. For instance, the series circuit 165 attenuates a harmonic component of three times a center frequency of the communication band as a reference. That is, the series circuit 165 attenuates the harmonic component of three times the frequency of the transmission signals among the signals outputted from the first amplifying element 161. Further, the series circuit 165 attenuates the harmonic component of three times the frequency of the transmission signals among the signals outputted from the second amplifying element 162. That is, the series circuit 165 can be said to be a bypass circuit to bypass the harmonic components passing through the first wiring R1 and the second wiring R2 into the series circuit 165. Moreover, in other words, the series circuit 165 can be said to be an attenuation circuit because the series circuit 165 attenuates the harmonic components passing through the first wiring R1 and the second wiring R2.

The output matching circuit 166 is a so-called balun circuit. The output matching circuit 166 matches impedance between the differential amplifier 16A and the transmission filter 14. The output matching circuit 166 includes a plurality of (four in the illustrated example) inductors L1, L2, L3, and L4 and a capacitor C2 and configures a balun circuit. The output matching circuit 166 further includes a pair of balanced terminals 166a and 166b and an unbalanced terminal 166c. The inductors L1, L2, L3, and L4 are formed of conductor pattern portions. Incidentally, the inductors L1, L2, L3, and L4 may be chip inductors or the like.

The balanced terminal 166a is electrically connected to the first output terminal 161b of the first amplifying element 161 with the first wiring R1 interposed therebetween. The balanced terminal 166b is electrically connected to the second output terminal 162b of the second amplifying element 162 with the second wiring R2 interposed therebetween. The unbalanced terminal 166c is electrically connected to the serial resonance circuit 167 and the transmission filter 14.

The inductor L1 and the inductor L2 are serially connected. One end of the inductor L1 is electrically connected to the ground. The other end of the inductor L1 is electrically connected to one end of the inductor L2. The other end of the inductor L2 is electrically connected to the unbalanced terminal 166c. The inductor L3 and the inductor L4 are serially connected. One end of the inductor L3 is electrically connected to the balanced terminal 166a. The other end of the inductor L3 is electrically connected to one end of the inductor L4. The other end of the inductor L4 is electrically connected to the balanced terminal 166b. One end of the capacitor C2 is electrically connected to a point (such as midpoint) between the inductor L3 and the inductor L4. The other end of the capacitor C2 is electrically connected to the ground.

In the output matching circuit 166, the signals outputted from the first amplifying element 161 and the signals outputted from the second amplifying element undergo impedance transformation, while a state in which the phases are inverted is maintained. Thus, output impedance of the differential amplifier 16A undergoes impedance matching with input impedance of the transmission filter 14. The transmission signals having undergone the impedance matching are inputted into the transmission filter 14.

The serial resonance circuit 167 has one end electrically connected to the unbalanced terminal 166c and has the other end electrically connected to the ground. The serial resonance circuit 167 includes a capacitor C3 (second capacitor) and an inductor Lc3. The inductor Lc3 is formed of a conductor pattern portion. One end of the capacitor C3 is electrically connected to the unbalanced terminal 166c. The other end of the capacitor C3 is electrically connected to one end of the inductor Lc3. The other end of the inductor Lc3 is electrically connected to the ground. Incidentally, the inductor Lc3 may be a chip inductor or the like.

The serial resonance circuit 167 attenuates an even-order harmonic component, such as a second-order harmonic component, of the frequency of the transmission signals. The serial resonance circuit 167 attenuates harmonic components between a third value that is two times the lower limit of the communication band to which the transmission signals belong and a fourth value that is two times the upper limit of the communication band. For instance, the serial resonance circuit 167 attenuates a harmonic component of two times the center frequency of the communication band as the reference. That is, the serial resonance circuit 167 attenuates the harmonic component of two times the frequency of the transmission signals among the signals outputted from the output matching circuit 166.

As illustrated in FIG. 2, the differential amplifier circuit 16 further includes a plurality of (two in the illustrated example) inductors La1 (third inductor) and La2 (fourth inductor). The inductor La1 and the inductor La2 are formed of conductor pattern portions. Inductance values of the inductor La1 and the inductor La2 are identical. The inductor La1 and the inductor La2 are mounted (placed) so as to be in line symmetry with respect to a specified axis, for instance. Thus, the inductance values of the inductor La1 and the inductor La2 can be made identical. Herein, “inductance values of the inductor La1 and the inductor La2 are identical” encompasses presence, based on the inductance value of one (such as the inductor La1) of the inductors La1 and La2, of the inductance value of the other (such as the inductor La2) in ±20% range, other than complete coincidence between the inductance value of the inductor La1 and the inductance value of the inductor La2.

The inductor La1 is connected between the first output terminal 161b and the first wiring R1. The inductor La2 is connected between the second output terminal 162b and the second wiring R2. The inductors La1 and La2 regulate a phase of the harmonic component (harmonic component of three times (third order) the frequency of the transmission signals). Specifically, the inductors La1 and La2 regulate the phase of the harmonic component in an open direction.

(5) Effects

As described above, the high-frequency circuit 10 according to the embodiment includes the differential amplifier circuit 16. The differential amplifier circuit 16 includes the first amplifying element 161, the second amplifying element 162, the first wiring R1, the second wiring R2, and the series circuit 165. The first amplifying element 161 includes the first input terminal 161a and the first output terminal 161b. The second amplifying element 162 includes the second input terminal 162a and the second output terminal 162b. The first wiring R1 is connected to the first output terminal 161b. The second wiring R2 is connected to the second output terminal 162b. The series circuit 165 is connected between the first wiring R1 and the second wiring R2. The series circuit 165 includes the first inductor (inductor Lc1), the second inductor (inductor Lc2), and the capacitor C1.

According to this configuration, in case where the series circuit 165 is a serial resonance circuit, a harmonic component of the transmission signals in the differential amplification, such as the third-order harmonic component of the frequency of the transmission signals, can be attenuated.

Herein, frequency characteristics of the high-frequency circuit 10 including the series circuit 165 and a high-frequency circuit including no serial resonance circuit are illustrated in FIG. 3. A frequency band f0 illustrated in FIG. 3 is a band to which the frequency of the transmission signals belongs. A frequency band f1 illustrated in FIG. 3 is a frequency band that is three times the frequency band f0. That is, the frequency band f1 includes a third-order frequency of the frequency of the transmission signals. A solid line represents the frequency characteristics G1 of the high-frequency circuit 10 including the series circuit 165. A dashed line represents the frequency characteristics G2 of the high-frequency circuit including no serial resonance circuit. Incidentally, the second-order harmonic component of the frequency of the transmission signals is not mentioned in FIG. 3.

In the high-frequency circuit 10 of the embodiment, as apparent from the frequency characteristics G1, the signals are not attenuated in the frequency band f0, while the signals are attenuated in the frequency band f1. On the other hand, in the high-frequency circuit including no serial resonance circuit, the signals are not attenuated in both the frequency band f0 and the frequency band f1, as apparent from the frequency characteristics G2.

Therefore, the high-frequency circuit 10 of the embodiment is capable of carrying out a satisfactory communication, compared with the high-frequency circuit including no serial resonance circuit.

Meanwhile, the series circuit 165 is connected between the first wiring R1 and the second wiring R2. Compared with a case where a circuit (resonance circuit) to attenuate a harmonic component is provided in wiring, the high-frequency circuit 10 of the embodiment is capable of reducing loss of the transmission signals due to the resonance circuit.

Moreover, the high-frequency circuit 10 of the embodiment further includes the third inductor (inductor La1) and the fourth inductor (inductor La2). The third inductor is connected between the first output terminal 161b and the first wiring R1. The fourth inductor is connected between the second output terminal 162b and the second wiring R2.

According to this configuration, the phase of the third-order harmonic component of the frequency of the transmission signals can be regulated in the open direction.

Herein, frequency characteristics of the high-frequency circuit 10 (high-frequency circuit 10 of the embodiment) including the series circuit 165, the third inductor, and the fourth inductor and a high-frequency circuit not including the third inductor and the fourth inductor are illustrated in FIG. 4A. The frequency characteristics of the high-frequency circuit 10 of the embodiment and the high-frequency circuit (high-frequency circuit of a comparative example) not including the third inductor and the fourth inductor are illustrated in FIG. 4A. Herein, the high-frequency circuit of the comparative example includes a resonance circuit to attenuate the third-order harmonic component of the frequency of the transmission signals. FIG. 4A is a diagram representing the frequency characteristics in the frequency band f1. Incidentally, the second-order harmonic component of the frequency of the transmission signals is not mentioned in FIG. 4A.

Meanwhile, a Smith chart representing the phases of the third-order harmonic component of the frequency of the transmission signals in each of the high-frequency circuit 10 of the embodiment and the high-frequency circuit of the comparative example is illustrated in FIG. 4B.

ZA1 illustrated in FIG. 4B denotes the phase in the third-order frequency of the frequency of the transmission signals in the high-frequency circuit 10 of the embodiment. ZA2 illustrated in FIG. 4B denotes the phase in the third-order frequency of the frequency of the transmission signals in the high-frequency circuit of the comparative example.

As apparent from FIG. 4A, the frequency characteristics of the high-frequency circuit 10 of the embodiment and the high-frequency circuit of the comparative example are substantially identical. That is, both the high-frequency circuit 10 of the embodiment and the high-frequency circuit of the comparative example attenuate the third-order harmonic component of the frequency of the transmission signals.

Meanwhile, as apparent from FIG. 4B, the phase of the third-order harmonic component of the frequency of the transmission signals in the high-frequency circuit 10 of the embodiment is positioned on an open side, compared with the phase of the third-order harmonic component of the frequency of the transmission signals in the high-frequency circuit of the comparative example. That is, the high-frequency circuit is capable of regulating the phase of the third-order harmonic component of the frequency of the transmission signals in the open direction by including the third inductor and the fourth inductor.

Furthermore, the differential amplifier circuit 16 of the high-frequency circuit 10 of the embodiment includes the serial resonance circuit 167. The serial resonance circuit 167 has the one end connected to the unbalanced terminal 166c. The serial resonance circuit 167 includes the capacitor C2, different from the capacitor C1 of the series circuit 165, and the inductor Lc3.

According to this configuration, the harmonic component for the transmission signals in the differential amplification, such as the second-order harmonic component of the frequency of the transmission signals, can be attenuated.

Herein, frequency characteristics of the high-frequency circuit 10 including the series circuit 165 and the serial resonance circuit 167 (to be simply referred to as the high-frequency circuit 10 below) and a high-frequency circuit including no serial resonance circuit (high-frequency circuit of another comparative example) are illustrated in FIG. 5. The frequency band f0 illustrated in FIG. 5 is the band to which the frequency of the transmission signals belongs. The frequency band f1 illustrated in FIG. 5 is the frequency band that is three times the frequency band f0. That is, the frequency band f1 includes the frequency that is three times the frequency of the transmission signals. A frequency band f2 illustrated in FIG. 5 is a frequency band that is two times the frequency band f0. That is, the frequency band f2 includes a frequency that is two times the frequency of the transmission signals. A solid line represents the frequency characteristics G11 of the high-frequency circuit 10. A dashed line represents the frequency characteristics G12 of the high-frequency circuit of another comparative example.

In the high-frequency circuit 10, as apparent from the frequency characteristics G11, the signals are not attenuated in the frequency band f0, while the signals are attenuated in the frequency band f1 and the frequency band f2. On the other hand, in the high-frequency circuit of another comparative example, the signals are not attenuated in any frequency band of the frequency band f0, the frequency band f1, and the frequency band f2, as apparent from the frequency characteristics G12.

Therefore, the high-frequency circuit 10 is capable of carrying out a satisfactory transmission, compared with the high-frequency circuit of another comparative example.

(6) Specific Example

Herein, specific examples of structures of the inductors Lc1, Lc2, La1, and La2 will be described with use of FIGS. 6 to 7B.

As illustrated in FIGS. 6 and 7A, the first output terminal 161b and the second output terminal 162b of the differential amplifier 16A, the inductors Lc1 and Lc2, and the capacitor C1 are mounted on the main surface 301 of the mount substrate 300. The inductors Lc1 and Lc2 are placed as the conductor pattern portions on the main surface 301 of the mount substrate 300. As illustrated in FIG. 7B, the inductors La1 and La2 are placed as the conductor pattern portions on a dielectric layer 302 in the mount substrate 300.

The first output terminal 161b and the inductor La1 are electrically connected with a via B1 interposed therebetween. The second output terminal 162b and the inductor La2 are electrically connected with a via B2 interposed therebetween. The inductor La1 and the inductor Lc1 are electrically connected with a via B11 interposed therebetween. The inductor La2 and the inductor Lc2 are electrically connected with a via B12 interposed therebetween.

The inductor Lc1 and the inductor Lc2 are placed in line symmetry with respect to an axis extending through a center of the capacitor C1 and along a direction D1, in the plan view from the thickness direction of the mount substrate 300. A difference in impedance between the first output terminal 161b and the second output terminal 162b can be decreased by placement of the inductor Lc1 and the inductor Lc2 in line symmetry with respect to the axis extending through the center of the capacitor C1 and along the direction D1. That is, the inductance values of the inductor Lc1 and the inductor Lc2 can be made identical.

The inductor La1 and the inductor La2 are placed in line symmetry with respect to the axis extending through the center of the capacitor C1 and along the direction D1, in the plan view from the thickness direction of the mount substrate 300. A difference in impedance between the first output terminal 161b and the second output terminal 162b can be decreased by placement of the inductor La1 and the inductor La2 in line symmetry with respect to the axis extending through the center of the capacitor C1 and along the direction D1. The inductance values of the inductor La1 and the inductor La2 can be made identical.

Incidentally, though the inductor Lc1 and the inductor Lc2 are configured so as to be placed on the main surface 301 of the mount substrate 300 in the embodiment, there is no limitation to this configuration. The inductor Lc1 and the inductor Lc2 may be placed as conductor pattern portions on a dielectric layer in the mount substrate 300. Alternatively, a chip inductor may be mounted as the inductor Lc1 in or on the mount substrate 300. Similarly, a chip inductor may be mounted as the inductor Lc2 in or on the mount substrate 300.

Though the inductor La1 and the inductor La2 are configured so as to be placed as the conductor pattern portions on the dielectric layer 302 in the mount substrate 300, there is no limitation to this configuration. The inductor La1 and the inductor La2 may be placed as conductor pattern portions on the main surface 301. Alternatively, a chip inductor may be mounted as the inductor La1 in or on the mount substrate 300. Similarly, a chip inductor may be mounted as the inductor La2 in or on the mount substrate 300.

Though a configuration is provided in the embodiment in which the first output terminal 161b and the second output terminal 162b are placed on a surface closer to the mount substrate 300 of two surfaces of the differential amplifier 16A that are opposed to each other in the thickness direction of the mount substrate 300, there is no limitation to this configuration. A configuration may be used in which the first output terminal 161b and the second output terminal 162b are placed on a surface farther from the mount substrate 300 of the two surfaces of the differential amplifier 16A that are opposed to each other in the thickness direction of the mount substrate 300. In this case, the inductors La1 and La2 may be configured by wire bonding.

(7) Modification

Hereinbelow, modifications of the embodiment will be described.

(7.1) Modification 1

The inductors La1 and La2 are optional components of the high-frequency circuit 10. Even in case where the high-frequency circuit 10 does not include the inductors La1 and La2, the harmonic component for the transmission signals can be attenuated as illustrated in FIG. 4A, providing that the high-frequency circuit 10 includes the series circuit 165, as described above.

A structure of the inductors Lc1 and Lc2 in modification 1 will be described with use of FIG. 8.

The first output terminal 161b and the second output terminal 162b of the differential amplifier 16A, the inductors Lc1 and Lc2, and the capacitor C1 are mounted on the main surface 301 of the mount substrate 300 as illustrated in FIG. 8. The inductors Lc1 and Lc2 are placed as conductor pattern portions on the main surface 301 of the mount substrate 300.

The first output terminal 161b and the inductor Lc1 are electrically connected. The second output terminal 162b and the inductor Lc2 are electrically connected.

The inductor Lc1 and the inductor Lc2 are placed in line symmetry with respect to the axis extending through the center of the capacitor C1 and along the direction D1, in the plan view from the thickness direction of the mount substrate 300. The difference in impedance between the first output terminal 161b and the second output terminal 162b can be decreased by placement of the inductor Lc1 and the inductor Lc2 in line symmetry with respect to the axis extending through the center of the capacitor C1 and along the direction D1. That is, the inductance values of the inductor Lc1 and the inductor Lc2 can be made identical.

Incidentally, though the inductor Lc1 and the inductor Lc2 are configured so as to be placed on the main surface 301 of the mount substrate 300 in modification 1, there is no limitation to this configuration. The inductor Lc1 and the inductor Lc2 may be placed as conductor pattern portions on a dielectric layer in the mount substrate 300. Alternatively, a chip inductor may be mounted as the inductor Lc1 in or on the mount substrate 300. Similarly, a chip inductor may be mounted as the inductor Lc2 in or on the mount substrate 300.

Though the configuration is provided in modification 1 in which the first output terminal 161b and the second output terminal 162b are placed on the surface closer to the mount substrate 300 of the two surfaces of the differential amplifier 16A that are opposed to each other in the thickness direction of the mount substrate 300, there is no limitation to this configuration. The configuration may be used in which the first output terminal 161b and the second output terminal 162b are placed on the surface farther from the mount substrate 300 of the two surfaces of the differential amplifier 16A that are opposed to each other in the thickness direction of the mount substrate 300. In this case, the inductors La1 and La2 may be configured by wire bonding.

(7.2) Modification 2

A circuit mounted between the third amplifying element 163 and the first and second amplifying elements 161 and 162 is not limited to the interstage balun circuit 164. It is sufficient if a circuit that generates two signals having phases inverted to each other from one signal is provided between the third amplifying element 163 and the first and second amplifying elements 161 and 162.

(7.3) Modification 3

Though the high-frequency circuit 10 is used for the communication in the mid-band frequency band, there is no limitation thereto. The high-frequency circuit 10 may be used for communication in a low-band frequency band or may be used for communication in a high-band frequency band. Alternatively, the high-frequency circuit 10 may be used for ultra-high-band communication.

(7.4) Modification 4

Though the transmission filter 14 is configured so as to allow the passage therethrough of the one communication band, there is no limitation to this configuration. The transmission filter 14 may be configured so as to allow passage therethrough of a plurality of communication bands.

The series circuit 165 in modification 4 attenuates high-frequency signals between a first value that is three times the smallest lower limit among lower limits of the plurality of communication bands and a second value that is three times the greatest upper limit among upper limits of the plurality of communication bands.

(7.5) Modification 5
(7.5.1) First Standpoint

A modification at a standpoint with a view of the mount substrate 300 from an arrangement direction D1 (direction D1) will be described with use of FIGS. 9A to 9C. Herein, the arrangement direction D1 is a direction in which the output matching circuit 166 and the differential amplifier 16A are arranged, in the plan view from the thickness direction of the mount substrate 300.

In the view, from the arrangement direction D1, of the mount substrate 300, that is, the differential amplifier 16A, the output matching circuit 166, and the capacitor C1 included in the series circuit 165, the capacitor C1 may be placed on the mount substrate 300 so that a first portion that is at least a portion of the capacitor C1 overlaps with the output matching circuit 166 and so that a second portion that is at least a portion of the capacitor C1 overlaps with the differential amplifier 16A.

As illustrated in FIGS. 9A to 9C, for instance, the mount substrate 300 is a multilayer substrate and includes a first layer 300a, a second layer 300b, and a third layer 300c.

The first layer 300a includes the main surface 301, and the differential amplifier 16A, the capacitor C1 and the inductors Lc1 and Lc2 of the series circuit 165, and the inductor L2 of the output matching circuit 166 are placed on the first layer 300a (see FIG. 9A). The inductors Lc1 and Lc2 and the inductor L2 are each placed as a conductor pattern portion. The second layer 300b is an underlying layer for the first layer 300a and corresponds to the dielectric layer 302 described above. On the second layer 300b, the inductors La1 and La2 of the series circuit 165 and the inductors L3 and L4 of the output matching circuit 166 are placed (see FIG. 9B). The inductors La1 and La2 and the inductors L3 and L4 are each placed as a conductor pattern portion. The third layer 300c is an underlying layer for the second layer 300b, and the inductor L1 of the output matching circuit 166 is placed on the third layer 300c (see FIG. 9C). The inductor L1 is placed as a conductor pattern portion. A stacking direction for the first layer 300a, the second layer 300b, and the third layer 300c is the thickness direction of the mount substrate 300.

The inductor L2 and the inductor L1 are electrically connected with a via B20 interposed therebetween by stacking of the first layer 300a, the second layer 300b, and the third layer 300c. Further, the inductor Lc2, the inductor L4, and the inductor La2 are electrically connected with a via B21 interposed therebetween by the stacking of the first layer 300a, the second layer 300b, and the third layer 300c. Furthermore, the inductor Lc1, the inductor L3, and the inductor La1 are electrically connected with a via B22 interposed therebetween by the stacking of the first layer 300a, the second layer 300b, and the third layer 300c. The first output terminal 161b and the inductor La1 are electrically connected with the via B1 interposed therebetween. The second output terminal 162b and the inductor La2 are electrically connected with the via B2 interposed therebetween.

In the view from the arrangement direction D1, in this state, at least the portion (second portion) of the capacitor C1 overlaps with the differential amplifier 16A (see FIG. 9A).

Further, at least the portion (first portion) of the capacitor C1 overlaps with the output matching circuit 166 in the view from the arrangement direction D1. Specifically, at least the portion (first portion) of the capacitor C1 overlaps with the inductor L2 of the output matching circuit 166 in the view from the arrangement direction D1. That is, at least the portion (first portion) of the capacitor C1 is provided between two outer edges L2a and L2b of the inductor L2 that extend in the arrangement direction D1, in the view from the arrangement direction D1.

Further, the first portion of the capacitor C1 may be between the inductors L3 and L4 of the output matching circuit 166 in the view from the arrangement direction D1. That is, the first portion of the capacitor C1 may be provided between an outer edge L3a of the inductor L3 and an outer edge L4a of the inductor L4, in the view from the arrangement direction D1. Alternatively, the first portion of the capacitor C1 may overlap with the inductor L1 of the output matching circuit 166 in the view from the arrangement direction D1. That is, the first portion of the capacitor C1 may be provided between two outer edges L1a and L1b of the inductor L1 that extend in the arrangement direction D1, in the view from the arrangement direction D1.

Incidentally, the capacitor C1 may overlap with at least one of the output matching circuit 166 and the differential amplifier 16A in the view from the arrangement direction D1. In the first standpoint of modification 5, as illustrated in FIG. 9A, the capacitor C1 overlaps with both of the output matching circuit 166 and the differential amplifier 16A in the view of the mount substrate 300 from the arrangement direction D1.

Furthermore, the output matching circuit 166, the capacitor C1, and the differential amplifier 16A may be placed so that a center P2 of the capacitor C1 is aligned with at least one center of a center P1 of the output matching circuit 166 and a center P3 of the differential amplifier 16A along the arrangement direction D1 in the plan view from the thickness direction of the mount substrate 300. Herein, the center P2 of the capacitor C1 is aligned with the center P1 of the output matching circuit 166 and the center P3 of the differential amplifier 16A along the arrangement direction D1 in the plan view from the thickness direction of the mount substrate 300. More particularly, the center P2 of the capacitor C1, the center P1 of the output matching circuit 166, and the center P3 of the differential amplifier 16A exist on a straight line H1 along the arrangement direction D1 in the plan view from the thickness direction of the mount substrate 300. Herein, the center P1 of the output matching circuit 166 refers to a center of a rectangular area of the output matching circuit 166. Similarly, the center P2 of the capacitor C1 refers to a center of a rectangular area of the capacitor C1. Further, the center P3 of the differential amplifier 16A refers to a center of a rectangular area of the differential amplifier 16A.

In the first standpoint of modification 5, it is sufficient if the capacitor C1 is placed on the mount substrate 300 so that at least a portion of the capacitor C1 overlaps with the output matching circuit 166 and so that at least a portion of the capacitor C1 overlaps with the differential amplifier 16A, in the view from the arrangement direction D1. Therefore, order of arrangement of the output matching circuit 166, the series circuit 165, and the differential amplifier 16A in the arrangement direction D1 is not specified. That is, the capacitor C1, that is, the series circuit 165 is configured so as to be placed between the differential amplifier 16A and the output matching circuit 166 with respect to the arrangement direction D1 in FIGS. 9A to 9C, whereas there is no limitation to this configuration. The output matching circuit 166 may be placed between the series circuit 165 and the differential amplifier 16A with respect to the arrangement direction D1. Alternatively, the differential amplifier 16A may be placed between the series circuit 165 and the output matching circuit 166 with respect to the arrangement direction D1.

According to the first standpoint of modification 5, the capacitor C1 is placed on the mount substrate 300 so that at least the portion of the capacitor C1 overlaps with the output matching circuit 166 and so that at least the portion of the capacitor C1 overlaps with the differential amplifier 16A, in the view from the arrangement direction D1. According to this configuration, a length of the inductor La1 and the inductor Lc1 and a length of the inductor La2 and the inductor Lc2 between the differential amplifier 16A and the capacitor C1 can be balanced. That is, the length of the inductor La1 and the inductor Lc1 and the length of the inductor La2 and the inductor Lc2 between the differential amplifier 16A and the capacitor C1 can be made identical. Thus, a combined value (coupling amount) of inductance of the inductor La1 and the inductor Lc1 and a combined value (coupling amount) of inductance of the inductor La2 and the inductor Lc1 can be balanced. As a result, stabilization of operation during communication can be forwarded. Herein, the length of the inductor La1 and the inductor Lc1 refers to a length from the first output terminal 161b to the capacitor C1. The length of the inductor La2 and the inductor Lc2 refers to a length from the second output terminal 162b to the capacitor C1.

Though the inductors L1 to L4 of the output matching circuit 166 are each configured so as to be formed of the conductor pattern portion in the first standpoint of modification 5, there is no limitation to this configuration. The inductors L1 to L4 may be each formed of a chip inductor. Alternatively, the output matching circuit 166 may be made into one chip.

(7.5.2) Second Standpoint

A modification from a standpoint with a view from a direction D2 orthogonal to both of the thickness direction of the mount substrate 300 and the arrangement direction D1 of the output matching circuit 166 and the differential amplifier 16A will be described.

In the view from the direction D2, the capacitor C1 included in the series circuit 165 may be placed on the mount substrate 300 and between an outer edge 1601 farther from the output matching circuit 166 of two outer edges of the differential amplifier 16A along the direction D2 and an outer edge P101 farther from the differential amplifier 16A of two outer edges of the output matching circuit 166 along the direction D2 (see FIG. 9A). Herein, the outer edge P101 is a side, farther from the output matching circuit 166, of two sides of a smallest rectangle P10 enclosing the inductor L2 that extend along the direction D2.

Further, in the view from the direction D2, the capacitor C1 may be placed on the mount substrate 300 and between an outer edge that is a side, farther from the output matching circuit 166, of two sides of a smallest rectangle enclosing the inductors L3 and L4, the two sides extending along the direction D2, and the outer edge P101 of the differential amplifier 16A. Further, in the view of the mount substrate 300 from the direction D2, the capacitor C1 may be placed on the mount substrate 300 and between an outer edge that is a side, farther from the output matching circuit 166, of two sides of a smallest rectangle enclosing the inductor L1 that extend along the direction D2 and the outer edge P101 of the differential amplifier 16A.

In the second standpoint of modification 5, the capacitor C1 is placed between the output matching circuit 166 and the differential amplifier 16A in the plan view from the thickness direction of the mount substrate 300 (see FIG. 9A). In this case, in the view from the direction D2, the capacitor C1 is placed between the outer edge 1601 of the differential amplifier 16A and the outer edge P101 of the output matching circuit 166 and is placed so as not to overlap with either of the differential amplifier 16A and the output matching circuit 166. That is, the capacitor C1 is placed between an outer edge, closer to the output matching circuit 166, of the two outer edges of the differential amplifier 16A along the direction D2 and an outer edge, closer to the differential amplifier 16A, of the two outer edges of the output matching circuit 166 along the direction D2, in the view from the direction D2.

In the second standpoint of modification 5, it is sufficient if the capacitor C1 is placed between the outer edge (such as the outer edge P101), farther from the differential amplifier 16A, of the two outer edges of the output matching circuit 166 along the second direction and the outer edge 1601 of the differential amplifier 16A, in the view from the direction D2. Therefore, relation of placement among the capacitor C1, the output matching circuit 166, and the differential amplifier 16A in the view of the mount substrate 300 from the arrangement direction D1 is not specified. That is, at least a portion of the capacitor C1 does not have to overlap with the output matching circuit 166 in the view from the arrangement direction D1 in the second standpoint of modification 5. Furthermore, in the second standpoint of modification 5, at least a portion of the capacitor C1 does not have to overlap with the differential amplifier 16A.

According to the second standpoint of modification 5, the capacitor C1 is placed between the outer edge 1601 of the differential amplifier 16A and the outer edge P101 of the output matching circuit 166 in the view from the direction D2. Accordingly, lengths of the inductors La1 and La2 and lengths of the inductors Lc1 and Lc2 can be shortened, compared with a case where the capacitor C1 is placed on a side opposed to the differential amplifier 16A with respect to the outer edge P101 of the output matching circuit 166. That is, a path length between the first output terminal 161b and the capacitor C1 and a path length between the second output terminal 162b and the capacitor C1 can be shortened. Thus, the inductance values of the inductors La1 and La2 can be decreased. Additionally, the inductance values of the inductors Lc1 and Lc2 can be decreased. As a result, errors with respect to impedance values of impedance design for the high-frequency circuit 10 can be decreased.

Though the inductors L1 to L4 of the output matching circuit 166 are each configured so as to be formed of the conductor pattern portion in the second standpoint of modification 5, there is no limitation to this configuration. The inductors L1 to L4 may be each formed of a chip inductor, as with the first standpoint of modification 5. Alternatively, the output matching circuit 166 may be made into one chip.

Overview

As described above, the high-frequency circuit (10) of a first aspect includes the differential amplifier circuit (16). The differential amplifier circuit (16) includes the first amplifying element (161), the second amplifying element (162), the first wiring (R1), the second wiring (R2), and the series circuit (165). The first amplifying element (161) includes the first input terminal (161a) and the first output terminal (161b). The second amplifying element (162), the second input terminal (162a), and the second output terminal (162b) are provided. The first wiring (R1) is connected to the first output terminal (161b). The second wiring (R2) is connected to the second output terminal (162b). The series circuit (165) is connected between the first wiring (R1) and the second wiring (R2). The series circuit (165) includes the first inductor (such as the inductor Lc1), the second inductor (such as the inductor Lc2), and the capacitor (C1).

According to this configuration, in case where the series circuit (165) is a serial resonance circuit, a harmonic component for the transmission signals in the differential amplification, such as the odd-order (third-order, for instance) harmonic component of the frequency of the transmission signals, can be attenuated.

In the high-frequency circuit (10) of a second aspect, the differential amplifier circuit (16) further includes the third inductor (such as the inductor La1) and the fourth inductor (such as the inductor La2), in the first aspect. The third inductor is connected between the first output terminal (161b) and the first wiring (R1). The fourth inductor is connected between the second output terminal (162b) and the second wiring (R2).

According to this configuration, the phase of the harmonic component, such as the odd-order (third-order, for instance) harmonic component of the frequency of the transmission signals, can be regulated.

In the high-frequency circuit (10) of a third aspect, the inductance values of the third inductor and the fourth inductor are identical, in the second aspect.

According to this configuration, the difference in impedance between the first output terminal (161b) and the second output terminal (162b) can be decreased.

In the high-frequency circuit (10) of a fourth aspect, the inductance values of the first inductor and the second inductor are identical, in any of the first to third aspects.

According to this configuration, the difference in impedance between the first output terminal (161b) and the second output terminal (162b) can be decreased.

In the high-frequency circuit (10) of a fifth aspect, the capacitor (C1) is a chip capacitor, in any of the first to fourth aspects.

According to this configuration, Q value of the capacitor (C1) can be increased. Therefore, attenuation of the harmonic component can be increased. Further, an effect of improvement in insertion loss can be expected.

In the high-frequency circuit (10) of a sixth aspect, the differential amplifier circuit (16) further includes the balun circuit (such as the output matching circuit 166), in any of the first to fifth aspects. The balun circuit includes the pair of balanced terminals (166a, 166b) that are each connected to the first wiring (R1) and the second wiring (R2) and the unbalanced terminal (166c).

According to this configuration, signals having the odd-order harmonic component in the differential amplification attenuated can be outputted, for instance.