401 is exposed. Further, STI regions 501 and 502 have been formed. In an embodiment, STI regions 501 and 502 can comprise a dielectric material such as silicon dioxide or another suitable dielectric.

FIG. 6A illustrates a top-down view of an example, non-limiting, fifth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. As shown by FIG. 6A, one or more dummy gates, such as dummy gate 601 can be patterned across the substrate and a hardmask 602 can be patterned on top of the dummy gate 601. FIG. 6A further comprises lines 611, 612 and 613 utilized to illustrate cross-sections below.

FIGS. 6B, 6C and 6D illustrate various cross-sections of a fifth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 6B illustrates a cross-section along line 612 of FIG. 6A. As shown, dummy gate 601 has been patterned across the substrate with hardmask 602 patterned on top. In an embodiment, dummy gate 601 can comprise a material such as polysilicon, or another suitable material. FIG. 6C illustrates a cross-section along line 611 of FIG. 6A. As shown, no dummy gate is patterned over this portion of the semiconductor device. FIG. 6D illustrates a cross-section along line 613 of FIG. 6A. As shown, dummy gates 620, 601 and 630 have been patterned across the semiconductor device.

FIGS. 7A, 7B and 7C illustrate various cross-sections of a sixth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 7A illustrates a cross-section along line 612 of FIG. 6A, FIG. 7B illustrates a cross-section along line 611 of FIG. 6A, and FIG. 7C illustrates a cross-section along line 613 of FIG. 6A. As shown by FIGS. 7A, 7B and 7C SiGe55 layer 203 can be removed from the semiconductor device.

FIG. 8A illustrates a top-down view of an example, non-limiting, seventh stage of production of a semiconductor device, in accordance with one or more embodiments described herein. As shown by FIG. 8A, a spacer material 802 can be deposited on the sidewalls of dummy gate 620, 601 and 630. Additionally, as described in greater detail below, a bottom dielectric isolation (BDI) can be deposited in the areas vacated by the removal of SiGe55 layer 203. FIG. 8A further comprises lines 811, 812 and 813 utilized to illustrate cross-sections below.

FIGS. 8B, 8C and 8D illustrate various cross-sections of a seventh stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 8B illustrates a cross-section along line 811 of FIG. 8A. FIG. 8C illustrates a cross-section along line 812 of FIG. 8A. As shown, BDI layer 801 has been deposited in the regions vacated by SiGe55 layer 203. Further, BDI layer 801 can extend up the sidewalls of channels 804 and 805. FIG. 8D illustrates a cross-section along line 813 of FIG. 8A. As shown, spacer material 802 can be deposited along the sidewalls of the dummy gates. In an embodiment, BDI layer 801 and spacer material 802 can comprise the same material, such as a dielectric insulation material.

FIG. 9A illustrates a top-down view of an example, non-limiting, eighth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. As shown by FIG. 9A, an etching process can remove silicon layers 204 and SiGe30 layers 205 from regions of the semiconductor device not covered by the hardmask to expose BDI layer 801. FIG. 9A further comprises lines 911, 912 and 913 utilized to illustrate cross-sections below.

FIGS. 9B, 9C and 9D illustrate various cross-sections of an eighth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 9B illustrates a cross-section along line 912 of FIG. 9A. As shown, hardmask 602 protects the regions below during the etching process. FIG. 9C illustrates a cross-section along line 911 of FIG. 9A. As shown, since FIG. 9C is not covered by hardmask 602, the layers of silicon and SiGe30 can be removed by an etching process to expose BDI layer 801. FIG. 9D illustrates a cross-section along line 913 of FIG. 9A. As shown, portions of the silicon and SiGe30 layers not covered by hardmask 602 have been removed. Further, inner spacer 901 can be patterned on sidewall portion of the SiGe30 layers.

FIG. 10A illustrates a top-down view of an example, non-limiting, ninth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. As shown by FIG. 10A, an organic planarization layer (OPL) 1001 can be deposited on the semiconductor device and a channel 1002 can be patterned through OPL 1001. FIG. 10A further comprises lines 1011, 1012 and 1013 utilized to illustrate cross-sections below.

FIGS. 10B, 10C and 10D illustrate various cross-sections of a ninth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 10B illustrates a cross-section along line 1012 of FIG. 10A. FIG. 10C illustrates a cross-section along line 1011 of FIG. 10A. As shown by FIG. 10C, channel 1002 has been patterned through OPL 1001. In an embodiment, a portion of dielectric bar 401 can be exposed by channel 1002. FIG. 10D illustrates a cross-section along line 1013 of FIG. 10A. As shown, channel 1002 is patterned through OPL 1001.

FIG. 11A illustrates a top-down view of an example, non-limiting, tenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. As shown by FIG. 11A, a contact place holder 1101 can be deposited within channel 1002. In an embodiment, contact place holder 1101 can comprise a material such as TiOx, AlOx, SiC, or another suitable dielectric material. FIG. 11A further comprises lines 1111, 1112 and 1113 utilized to illustrate cross-sections below.

FIGS. 11B, 11C and 11D illustrate various cross-sections of a tenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 11B illustrates a cross-section along line 1112 of FIG. 11A. FIG. 11C illustrates a cross-section along line 1111 of FIG. 11A. FIG. 11D illustrates a cross-section along line 1113 of FIG. 11A. As shown by FIGS. 11C and 11D, contact place holder 1101 can be deposited in a bottom portion of channel 1002.

FIG. 12A illustrates a top-down view of an example, non-limiting, eleventh stage of production of a semiconductor device, in accordance with one or more embodiments described herein. As shown by FIG. 12A, OPL 1001 can be removed and source/drain epis 1201, 1202, 1203 and 1204 can be patterned. In an embodiment, source/drain epis 1201 and 1202 can be utilized for PFETs and source/drain epis 1203 and 1204 can be utilized for NFETs. FIG. 12A further comprises lines 1211, 1212 and 1213 utilized to illustrate cross-sections below.

FIGS. 12B, 12C and 12D illustrate various cross-sections of an eleventh stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 12B illustrates a cross-section along line 1212 of FIG. 12A. FIG. 12C illustrates a cross-section alone line 1211 of FIG. 12A. As shown, source/drain epis 1201, 1202, 1203 and 1204 have been patterned. As shown, source/drain epi 1201 is located adjacent to dielectric bar 401 and on top of the contact place holder. FIG. 12D illustrates a cross-section along line 1213 of FIG. 12A. As shown by FIG. 12D, source/drain epis 1201 and 1202 have been formed, wherein source/drain epi 1201 is located on top of the contact place holder.

FIG. 13A illustrates a top-down view of an example, non-limiting, twelfth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. As shown by FIG. 13A, a second OPL layer 1301 can be deposited between, dummy gates 620, 601 and 630. FIG. 13A further comprises lines 1311, 1312 and 1313 utilized to illustrate cross-sections below.

FIGS. 13B, 13C and 13D illustrate various cross-sections of a twelfth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 13B illustrates a cross-section along line 1312, FIG. 13C illustrates a cross-section along line 1311, and FIG. 13D illustrates a cross-section along line 1313. As shown by FIGS. 13B, 13C and 13D, second OPL layer 1301 can be deposited on the semiconductor device between dummy gates 620, 601 and 630.

FIGS. 14A, 14B and 14C illustrate various cross-sections of a thirteenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 14A illustrates a cross-section along line 1312, FIG. 14B illustrates a cross-section along line 1311, and FIG. 14C illustrates a cross-section along line 1313. As shown by FIG. 14C, spacer material 802 can be recessed to expose the sides of hardmask 602.

FIG. 15A illustrates a top-down view of an example, non-limiting, fourteenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. As shown by FIG. 15A, a second spacer 1501 can be deposited on the sidewalls of the exposed portions of hardmask 602. In an embodiment, second spacer 1501 can comprise materials such as AlN, AlOx, SiC, or another suitable material. FIG. 15A further comprises lines 1511, 1512 and 1513 utilized to illustrate cross-sections below.

FIGS. 15B, 15C and 15D illustrate various cross-sections of a fourteenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 15B illustrates a cross-section along line 1512, FIG. 15C illustrates a cross-section along line 1511, and FIG. 15D illustrates a cross-section along line 1513. As shown by FIG. 15D, second spacer 1501 has been deposited on the sidewalls of hardmask 602.

FIG. 16A illustrates a top-down view of an example, non-limiting, fifteenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. As shown, second OPL layer 1301 can be removed to facilitate removal of a portion of BDI layer 801. FIG. 16A further comprises lines 1611, 1612 and 1613 utilized to illustrate cross-sections below.

FIGS. 16B, 16C and 16D illustrate various cross-sections of a fifteenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 16B illustrates a cross-section along line 1612, FIG. 16C illustrates a cross-section along line 1611, and FIG. 16D illustrates a cross-section along line 1613. As shown by FIG. 16C, the portions of BDI layer 801 along the side walls of source/drain epis 1201, 1202, 1203 and 1204 can be removed.

FIG. 17A illustrates a top-down view of an example, non-limiting, sixteenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. As shown an intermediate layer dielectric (ILD) 1701 can be deposited between dummy gates 620, 601 and 630. In an embodiment, ILD 1701 can comprise SiO₂or another suitable dielectric material. FIG. 17A further comprises lines 1711, 1712 and 1713 utilized to illustrate cross-sections below.

FIGS. 17B, 17C and 17D illustrate various cross-sections of a sixteenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 17B illustrates a cross-section along line 1712, FIG. 17C illustrates a cross-section along line 1711, and FIG. 17D illustrates a cross-section along line 1713. As shown by FIGS. 17C and 17D, a liner 1702 can be deposited prior to deposition of ILD 1701. In an embodiment, liner 1702 can comprise a material such as SiN. In an embodiment, ILD 1701 can serve as a protective layer during later fabrication steps and liner 1702 can serve as an etch-stop layer for removal of ILD 1701.

FIGS. 18A, 18B and 18C illustrate various cross-sections of a seventeenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 18A illustrates a cross-section along line 1712, FIG. 18B illustrates a cross-section along line 1711, and FIG. 18C illustrates a cross-section along line 1713. As shown by FIG. 18A, hardmask 602, dummy gates 620, 601 and 630 and SiGe30 layers can be removed and replace by a metallization process to form gates 1801, 1802 and 1803. Gate cuts 1805 and 1806 can be patterned above STI regions 501 and 502. A second hardmask 1810 can then be patterned on top of the gates 1801, 1802 and 1803. As shown by FIG. 18B, ILD 1701 can protect portions of the semiconductor device during gate formation.

FIG. 19A illustrates a top-down view of an example, non-limiting, eighteenth stage of production of a semiconductor device in accordance with one or more embodiments described herein. As shown by FIG. 19A, ILD 1701 and liner 1702 can be removed after formation of gates 1801, 1802 and 1803 using an etching or other suitable process. For example, liner 1702 can serve as an etch-stop layer during removal of ILD 1701, and then can be removed. FIG. 19A further comprises lines 1911, 1912 and 1913 utilized to illustrate cross-sections below.

FIGS. 19B, 19C and 19D illustrate various cross-sections of an eighteenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 19B illustrates a cross-section along line 1912, FIG. 19C illustrates a cross-section along line 1911, and FIG. 19D illustrates a cross-section along line 1913. As shown, ILD 1701 and liner 1702 can be removed after formation of gates 1801, 1802 and 1803.

FIG. 20A illustrates a top-down view of an example, non-limiting, nineteenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. As shown by FIG. 20A, a metal layer 2001 can be deposited between gates 1801, 1802 and 1803. As will be described in greater detail below in further production stages, metal layer 2001 can be further formed to produce one or more contacts. In an embodiment, metal layer 2001 can comprise materials such as, but not limited to, aluminum, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, platinum, tantalum or another suitable metal. FIG. 20A further comprises lines 2011, 2012 and 2013 utilized to illustrate cross-sections below.

FIGS. 20B, 20C and 20D illustrate various cross-sections of a nineteenth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 20B illustrates a cross-section along line 2012, FIG. 20C illustrates a cross-section along line 2011, and FIG. 20D illustrates a cross-section along line 2013. As shown, metal layer 2001 can be deposited onto source/drain epis 1201, 1202, 1203 and 1204, and will facilitate production of contacts in further stages of production.

FIG. 21A illustrates a top-down view of an example, non-limiting, twentieth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. As shown, metal layer 2001 can be divided to form two or more metal contacts by deep contact cuts 2101 and 2102 and by shallow contact cut 2103. FIG. 21A further comprises lines 2111, 2112 and 2113 utilized to illustrate cross-sections below.

FIGS. 21B, 21C and 21D illustrate various cross-sections of a twentieth stage of production of a semiconductor device, in accordance with one or more embodiments described herein. FIG. 21B illustrates a cross-section along line 2112, FIG. 21C illustrates a cross-section along line 2111, and FIG. 21D illustrates a cross-section along line 2113. As shown, deep contact cuts 2101 and 2102 and shallow contact cut 2103 divide metal layer 2001 into contact 2122, 2121, 2120 and 2123, wherein each contact is in direct contact with a single source/drain epi. As shown, shallow contact cut 2103 can partially overlap with dielectric bar 401.

FIG. 22A illustrates a top-down view of an example, non-limiting further stage of production of a semiconductor device in accordance with one or more embodiments described herein. As shown, one or more vias, such as vias 2201,