In some implementations, a deposit 220 of an epoxy material (e.g., a combination of one or more deposits 220a-220c of the epoxy material) connect the footing structure 218 to the interposer 204. In some implementations, respective widths of the one or more deposits 220a-220c are proportional to respective widths of the one or more footing structures 218a-218c.

The lid component 214 further includes an access port 222 that provides access to the connector 208. For example, and in some implementations and as shown in FIG. 2A, the access port 222a (e.g., a top access port) passes through the top structure 216 to provide access to the connector 208.

In some implementations the semiconductor die package 206 (e.g., one or more IC dies including the IC die 212) generates an amount of heat. For example, the semiconductor die package 206 may generate up to approximately 3000 watts (W) of heat during a duty cycle of the IC die 212. However, other values and ranges for the amount of heat generated semiconductor die package 206 are within the scope of the present disclosure.

To dissipate heat from the semiconductor die package 206 so that a junction temperature of the IC die 212 (e.g., a temperature of a diode within the of the IC die 212) satisfies a threshold (e.g., remains at or below a target temperature in degrees Celsius), the fixture 202 may include a thermal interface material (TIM) 224 between a top surface of the semiconductor die package 206 and the top structure 216. The thermal interface material 224 may include combination of one or more thermally-conductive materials or structures. For example, the thermal interface material 224 may include a silicon-based gel material or an acrylic-based gel material. Additionally, or alternatively, the thermal interface material 224 may include a graphite material. Additionally, or alternatively, the thermal interface material 224 may include a combination of one or more carbon nanotubes. Additionally, or alternatively, the thermal interface material 224 may include an alloy material or a pure metal material including a tin (Sn) material, a silver (Ag) material, a gold (Au) material, a zinc (Zn) material, a bismuth (Bi) material, and/or an indium (In) material, among other examples.

In some implementations, and so that a performance of a thermal network including the thermal interface material 224 satisfies a threshold (e.g., a thermal-conductivity threshold in watts per meter Kelvin (W/m·K), among other examples), the thermal interface material 224 is compressed between the top surface of the semiconductor die package 206 and the top structure 216. Such a compression of the thermal interface material 224 enhance thermal contact (e.g., reduce thermal contact resistance) between the thermal interface material 224 and the top structure 216. Additionally, or alternatively, such a compression may enhance thermal contact (e.g., reduce thermal contact resistance) between the thermal interface material 224 and the top surface of the semiconductor die package 206.

In some implementations, the footing structures 218a-218c contribute to a moment of inertia of the lid component 214. In such cases, the moment of inertia may be such that a rigidity of the lid component 214 (e.g., a structural robustness) satisfies a bending moment threshold to maintain the compression of the thermal interface material 224. Additionally, or alternatively and relative to another lid component not including the footing structures 218a-218c, a likelihood of delamination of the top structure 216 from the thermal interface material 224 may be reduced.

Furthermore, the deposits 220a-220c of the epoxy material may retain the footing structure 218 (e.g., portions corresponding to the footing structures 218a-218c) to maintain the compression of the thermal interface material 224 between the top surface of the semiconductor die package 206 and the top structure 216.

In this way, a thermal performance of the fixture 202 (e.g., a thermal conductivity of the thermal network including the thermal interface material 224, among other examples) is maintained to satisfy a thermal performance threshold (e.g., a thermal performance threshold related to a rate of heat transferred or dissipated by the thermal network). By satisfying the thermal performance threshold, one or more IC dies (e.g., the IC die 212) may satisfy a junction temperature threshold (e.g., a temperature of a diode within the IC die 212). By satisfying the junction temperature threshold, the one or more IC dies may satisfy a circuitry performance threshold for compatibility with an application (e.g., a computing speed threshold or a refresh rate threshold, among other examples). Additionally, or alternatively, satisfying the thermal performance threshold (and the junction temperature threshold) may prolong a useful life of the semiconductor die package 206 including the one or more IC dies.

In the example implementation shown in FIG. 2B, the fixture 202 including the semiconductor die package 206 communicatively couples to a data source 228 using a cable 230. For example, the data source 228 may include a photonics source (e.g., a laser producing light waves, among other examples), the cable 230 may correspond to fiber-optic cable, and the connector 208 may correspond to an optical connector.

In some implementations, the fixture 202 communicatively couples to a computing resource 232 (e.g., the photonics tester tool included in the ATE tool set 120, among other examples). In some implementations, the interposer 204 communicatively couples to the computing resource 232 using one or more of an edge connector, a pogo-pin connector, a cabling component, and/or an interface board to which the fixture 202 is mounted, among other examples. The one or more IC dies of the semiconductor die package 206 (e.g., the IC die 212) may exchange information and/or data with the computing resource 232 to support the computing resource 232 executing an application (e.g., a testing application, among other examples).

As shown in FIG. 2B, the lid component 214 includes the footing structures 218a-218c. The cable 230 is routed through the access port 222a passing through the top structure 216 to connect with the connector 208. Furthermore, the cable 230 is routed between the footing structure 218b (e.g., an “inner” footing structure) and the thermal interface material 224.

As indicated above, FIGS. 2A and 2B are provided as an example. Other examples may differ from what is described with regard to FIGS. 2A and 2B.

FIGS. 3A and 3B are diagrams of an example implementation 300 of the fixture 202 described herein. FIG. 3A includes a top-view 302 including a footprint (e.g., a plan-view or a layout-view) of the footing structure 218, where the footing structure 218 includes portions having different widths. In FIG. 3A, the connector 208 is visible in the top-view 302 through the access port 222a (e.g., the access port 222a that passes through the top structure 216).

The fixture 202 may have one or more dimensional properties. For example, the fixture 202 have a length D1 that is included in a range of approximately 40 millimeters to approximately 200 millimeters. Additionally, or alternatively the fixture 202 may have a width D2 that is included in a range of approximately 40 millimeters to approximately 200 millimeters. However, other values and ranges for the length D1 and the width D2 are within the scope of the present disclosure.

Additionally, or alternatively, the access port 222a may have one or more dimensional properties. For example, the access port 222a may have a length D3 that is included in a range of approximately 0.4 millimeters to approximately 5 millimeters. Additionally, or alternatively, the access port 222a may have a width D4 that is included in a range of approximately 0.4 millimeters to approximately 5 millimeters. However, other values and ranges for the length D3 and the width D4 are within the scope of the present disclosure.

As shown in FIG. 3A, the footing structure 218 includes portions along an approximate perimeter 304 of the fixture 202 (and/or the lid component 214). As described in greater detail in connection with FIG. 3B with reference to the section line A-A, the footing structure 218 may extend from the approximate perimeter 304 to an underlying interposer (e.g., the interposer 204). Additionally, or alternatively and as described in greater detail in connection with FIG. 3B, portions of the footing structure 218 may include section areas having different widths.

FIG. 3B includes a cross-section view A-A of the fixture 202 taken along the section line A-A of FIG. 3A. As shown in FIG. 3B, the connector 208 is accessible through the access port 222a. Furthermore, the connector 208, the IC die 212, the footing structure 218a, and the footing structure 218d are visible in the cross-section view A-A. The footing structure 218d is adjacent to a side of the connector 208 (e.g., a first side), and the IC die 212 is adjacent to an opposite side (e.g., a second side) of the connector 208. Additionally, or alternatively, the footing structures 218a and 218d extend from the top structure 216 to the interposer 204. Further, and as shown in FIG. 3B, the connector 208, the IC die 212, the first section area of the footing structure 218, and the second section area of the footing structure 218 are in line with one another.

As shown in FIG. 3B, the footing structure 218d (in other words a first portion or first section area of the footing structure 218) includes a width D5. In some implementations, the width D5 is included in a range of approximately 2.0 millimeters to approximately 50.0 millimeters. If the width D5 is less than approximately 2.0 millimeters, a moment of inertia of the footing structure 218 (e.g., a rigidity) may be insufficient to prevent a bending flexure that causes delamination of the top structure 216 from the thermal interface material 224. If the width D5 is greater than approximately 50.0 millimeters, a size of the lid component 214 may increase to increase a cost of the fixture 202 and consume additional space in a system containing the fixture 202. However, other values and ranges for the width D5 are within the scope of the present disclosure.

Also, as shown in FIG. 3B, the footing structure 218a (in other words a second portion or second section area of the footing structure 218) includes a width D6. In some implementations, the width D6 is included in a range of approximately 0.2 millimeters to approximately 15.0 millimeters. If the width D6 is less, than approximately 0.2 millimeters, then an adhesive force provided by the deposit 220a of the epoxy material may be insufficient to prevent a separation of the lid component 214 from the interposer 204. If the width D6 is greater than approximately 15.0 millimeters, a size of the lid component 214 may increase to increase a cost of the fixture 202 and consume additional space in a system containing the fixture 202. However, other values and ranges for the width D6 are within the scope of the present disclosure.

As shown further in FIG. 3B, a deposit 220d (e.g., a first deposit) of the epoxy material may be proportional to the width D5, and the deposit 220a (e.g., a second deposit) of the epoxy material may be proportional to the width D6.

In some implementations, and as shown in FIG. 3B, the width D5 is greater relative to D6 (e.g., the widths of the footing structures 218d and 218a may be “uneven”). If the width D5 is equal to D6, or lesser relative to D6, a structural rigidity of the lid component 214 may be insufficient to reduce a likelihood of delamination of the top structure 216 from the thermal interface material 224. Additionally, or alternatively, a retention force provided by the deposits 220d and 220a of the epoxy material may be insufficient to reduce a likelihood of the lid component 214 (e.g., the footing structures 218d and 218a) from separating from the interposer 204.

Delamination of the top structure 216 from the thermal interface material 224, and/or separation of the lid component 214 from the interposer 204, may decrease an effectiveness of the thermal network including the thermal interface material 224 and compromise a performance of the IC die 212 during operation (e.g., reduce a computing speed and/or shorten a useful life, among other examples). However, other relationships of the width D6 relative to the width D5 are within the scope of the present disclosure.

As shown in FIGS. 3A and 3B, the implementation 300 of fixture 202 includes the interposer 204. The fixture 202 includes the semiconductor die package 206 that is mounted to the interposer 204 and that includes a connector 208 mounted to the substrate 210 and the IC die 212 mounted to the substrate 210. The fixture 202 includes the lid component 214 that is mounted to the interposer 204 and that includes the top structure 216 positioned above the semiconductor die package 206, an access port 222a configured to provide access to the connector, and the footing structure 218, where the footing structure extends from an approximate perimeter 304 of the lid component 214 to the interposer 204, where a first section area of the footing structure 218 (e.g., a section area corresponding to the footing structure 218d) is adjacent to a first side of the connector 208, where the first section area includes a first width (e.g., the width D5), where a second section area of the footing structure 218 (e.g., a section area corresponding to the footing structure 218a) is adjacent to a second side of the connector 208 that is opposite the first side, where the second section area includes a second width (e.g., the width D6) that is lesser relative to the first width, and where the connector 208, the IC die 212, the first section area of the footing structure 218, and the second section area of the footing structure 218 are in line with one another.

As indicated above, FIGS. 3A and 3B are provided as an example. Other examples may differ from what is described with regard to FIGS. 3A and 3B.

FIGS. 4A and 4B are diagrams of an example implementation 400 of the fixture 202 described herein. FIG. 4A includes a top-view 402 including a footprint (e.g., a plan-view or a layout-view) of the footing structure 218. A surface mount area 404 (e.g., a surface mount area for mounting one or more integrated circuit devices) may be located between the two or more portions of the footing structure 218. In FIG. 4A, the connector 208 is visible in the top-view 402 through the access port 222a (e.g., the access port 222a that passes through the top structure 216).

As shown in FIG. 4A, the footing structure 218 includes portions along the approximate perimeter 304 of the fixture 202 (and/or the lid component 214). As described in greater detail in connection with FIG. 4B with reference to the section line B-B, the footing structure 218 may include a portion extending from the approximate perimeter 304 to an underlying interposer (e.g., the interposer 204). Additionally, or alternatively and as described in greater detail in connection with FIG. 4B, the footing structure 218 may include one or more additional footing structures (e.g., inner portions) extending to the interposer 204.

FIG. 4B includes a cross-section view B-B of the fixture 202 taken along the section line B-B of FIG. 4A. As shown in FIG. 3B, the connector 208 is accessible through the access port 222a. Furthermore, the connector 208, the IC die 212, the footing structure 218a, the footing structure 218b, and the footing structure 218c are visible in the cross-section view B-B. The footing structure 218c (e.g., a first footing structure) is adjacent to a side of the connector 208 (e.g., a first side), and the IC die 212 is adjacent to an opposite side (e.g., a second side) of the connector 208. The footing structure 218b (e.g., a second footing structure or an “inner” footing structure) is located between the footing structure 218c and the connector 208. Additionally, or alternatively, the footing structures 218b and 218c extend from the top structure 216 to the interposer 204.

The IC device 226 may be mounted to the interposer 204 between the footing structures 218c and 218b (e.g., within the surface mount area 404). Examples of the IC device 226 include an integrated passive device such as a capacitor or a resistor, among other examples.

The fixture 202 includes the lid component 214 that is mounted to the interposer 204. The lid component 214 includes the top structure 216 positioned above the semiconductor die package 206. The lid component 214 includes an access port 222a configured to provide access to the connector 208. The lid component 214 includes a first footing structure (e.g., the footing structure 218c) extending from the top structure 216 to the interposer 204 and a second footing structure (e.g., the footing structure 218b) extending from the top structure 216 to the interposer 204, where the second footing structure is adjacent to a second side of the connector 208 that is opposite the first side, and where the second footing structure is between the connector 208 and the first footing structure.

As shown in FIGS. 4A and 4B, the implementation 400 of the fixture 202 includes the interposer 204. The fixture 202 includes the semiconductor die package 206 that is mounted to the interposer 204 and that includes the connector 208 mounted to the substrate 210 substrate 210 and the IC die 212 mounted to the substrate 210 adjacent to a first side of the connector 208. The fixture 202 includes the lid component 214 that is mounted to the interposer 204 and that includes the top structure 216 positioned above the semiconductor die package 206, an access port 222a configured to provide access to the connector 208, a first footing structure (e.g., the footing structure 218c) extending from the top structure to the interposer 204, and a second footing structure (e.g., the footing structure 218b) extending from the top structure 216 to the interposer 204, where the second footing structure is adjacent to a second side of the connector 208 that is opposite the first side, and where the second footing structure is between the connector 208 and the first footing structure.

As indicated above, FIGS. 4A and 4B are provided as an example. Other examples may differ from what is described with regard to FIGS. 4A and 4B.

FIG. 5 is a diagram of an example implementation 500 of the fixture 202 described herein. FIG. 5 includes a top-view 502 including a footprint (e.g., a plan-view or a layout-view) of the footing structure 218, where the footing structure 218 includes multiple portions and an extension structure 504 that connects at least two portions (e.g., the footing structures 218b and 218c, among other examples). As shown in FIG. 5, the footing structure 218 may include additional portions (e.g., the footing structures 218e and 218f, among other examples). The additional portions may be approximately orthogonal to one or more other portions of the footing structure 218 (e.g., approximately orthogonal to the footing structures 218b and 218c).

As indicated above, FIG. 5 is provided as an example. Other examples may differ from what is described with regard to FIG. 5.

FIGS. 6A and 6B are diagrams of an example implementation 600 of the fixture 202 described herein. FIG. 6A includes a top-view 602 including a footprint (e.g., a plan-view or a layout-view) of the footing structure 218, where the footing structure 218 includes portions having different widths. In FIG. 6A, the connector 208 is hidden in the top-view 602 and may be accessed through the access port 222b (e.g., a side access port) that passes through the footing structure 218 (e.g., through a sidewall of the lid component 214).

As shown in FIG. 6A, the footing structure 218 includes portions along the approximate perimeter 304 of the fixture 202 (and/or the lid component 214). As described in greater detail in connection with FIG. 6B with reference to the section line C-C, the footing structure 218 may extend from the approximate perimeter 304 to an underlying interposer (e.g., the interposer 204). Additionally, or alternatively and as described in greater detail in connection with FIG. 6B, portions of the footing structure 218 may include section areas having different widths.

FIG. 6B includes a cross-section view C-C of the fixture 202 taken along the section line C-C of FIG. 6A. As shown in FIG. 6B, the connector 208 is accessible through the access port 222b that passes through the footing structure 218d (e.g., through a sidewall of the lid component 214). Furthermore, the connector 208, the IC die 212, the footing structure 218a, and the footing structure 218d are visible in the cross-section view C-C. The footing structure 218d is adjacent to a side of the connector 208 (e.g., a first side), and the IC die 212 is adjacent to an opposite side (e.g., a second side) of the connector 208. Additionally, or alternatively, the footing structures 218a and 218d extend from the top structure 216 of the lid component 214 to the interposer 204.

As indicated above, FIGS. 6A and 6B are provided as an example. Other examples may differ from what is described with regard to FIGS. 6A and 6B.

FIGS. 7A and 7B are diagrams of an example implementation 700 of the fixture 202 described herein. FIG. 7A includes a top-view 702 including a footprint (e.g., a plan-view or a layout-view) of the footing structure 218. A surface mount area 404 (e.g., an area for mounting one or more integrated circuit devices) may between two or more portions of the footing structure 218. In FIG. 7A, the connector 208 is hidden in the top-view 702 and may be accessed through the access port 222b that passes through the footing structure 218b and 218c (e.g., through sidewalls of the lid component 214).

As shown in FIG. 7A, the footing structure 218 includes portions along the approximate perimeter 304 of the fixture 202 (and/or the lid component 214). As described in greater detail in connection with FIG. 7B with reference to the section line D-D, the footing structure 218 may include a portion extending from the approximate perimeter 304 to an underlying interposer (e.g., the interposer 204). Additionally, or alternatively, the footing structure 218 may include one or more additional footing structures (e.g., inner portions) extending to the interposer.

FIG. 7B includes a cross-section view D-D of the fixture 202 taken along the section line D-D of FIG. 7A. As shown in FIG. 7B, the connector 208 is accessible through the access port 222b that passes through the footing structures 218b and 218c. Furthermore, the connector 208, the IC die 212, the footing structure 218a, the footing structure 218b, and the footing structure 218c are visible in the cross-section view D-D. The footing structure 218c (e.g., a first footing structure) is adjacent to a side of the connector 208 (e.g., a first side), and the IC die 212 is adjacent to an opposite side (e.g., a second side) of the connector 208. The footing structure 218b (e.g., a second footing structure or an “inner” footing structure) is between the footing structure 218c and the connector 208. Additionally, or alternatively, the footing structures 218b and 218c extend from the top structure 216 of the lid component 214 to the interposer 204.

The IC device 226 may be mounted to the interposer 204 between the footing structures 218c and 218b (e.g., within the surface mount area 404).

As indicated above, FIGS. 7A and 7B are provided as an example. Other examples may differ from what is described with regard to FIGS. 7A and 7B.

FIGS. 8A-8F are diagrams of an example manufacturing process flow 800 described herein. In some implementations, the manufacturing process flow 800 uses one or more tools of the semiconductor processing tools 105-150 to form portions of the fixture 202 including the lid component 214. Furthermore, FIGS. 8A-8F show a section view E-E of the manufacturing process flow 800, which may correspond to one or more of the section views A-A through D-D shown in connection with FIG. 3B, 4B, 6B, or 7B.

As shown in FIG. 8A, one or more tools of the of the semiconductor processing tool sets 105-150 may perform a series of operations 802 to attach the semiconductor die package 206 to the interposer 204. For example, the pick-and-place tool and the reflow tool of the die-attach tool set 130 may attach the semiconductor die package 206 to the interposer 204. Additionally, or alternatively as part of the series of operations 802, the dispense tool of the encapsulation tool set 135 may dispense an encapsulant material 804 (e.g., an epoxy-resin based material) around the semiconductor die package 206.

As shown in FIG. 8B, one or more tools of the of the semiconductor processing tool sets 105-150 may perform a series of operations 806 to form the thermal interface material 224 on the top surface of the semiconductor die package 206. For example, the dispense tool of the encapsulation tool set 135 may dispense the thermal interface material 224 on the top surface of the semiconductor die package 206. Additionally, or alternatively, the pick-and-place tool of the die-attach tool set 130 may attach the thermal interface material 224 to the top surface of the semiconductor die package 206.

The thermal interface material 224 may be deposited such that the thermal interface material 224 includes one or more dimensional properties. For example, the thermal interface material 224 may be deposited such that the thermal interface material 224 has a thickness D7 that is included in a range of approximately 20 microns to approximately 300 microns. Additionally, or alternatively, the thermal interface material 224 may be deposited such that the thermal interface material 224 has a length (or width) D8 that is included in a range of approximately 20 millimeters to approximately 70 millimeters. However, other values and ranges for the thickness D7 and the length (or width) D8 are within the scope of the present disclosure.

As shown in FIG. 8C, one or more tools of the of the semiconductor processing tool sets 105-150 may perform a series of operations 808 to form the deposits 220 of the epoxy material on the interpose. For example, the dispense tool of the encapsulation tool set 135 may dispense the deposits 220 of the epoxy material on the interposer 204.

As shown in FIG. 8D, a series of operations 810 may include a stamping tool or an injection molding tool forming the lid component 214 including the top structure 216 and the footing structure 218. The lid component 214 may be formed to include one or more dimensional properties. For example, the lid component 214 may be formed to include a width (or length) D9 that is included in a range of approximately 35 millimeters to approximately 195 millimeters. However, other values and ranges for the width (or length) D8 are within the scope of the present disclosure.

Additionally, or alternatively, the series of operations 810 as shown in FIG. 8D may include one or more tools of the semiconductor processing tool sets 105-150 attaching the lid component 214 to the interposer 204. For example, the pick-and-place tool of the die-attach tool set 130 may attach the lid component 214 to the interposer 204 (e.g., attach the footing structure 218 to the deposits 220 of the epoxy material).

As shown in FIG. 8E, a clamping tool may compress the lid component 214 into deposits 220 of the epoxy material to form the fixture 202.

As shown in FIG. 8F, one or more tools of the of the semiconductor processing tool sets 105-150 may perform a series of operations 812 to cure the deposits 220 of the epoxy material (e.g., the fixture 202). For example, the curing tool (e.g., the furnace) of the PCB tool set 140 may cure the deposits 220 of the epoxy material to strengthen a bonding property of the deposits 220 of the epoxy material.

As indicated above, FIGS. 8A-8F are provided as an example. Other examples may differ from what is described with regard to FIGS. 8A-8F.

FIG. 9 is a diagram of example components of a device 900 described herein. In some implementations, one or more of the semiconductor processing tool sets 105-150 and/or the transport tool set 155 may include one or more devices 900 and/or one or more components of device 900. As shown in FIG. 9, device 900 may include a bus 910, a processor 920, a memory 930, an input component 940, an output component 950, and a communication component 960.

Bus 910 may include one or more components that enable wired and/or wireless communication among the components of device 900. Bus 910 may couple together two or more components of FIG. 9, such as via operative coupling, communicative coupling, electronic coupling, and/or electric coupling. Processor 920 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and/or another type of processing component. Processor 920 is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 920 may include one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

Memory 930 may include volatile and/or nonvolatile memory. For example, memory 930 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory). Memory 930 may include internal memory (e.g., RAM, ROM, or a hard disk drive) and/or removable memory (e.g., removable via a universal serial bus connection). Memory 930 may be a non-transitory computer-readable medium. Memory 930 stores information, instructions, and/or software (e.g., one or more software applications) related to the operation of device 900. In some implementations, memory 930 may include one or more memories that are coupled to one or more processors (e.g., processor 920), such as via bus 910.

Input component 940 enables device 900 to receive input, such as user input and/or sensed input. For example, input component 940 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, an accelerometer, a gyroscope, and/or an actuator. Output component 950 enables device 900 to provide output, such as via a display, a speaker, and/or a light-emitting diode. Communication component 960 enables device 900 to communicate with other devices via a wired connection and/or a wireless connection. For example, communication component 960 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.

Device 900 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 930) may store a set of instructions (e.g., one or more instructions or code) for execution by processor 920. Processor 920 may execute the set of instructions to perform one or more operations or processes described herein. In some implementations, execution of the set of instructions, by one or more processors 920, causes the one or more processors 920 and/or the device 900 to perform one or more operations or processes described herein. In some implementations, hardwired circuitry is used instead of or in combination with the instructions to perform one or more operations or processes described herein. Additionally, or alternatively, processor