216 with a lower PD, and for a greater amount of time for an RDL 216 with a higher PD. As merely one example, the Ar ion bombardment step 321 may be performed for about 10 seconds for an RDL 216 having a low PD and for about 30 seconds for an RDL 216 having a high PD. In various embodiments, the Ar ion bombardment step 321 serves to further enhance the rounding of the corners 319 of the RDL 216. It is further noted that in some examples, the density of the as-deposited RDL 216 may be modified (e.g., by modifying the deposition rate of the RDL 216), and as a result, the corner rounding of the RDL 216 provided by the etching process 315 (block 104) and the Ar ion bombardment step 321 (block 105) may be improved.

As noted above, FIG. 3C provides an enlarged view of a portion 311 of the workpiece 200 illustrated in FIG. 3 after the RDL 216 is patterned (e.g., after the Ar ion bombardment step 321 of block 105). In particular, the example of FIG. 3C provides an exemplary technique for measuring an extent of rounding of the corners 319 of the RDL 216. As shown, a circle may be drawn such that the surface of the rounded corners 319 overlaps with a portion of a circumference (an arc ‘S’) of the circle. A length of the arc ‘S’ may be determined according to the equation: arc length=2πR*(θ/360), where R is the radius of the circle and θ is the central angle of the arc ‘S’. In the example shown, the central angle θ is equal to about 90 degrees, and the radius R is in a range of about 200-210 nm. Thus, in the example of FIG. 3C, the length of the arc ‘S’ is in a range of about 314-330 nm. The length of the arc ‘S’ may thus be equivalently referred to as the length of the rounded portion of the corners 319 of the RDL 216.

FIG. 3D also provides an enlarged view of the portion 311 of the workpiece 200 illustrated in FIG. 3 after the RDL 216 is patterned (e.g., after the Ar ion bombardment step 321 of block 105), as previously noted. The example of FIG. 3D provides an exemplary alternative technique for measuring an extent of rounding of the corners 319 of the RDL 216. As shown, tangent lines can be drawn that are tangent to the sidewall surface of the patterned RDL 216 (tangent line A) and tangent to the top surface of the patterned RDL 216 (tangent line B). As shown, the two tangent lines A and B intersect at a point C. In an example, the corner rounding can then be described as a distance D between the intersection point C and the rounded surface of the RDL 216. In some embodiments, this may also be described as a distance D by which the corner of the patterned RDL 216 has “withdrawn” from the intersection point C due to the corner rounding. In various embodiments, the distance D may be greater than or equal to about 70 nm.

Referring now to FIGS. 1 and 4, the method 100 includes a block 106 where a first dielectric layer 220 is deposited over the patterned RDL 216 that includes the first conductive feature 216-1 and the second conductive feature 216-2, including within the recess 218. As noted above, and in some embodiments, since the nitride layer 302 remains over the RDL 216, the first dielectric layer 220 may be deposited over the nitride layer 302. In some embodiments, the first dielectric layer 220 includes silicon oxide and may be formed using chemical vapor deposition (CVD), sub-atmospheric CVD (SACVD), or plasma-enhanced CVD (PECVD). In some implementations, the first dielectric layer 220 may be an undoped silicate glass (USG) layer formed to a thickness between about 1500 Angstroms (Å) and about 5000 Å. In at least some examples, the first dielectric layer 220 has a thickness of about 4000 Å. As shown in the example of FIG. 4, in some embodiments and due to the aspect ratio of the recess 218 and/or to the deposition process used to deposit the dielectric layer 220, the deposited first dielectric layer 220 may accumulate over the corners 319 of the RDL 216 adjacent to the recess 218 to form overhang regions 419. As a result, the as-deposited thickness of the first dielectric layer 220 may be non-conformal. For example, the first dielectric 220 may have a thickness ‘T1’ between about 3000 Å and about 5000 Å along a top surface of the RDL 216 (on a first side of the overhang region 419) and a thickness ‘T2’ between about 2000 Å and about 4000 Å along a sidewall surface of the RDL 216 within the recess 218 (on a second side of the overhang region 419).

Referring now to FIGS. 1 and 5, the method 100 includes a block 107 where a nitride layer 227 is deposited over the first dielectric layer 220, including within the recess 218 and over the overhang regions 419. In some embodiments, the nitride layer 227 includes silicon nitride (SiN) and may be formed using CVD, SACVD, or PECVD. In some implementations, the nitride layer 227 may be formed to a thickness between about 675 Å and about 825 Å. In at least some cases, the nitride layer 227 may be formed to a thickness of about 750 Å. In some examples, the nitride layer 227 may serve as an etch-stop layer. Moreover, as the nitride layer 227 has a high Young's modulus, the nitride layer 227 can constrain the RDL 216 during subsequent annealing processes and cause residual stress to form in the RDL 216. In accordance with some embodiments, and as described further below, portions of the nitride layer 227 at the overhang regions 419 (and over the corners 319) can be removed (or chopped) so as to release the residual stress from corners 319 of the RDL 216 where such stress can accumulate.

Referring now to FIGS. 1, 6, 7, and 8, the method 100 includes a block 108 where a second dielectric layer 222 is formed. The second dielectric layer 222 is formed using a deposition technique different from the one used to deposit the first dielectric layer 220. In some embodiments, the second dielectric layer 222 includes silicon oxide and may be deposited using a high-density plasma chemical vapor deposition (HDPCVD) process. In various examples, the HDPCVD deposition of the second dielectric layer 222 includes alternating deposition and etching-back cycles to chop portions of the nitride layer 227 in the overhang regions 419, thereby releasing residual stress from corners 319 of the RDL 216. The HDPCVD deposition also provides excellent gap fill (e.g., of the recess 218) and a void-free dielectric layer (the second dielectric layer 222) over the RDL 216. In some cases, the various deposition and etching-back cycles may be performed at different radio frequency (RF) power values and/or at different pressures, as discussed below. Also, in some embodiments, the deposition and etching-back cycles may occur concurrently, with a net positive deposition rate.

By way of example, and as shown in FIG. 6, the HDPCVD deposition of the second dielectric layer 222 begins with a first deposition of the second dielectric layer 222 (denoted in FIG. 7 as 222-1) over the nitride layer 227, including within the recess 218 and over the overhang regions 419. In an example, the first deposition of the second dielectric layer 222 may be performed at an RF power of between about 4.7 kW and about 6.7 kW, such as for instance about 5.7 kW, and at a pressure in a range of between about 4E-3 Torr and 5E-3 Torr. In some implementations, the first deposition of the second dielectric layer 222-1 may be formed to a thickness between about 250 nm and about 350 nm along a top surface 602 of the workpiece 200. In at least some examples, the first deposition of the second dielectric layer 222-1 may have a thickness of about 300 nm. It is noted that due to the overhang regions 419, the first deposition of the second dielectric layer 222-1 may be thinner within the recess 218 (e.g., such as along sidewalls of the recess 218) as compared to the top surface 602.

After the first deposition of the second dielectric layer 222-1, the HDPCVD process continues with an etching-back process. With reference to FIG. 7, an etching-back process is performed (e.g., using an oxygen-containing species, such as high-energy oxygen atoms) to remove a portion of the previously deposited first deposition of the second dielectric layer 222-1. In some embodiments, the etching-back process is performed at a high RF power of about 8 kW and at a pressure of about 9E-3 Torr. In some embodiments, the etching-back process may be performed at an RF power of between about 7 kW and about 9 kW, and at a pressure in a range of between about 10E-2 Torr and 10E-3 Torr. In some cases, the etching-back process may cause thinning of a thickness of the first deposition of the second dielectric layer 222-1 along the top surface 602. More particularly, the etching-back process may preferentially etch the workpiece 200 at or near the overhang regions 419. As a result, the etching-back process may remove (or chop) corners of the first deposition of the second dielectric layer 222-1, the nitride layer 227, and the first dielectric layer 220 in the overhang regions 419 to form etched surfaces 719 that define a discontinuity region 721 in the nitride layer 227. As shown, the discontinuity region 721 in the nitride layer 227 is substantially aligned with the corners 319 of the RDL 216, thereby providing for residual stress from the corners 319 of the RDL 216 to be released.

After performing the etching-back process to form the etched surfaces 719, and as shown in FIG. 8, the HDPCVD process continues with a second deposition of the second dielectric layer 222 over the first deposition of the second dielectric layer 222-1 (on the top surface 602 and within the recess 218), and over the etched surfaces 719 that include the discontinuity region 721 in the nitride layer 227. In some embodiments, the second deposition of the second dielectric layer 222 is performed at a low RF power of about 5.7 kW and at a pressure of about 4.5E-3 Torr. In some embodiments, the second deposition of the second dielectric layer 222 may be performed at an RF power of between about 4.7 kW and about 6.7 kW, and at a pressure in a range of between about 4E-3 Torr and 5E-3 Torr. In some implementations, the second deposition of the second dielectric layer 222 may be formed to a thickness between about 2,225 nm and about 2,750 nm. In at least some examples, the second deposition of the second dielectric layer 222 may have a thickness of about 2,500 nm. In one example, a total thickness ‘T3’ of the second dielectric layer 222, which includes the net deposition of both the first and second depositions of the second dielectric layer 222, may be about 2,700 nm.

It is noted that while after the second deposition of the second dielectric layer 222 the recess 218 is substantially filled, because of the topography of the workpiece 200, a dent 218′ remains. In some embodiments, the second dielectric layer 222 is deposited to the thickness ‘T3’ to ensure that a bottom surface 221 of the dent 218′ is higher (farther away from the substrate 202) than a top surface 219 of the RDL 216. When the bottom surface 221 is higher (farther away from the substrate 202) than the top surface 219, the first conductive feature 216-1 and the second conductive feature 216-2 are spaced apart by portions of the first dielectric layer 220, the nitride layer 227, and the second dielectric layer 222, and a third dielectric layer 224 (shown in FIG. 9) does not extend between the first conductive feature 216-1 and the second conductive feature 216-2. That means the first conductive feature 216-1 and the second conductive feature 216-2 are separated largely by the second dielectric layer 222, which may include high-quality and substantially void-free silicon oxide deposited using HDPCVD.

Referring now to FIGS. 1 and 9, the method 100 includes a block 110 where a third dielectric layer 224 is deposited over the second dielectric layer 222. The third dielectric layer 224 is deposited using a deposition technique different from the one used to deposit the second dielectric layer 222. In some embodiments, the third dielectric layer 224 includes silicon oxide and may be deposited using CVD, SACVD, or PECVD. In some implementations, the third dielectric layer 224 may be an undoped silicate glass (USG) layer formed to a thickness ‘T4’ between about 8,000 Angstroms (Å) and about 10,000 Å. The thickness ‘T4’ is selected such that a lowest top surface of the third dielectric layer 224 is higher (farther away from the substrate 202) than a top surface of the second dielectric layer 222. This arrangement helps to ensure that after the planarization process at block 112 (described below), the workpiece 200 would include a level top surface.

Referring now to FIGS. 1 and 10, the method 100 includes a block 112 where a top surface of the workpiece 200 is planarized to provide a level top surface 226. In some embodiments, the workpiece 200 is planarized using CMP. Portions of the third dielectric layer 224 and the second dielectric layer 222 are removed at block 112 to produce the level top surface 226. In some embodiments, and after the CMP process, the total thickness ‘T3’ of the second dielectric layer 222 may be between about 900 nm and about 1,500 nm. As illustrated in FIG. 10, the level top surface 226 includes a portion of the third dielectric layer 224 and a portion of the second dielectric layer 222.

Referring to FIGS. 1 and 11, the method 100 includes a block 114 where a fourth dielectric layer 228 is deposited over the level top surface 226. In some embodiments, the fourth dielectric layer 228 may be a nitrogen-containing dielectric material such as silicon nitride or silicon carbonitride and may be deposited using CVD, PECVD, HDPCVD, SACVD, or a suitable deposition technique. In one embodiment, the fourth dielectric layer 228 is formed of silicon nitride. Because the fourth dielectric layer 228 is deposited over and in direct contact with the level top surface 226, the fourth dielectric layer 228 is planar and does not extend downward (towards the substrate 202) into either the third dielectric layer 224 or the second dielectric layer 222. In some implementations, the fourth dielectric layer 228 is formed to a thickness between about 4,000 Å and about 10,000 Å, including about 7,000 Å. In some cases, the fourth dielectric layer 228 is a barrier layer, for example protecting against moisture or other contaminants, to protect the underlying elements of the workpiece 200. The first dielectric layer 220, the nitride layer 227, the planarized second dielectric layer 222, the planarized third dielectric layer 224, and the fourth dielectric layer 228 may be regarded as a second passivation layer 230. As illustrated in FIG. 11, the RDL 216, such as the first conductive feature 216-1 and the second conductive feature 216-2, is thus sandwiched between the underlying first passivation layer 212 and the overlying second passivation layer 230.

Referring to FIGS. 1 and 12, the method 100 includes a block 116 where a bonding layer 250 is formed over the fourth dielectric layer 228. In some embodiments, the bonding layer 250 may include an oxide or nitrogen-containing dielectric material such as SiO₂, SiN, SiON, SiCN, or SiOCN and may be deposited using CVD, PECVD, HDPCVD, SACVD, or a suitable deposition technique. In one embodiment, the bonding layer 250 is formed of SiON. In some cases, the bonding layer 250 provides for improved bonding between the workpiece 200 (which may include a first die) and another workpiece (which may include a second die), for example, as part of a subsequent die-to-die stacking process.

Still referring to FIGS. 1 and 12, the method 100 includes a block 118 where contact features, such as a contact feature 240 including a conductive via portion 240A and a conductive line portion 240B, are formed. Initially, a contact recess may be formed through the bonding layer 250, the fourth dielectric layer 228, the second dielectric layer 222, the nitride layer 227, and the first dielectric layer 220 to expose the first conductive feature 216-1. After forming the contact recess, a metal layer is deposited therein to form the contact feature 240. The contact features, such as the contact feature 240, may be formed of copper, nickel, cobalt, aluminum, gold, silver, palladium, tin, bismuth, or an alloy thereof and may be deposited by electroplating, evaporation, electroless plating, sputter deposition, or other suitable technique. In an example, the contact feature 240 is formed of copper. After formation of the contact feature 240, a CMP process may be performed to remove excess material and planarize a top surface of the workpiece 200. In some embodiments, the first conductive feature 216-1 thus serves as a contact pad to engage the contact feature 240 formed there above. In some examples, a contact feature may be similarly formed to engage the second conductive feature 216-2, and other contact features may also be formed to engage other conductive features (e.g., of the RDL 216) not explicitly shown.

Referring to FIGS. 1 and 13, the method 100 includes a block 120 where a bonding process is performed. In an example, the bonding process may be a hybrid bonding process which includes bonding of metal pads (e.g., such as the conductive line portion 240B of the contact feature 240) and the surrounding dielectric material (e.g., such as the bonding layer 250) of two IC chips (die), two wafers, or a die and a wafer to create a low profile, low parasitic, high-performance interconnect therebetween. In the example of FIG. 13, the workpiece 200 provides a first die 200 (or IC chip), and another workpiece 201 may be similarly processed according to the method 100 to provide a second die 201 (or IC chip) which can be bonded to the first 200 die as part of the bonding process. In the example shown, the second die 201 may be flipped so that a front side 205 of the first die 200 faces, and is in contact with, a front side 205-1 of the second die 201. It is noted that prior to contacting the first die 200 and the second die 201, a surface activation process may be performed to each of the front side 205 of the first die 200 and the front side 205-1 of the second die 201. In some embodiments, the surface activation may include a plasma treatment process (e.g., such as using an Ar plasma) to increase the bonding energy of the bonding layer 250 of the first die 200 and a bonding layer 250-1 of the second die 201.

After the surface activation process, and using a high precision alignment process, the front side 205 of the first die 200 may be brought into contact with the front side 205-1 of the second die 201 along an interface 207 such that the conductive line portion 240B of the first die 200 is substantially aligned with a conductive line portion 240B-1 of the second die 201. In some embodiments, the surfaces of the bonding layer 250 and the bonding layer 250-1, which are now in contact with each other along the interface 207, may form covalent bonds and/or may be attracted to each other by van der Waals forces. In some cases, the bonding of the surfaces of the bonding layer 250 and the bonding layer 250-1 may occur at room temperature. Once the front side 205 of the first die 200 is brought into contact with the front side 205-1 of the second die 201, an annealing process may be performed to form an electrical connection between the conductive line portion 240B of the first die 200 and the conductive line portion 240B-1 of the second die 201. In some cases, the annealing process may be performed at a temperature between about 200 degrees Celsius and about 400 degrees Celsius. As an example, for instance when the contact features 240 are formed of copper, the annealing process may result in volume expansion of the copper, including filling of any gaps that may have been present between the conductive line portion 240B and the conductive line portion 240B-1 (e.g., due to CMP dishing), thereby completing the electrical connection between the conductive line portion 240B and the conductive line portion 240B-1. It is noted that in accordance with various embodiments which provide for the release of residual stress from the RDL 216, the formation of cracks (e.g., in the second passivation layer 230) can be substantially avoided during the annealing process to form the electrical connection between the conductive line portions 240B, 240B-1, as well as during other annealing processes that may be performed during fabrication of the first die 200 and the second die 201. As a result, device yield and reliability are enhanced, and the process of bonding of the first die 200 to the second die 201 is improved.

Referring now to FIG. 14, illustrated therein is a flowchart illustrating a method 150 for fabricating a semiconductor device according to some alternative embodiments of the present disclosure. The method 150 is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated in the method 150. Additional steps can be provided before, during, and after the method 150, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method. Not all steps are described herein in detail for reasons of simplicity. The method 150 is described below in conjunction with FIGS. 15-22, which provide cross-sectional views of the workpiece 200 at different stages of fabrication according to embodiments of the present disclosure. It is noted that the method 150 is substantially similar to the method 100, described above. As such, the discussion of the method 150 provided below focuses primarily on the differences between the methods 100, 150. Moreover, unless otherwise stated, like reference numerals in the figures may refer to the same features or elements previously described.

Referring to FIGS. 14 and 15, the method 150 includes the block 102 where the workpiece 200 that includes the RDL 216 is received. In some embodiments, the workpiece 200 may be substantially the same as described above with reference to the example of FIG. 2. Still referring to FIGS. 14 and 15, instead of initially patterning the RDL 216 as in the method 100, the method 150 first proceeds to the block 106 where the first dielectric layer 220 is deposited over the RDL 216. After depositing the first dielectric layer 220, and still with reference to FIGS. 14 and 15, the method 150 proceeds to the block 107 where the nitride layer 227 is deposited over the first dielectric layer 220. It is noted that in at least some embodiments, the first dielectric layer 220 may not be formed and instead the nitride layer 227 may be formed directly over the nitride layer 302 (e.g., such as SiON) that remains over the RDL 216 (e.g., as shown in FIG. 3B).

Referring to FIGS. 14 and 16, the method 150 includes a block 104′ where the RDL 216, the first dielectric layer 220, and the nitride layer 227 are patterned to form the recess 218 and corners 319 of the RDL 216 are rounded. A shown in FIG. 16, the recess 218 extends through the nitride layer 227, the first dielectric layer 220, and the RDL 216 to electrically separate the RDL 216 into the first conductive feature 216-1 and the second conductive feature 216-2. The etching process 315 may be used to pattern and round the corners 319 of the RDL 216, as previously described. However, in some embodiments of the method 150, since the dielectric layer 220 and the nitride layer 227 are deposited prior to the patterning and rounding process, corners of the dielectric layer 220 and the nitride layer 227 (disposed directly above the corners 319 of the RDL 216) may likewise be rounded by the etching process 315. More particularly, since the nitride layer 227 is deposited prior to the patterning and rounding process of block 104′, the nitride layer 227 is absent from the recess 218 (and thus absent from sidewalls of the RDL 216), in contrast to the method 100. In other words, the nitride layer 227 is only formed over a top surface the RDL 216 and not over sidewalls of the RDL 216. As a result, constraint on the RDL 216 by the nitride layer 227 will be significantly reduced and residual stress from the RDL 216 will be released. Further, as the nitride layer 227 may be used as an etch-stop layer, formation of the nitride layer 227 over only the top surface of the RDL 216 will reduce an etch-stop layer area by greater than about 20%, including about 24%. In some cases, this may also help to reduce formation of voids in or adjacent to the RDL 216.

After the patterning and rounding process of block 104′, the method 150 includes the block 105 where the corners 319 of the RDL 216 (and in some embodiments corners of the dielectric layer 220 and the nitride layer 227 disposed directly over the corners 319 of the RDL 216) are further rounded. In some embodiments, the further rounding may be performed by using the Ar ion bombardment step 321, as described above.

Referring to FIGS. 14 and 17, the method 150 includes the block 108 where the second dielectric layer 222 is formed. The second dielectric layer 222 may include silicon oxide and may be formed using an HDPCVD process, as described above. In the method 150, and in some embodiments, since the nitride layer 227 is not formed along sidewalls of the RDL 216, chopping portions of the nitride layer 227 near the corners 319 may not be necessary (or at least is an optional step). Thus, in some examples of the method 150, the various deposition and etching-back cycles of the HDPCVD may be performed at a substantially constant RF power value and pressure. For instance, in some embodiments, the second dielectric layer 222 may be deposited at a low RF power of about 5.7 kW and at a pressure of about 4.5E-3 Torr. In some embodiments, the second dielectric layer 222 may be deposited at an RF power of between about 4.7 kW and about 6.7 kW, and at a pressure in a range of between about 4E-3 Torr and 5E-3 Torr. In some implementations, the second dielectric layer 222 may be formed to a thickness of about 2,700 nm.

Referring now to FIGS. 14 and 18, the method 150 includes the block 110 where the third dielectric layer 224 is deposited over the second dielectric layer 222. In some embodiments, the third dielectric layer 224 may be substantially the same as described above. Referring to FIGS. 14 and 19, the method 150 also includes the block 112 where a top surface of the workpiece 200 is planarized (e.g., using CMP) to provide the level top surface 226. In some embodiments, and after the CMP process, the total thickness ‘T3’ of the second dielectric layer 222 may be between about 900 nm and about 1,500 nm. As illustrated in FIG. 19, the level top surface 226 includes a portion of the third dielectric layer 224 and a portion of the second dielectric layer 222.

Referring to FIGS. 14 and 20, the method 150